xref: /freebsd/sys/amd64/vmm/amd/svm_msr.c (revision 7d786ee2a9fe41aec8e1abad9e5bb89f16de5752)
18f02c5e4SNeel Natu /*-
28f02c5e4SNeel Natu  * Copyright (c) 2014, Neel Natu (neel@freebsd.org)
38f02c5e4SNeel Natu  * All rights reserved.
48f02c5e4SNeel Natu  *
58f02c5e4SNeel Natu  * Redistribution and use in source and binary forms, with or without
68f02c5e4SNeel Natu  * modification, are permitted provided that the following conditions
78f02c5e4SNeel Natu  * are met:
88f02c5e4SNeel Natu  * 1. Redistributions of source code must retain the above copyright
98f02c5e4SNeel Natu  *    notice unmodified, this list of conditions, and the following
108f02c5e4SNeel Natu  *    disclaimer.
118f02c5e4SNeel Natu  * 2. Redistributions in binary form must reproduce the above copyright
128f02c5e4SNeel Natu  *    notice, this list of conditions and the following disclaimer in the
138f02c5e4SNeel Natu  *    documentation and/or other materials provided with the distribution.
148f02c5e4SNeel Natu  *
158f02c5e4SNeel Natu  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
168f02c5e4SNeel Natu  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
178f02c5e4SNeel Natu  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
188f02c5e4SNeel Natu  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
198f02c5e4SNeel Natu  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
208f02c5e4SNeel Natu  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
218f02c5e4SNeel Natu  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
228f02c5e4SNeel Natu  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
238f02c5e4SNeel Natu  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
248f02c5e4SNeel Natu  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
258f02c5e4SNeel Natu  */
268f02c5e4SNeel Natu 
278f02c5e4SNeel Natu #include <sys/cdefs.h>
288f02c5e4SNeel Natu __FBSDID("$FreeBSD$");
298f02c5e4SNeel Natu 
30*7d786ee2SNeel Natu #include <sys/param.h>
318f02c5e4SNeel Natu #include <sys/errno.h>
32*7d786ee2SNeel Natu #include <sys/systm.h>
33*7d786ee2SNeel Natu #include <sys/cpuset.h>
348f02c5e4SNeel Natu 
358f02c5e4SNeel Natu #include <machine/cpufunc.h>
368f02c5e4SNeel Natu #include <machine/specialreg.h>
37*7d786ee2SNeel Natu #include <machine/vmm.h>
388f02c5e4SNeel Natu 
39*7d786ee2SNeel Natu #include "svm.h"
40*7d786ee2SNeel Natu #include "vmcb.h"
41*7d786ee2SNeel Natu #include "svm_softc.h"
428f02c5e4SNeel Natu #include "svm_msr.h"
438f02c5e4SNeel Natu 
448f02c5e4SNeel Natu #ifndef MSR_AMDK8_IPM
458f02c5e4SNeel Natu #define	MSR_AMDK8_IPM	0xc0010055
468f02c5e4SNeel Natu #endif
478f02c5e4SNeel Natu 
488f02c5e4SNeel Natu enum {
498f02c5e4SNeel Natu 	IDX_MSR_LSTAR,
508f02c5e4SNeel Natu 	IDX_MSR_CSTAR,
518f02c5e4SNeel Natu 	IDX_MSR_STAR,
528f02c5e4SNeel Natu 	IDX_MSR_SF_MASK,
538f02c5e4SNeel Natu 	HOST_MSR_NUM		/* must be the last enumeration */
548f02c5e4SNeel Natu };
558f02c5e4SNeel Natu 
568f02c5e4SNeel Natu static uint64_t host_msrs[HOST_MSR_NUM];
578f02c5e4SNeel Natu 
588f02c5e4SNeel Natu void
598f02c5e4SNeel Natu svm_msr_init(void)
608f02c5e4SNeel Natu {
618f02c5e4SNeel Natu 	/*
628f02c5e4SNeel Natu 	 * It is safe to cache the values of the following MSRs because they
638f02c5e4SNeel Natu 	 * don't change based on curcpu, curproc or curthread.
648f02c5e4SNeel Natu 	 */
658f02c5e4SNeel Natu 	host_msrs[IDX_MSR_LSTAR] = rdmsr(MSR_LSTAR);
668f02c5e4SNeel Natu 	host_msrs[IDX_MSR_CSTAR] = rdmsr(MSR_CSTAR);
678f02c5e4SNeel Natu 	host_msrs[IDX_MSR_STAR] = rdmsr(MSR_STAR);
688f02c5e4SNeel Natu 	host_msrs[IDX_MSR_SF_MASK] = rdmsr(MSR_SF_MASK);
698f02c5e4SNeel Natu }
708f02c5e4SNeel Natu 
718f02c5e4SNeel Natu void
728f02c5e4SNeel Natu svm_msr_guest_init(struct svm_softc *sc, int vcpu)
738f02c5e4SNeel Natu {
748f02c5e4SNeel Natu 	/*
758f02c5e4SNeel Natu 	 * All the MSRs accessible to the guest are either saved/restored by
768f02c5e4SNeel Natu 	 * hardware on every #VMEXIT/VMRUN (e.g., G_PAT) or are saved/restored
778f02c5e4SNeel Natu 	 * by VMSAVE/VMLOAD (e.g., MSR_GSBASE).
788f02c5e4SNeel Natu 	 *
798f02c5e4SNeel Natu 	 * There are no guest MSRs that are saved/restored "by hand" so nothing
808f02c5e4SNeel Natu 	 * more to do here.
818f02c5e4SNeel Natu 	 */
828f02c5e4SNeel Natu 	return;
838f02c5e4SNeel Natu }
848f02c5e4SNeel Natu 
858f02c5e4SNeel Natu void
868f02c5e4SNeel Natu svm_msr_guest_enter(struct svm_softc *sc, int vcpu)
878f02c5e4SNeel Natu {
888f02c5e4SNeel Natu 	/*
898f02c5e4SNeel Natu 	 * Save host MSRs (if any) and restore guest MSRs (if any).
908f02c5e4SNeel Natu 	 */
918f02c5e4SNeel Natu }
928f02c5e4SNeel Natu 
938f02c5e4SNeel Natu void
948f02c5e4SNeel Natu svm_msr_guest_exit(struct svm_softc *sc, int vcpu)
958f02c5e4SNeel Natu {
968f02c5e4SNeel Natu 	/*
978f02c5e4SNeel Natu 	 * Save guest MSRs (if any) and restore host MSRs.
988f02c5e4SNeel Natu 	 */
998f02c5e4SNeel Natu 	wrmsr(MSR_LSTAR, host_msrs[IDX_MSR_LSTAR]);
1008f02c5e4SNeel Natu 	wrmsr(MSR_CSTAR, host_msrs[IDX_MSR_CSTAR]);
1018f02c5e4SNeel Natu 	wrmsr(MSR_STAR, host_msrs[IDX_MSR_STAR]);
1028f02c5e4SNeel Natu 	wrmsr(MSR_SF_MASK, host_msrs[IDX_MSR_SF_MASK]);
1038f02c5e4SNeel Natu 
1048f02c5e4SNeel Natu 	/* MSR_KGSBASE will be restored on the way back to userspace */
1058f02c5e4SNeel Natu }
1068f02c5e4SNeel Natu 
1078f02c5e4SNeel Natu int
1088f02c5e4SNeel Natu svm_rdmsr(struct svm_softc *sc, int vcpu, u_int num, uint64_t *result,
1098f02c5e4SNeel Natu     bool *retu)
1108f02c5e4SNeel Natu {
1118f02c5e4SNeel Natu 	int error = 0;
1128f02c5e4SNeel Natu 
1138f02c5e4SNeel Natu 	switch (num) {
114*7d786ee2SNeel Natu 	case MSR_MTRRcap:
115*7d786ee2SNeel Natu 	case MSR_MTRRdefType:
116*7d786ee2SNeel Natu 	case MSR_MTRR4kBase ... MSR_MTRR4kBase + 8:
117*7d786ee2SNeel Natu 	case MSR_MTRR16kBase ... MSR_MTRR16kBase + 1:
118*7d786ee2SNeel Natu 	case MSR_MTRR64kBase:
119*7d786ee2SNeel Natu 		*result = 0;
120*7d786ee2SNeel Natu 		break;
1218f02c5e4SNeel Natu 	case MSR_AMDK8_IPM:
1228f02c5e4SNeel Natu 		*result = 0;
1238f02c5e4SNeel Natu 		break;
1248f02c5e4SNeel Natu 	default:
1258f02c5e4SNeel Natu 		error = EINVAL;
1268f02c5e4SNeel Natu 		break;
1278f02c5e4SNeel Natu 	}
1288f02c5e4SNeel Natu 
1298f02c5e4SNeel Natu 	return (error);
1308f02c5e4SNeel Natu }
1318f02c5e4SNeel Natu 
1328f02c5e4SNeel Natu int
1338f02c5e4SNeel Natu svm_wrmsr(struct svm_softc *sc, int vcpu, u_int num, uint64_t val, bool *retu)
1348f02c5e4SNeel Natu {
1358f02c5e4SNeel Natu 	int error = 0;
1368f02c5e4SNeel Natu 
1378f02c5e4SNeel Natu 	switch (num) {
138*7d786ee2SNeel Natu 	case MSR_MTRRcap:
139*7d786ee2SNeel Natu 		vm_inject_gp(sc->vm, vcpu);
140*7d786ee2SNeel Natu 		break;
141*7d786ee2SNeel Natu 	case MSR_MTRRdefType:
142*7d786ee2SNeel Natu 	case MSR_MTRR4kBase ... MSR_MTRR4kBase + 8:
143*7d786ee2SNeel Natu 	case MSR_MTRR16kBase ... MSR_MTRR16kBase + 1:
144*7d786ee2SNeel Natu 	case MSR_MTRR64kBase:
145*7d786ee2SNeel Natu 		break;		/* Ignore writes */
1468f02c5e4SNeel Natu 	case MSR_AMDK8_IPM:
1478f02c5e4SNeel Natu 		/*
1488f02c5e4SNeel Natu 		 * Ignore writes to the "Interrupt Pending Message" MSR.
1498f02c5e4SNeel Natu 		 */
1508f02c5e4SNeel Natu 		break;
1518f02c5e4SNeel Natu 	default:
1528f02c5e4SNeel Natu 		error = EINVAL;
1538f02c5e4SNeel Natu 		break;
1548f02c5e4SNeel Natu 	}
1558f02c5e4SNeel Natu 
1568f02c5e4SNeel Natu 	return (error);
1578f02c5e4SNeel Natu }
158