1 /*- 2 * Copyright (c) 2013, Anish Gupta (akgupt3@gmail.com) 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/smp.h> 33 #include <sys/kernel.h> 34 #include <sys/malloc.h> 35 #include <sys/pcpu.h> 36 #include <sys/proc.h> 37 #include <sys/sysctl.h> 38 39 #include <vm/vm.h> 40 #include <vm/pmap.h> 41 42 #include <machine/cpufunc.h> 43 #include <machine/psl.h> 44 #include <machine/pmap.h> 45 #include <machine/md_var.h> 46 #include <machine/specialreg.h> 47 #include <machine/smp.h> 48 #include <machine/vmm.h> 49 #include <machine/vmm_dev.h> 50 #include <machine/vmm_instruction_emul.h> 51 52 #include "vmm_lapic.h" 53 #include "vmm_stat.h" 54 #include "vmm_ktr.h" 55 #include "vmm_ioport.h" 56 #include "vatpic.h" 57 #include "vlapic.h" 58 #include "vlapic_priv.h" 59 60 #include "x86.h" 61 #include "vmcb.h" 62 #include "svm.h" 63 #include "svm_softc.h" 64 #include "svm_msr.h" 65 #include "npt.h" 66 67 SYSCTL_DECL(_hw_vmm); 68 SYSCTL_NODE(_hw_vmm, OID_AUTO, svm, CTLFLAG_RW, NULL, NULL); 69 70 /* 71 * SVM CPUID function 0x8000_000A, edx bit decoding. 72 */ 73 #define AMD_CPUID_SVM_NP BIT(0) /* Nested paging or RVI */ 74 #define AMD_CPUID_SVM_LBR BIT(1) /* Last branch virtualization */ 75 #define AMD_CPUID_SVM_SVML BIT(2) /* SVM lock */ 76 #define AMD_CPUID_SVM_NRIP_SAVE BIT(3) /* Next RIP is saved */ 77 #define AMD_CPUID_SVM_TSC_RATE BIT(4) /* TSC rate control. */ 78 #define AMD_CPUID_SVM_VMCB_CLEAN BIT(5) /* VMCB state caching */ 79 #define AMD_CPUID_SVM_FLUSH_BY_ASID BIT(6) /* Flush by ASID */ 80 #define AMD_CPUID_SVM_DECODE_ASSIST BIT(7) /* Decode assist */ 81 #define AMD_CPUID_SVM_PAUSE_INC BIT(10) /* Pause intercept filter. */ 82 #define AMD_CPUID_SVM_PAUSE_FTH BIT(12) /* Pause filter threshold */ 83 84 #define VMCB_CACHE_DEFAULT (VMCB_CACHE_ASID | \ 85 VMCB_CACHE_IOPM | \ 86 VMCB_CACHE_I | \ 87 VMCB_CACHE_TPR | \ 88 VMCB_CACHE_CR2 | \ 89 VMCB_CACHE_CR | \ 90 VMCB_CACHE_DT | \ 91 VMCB_CACHE_SEG | \ 92 VMCB_CACHE_NP) 93 94 static uint32_t vmcb_clean = VMCB_CACHE_DEFAULT; 95 SYSCTL_INT(_hw_vmm_svm, OID_AUTO, vmcb_clean, CTLFLAG_RDTUN, &vmcb_clean, 96 0, NULL); 97 98 static MALLOC_DEFINE(M_SVM, "svm", "svm"); 99 static MALLOC_DEFINE(M_SVM_VLAPIC, "svm-vlapic", "svm-vlapic"); 100 101 /* Per-CPU context area. */ 102 extern struct pcpu __pcpu[]; 103 104 static uint32_t svm_feature; /* AMD SVM features. */ 105 SYSCTL_UINT(_hw_vmm_svm, OID_AUTO, features, CTLFLAG_RD, &svm_feature, 0, 106 "SVM features advertised by CPUID.8000000AH:EDX"); 107 108 static int disable_npf_assist; 109 SYSCTL_INT(_hw_vmm_svm, OID_AUTO, disable_npf_assist, CTLFLAG_RWTUN, 110 &disable_npf_assist, 0, NULL); 111 112 /* Maximum ASIDs supported by the processor */ 113 static uint32_t nasid; 114 SYSCTL_UINT(_hw_vmm_svm, OID_AUTO, num_asids, CTLFLAG_RD, &nasid, 0, 115 "Number of ASIDs supported by this processor"); 116 117 /* Current ASID generation for each host cpu */ 118 static struct asid asid[MAXCPU]; 119 120 /* 121 * SVM host state saved area of size 4KB for each core. 122 */ 123 static uint8_t hsave[MAXCPU][PAGE_SIZE] __aligned(PAGE_SIZE); 124 125 static VMM_STAT_AMD(VCPU_EXITINTINFO, "VM exits during event delivery"); 126 static VMM_STAT_AMD(VCPU_INTINFO_INJECTED, "Events pending at VM entry"); 127 static VMM_STAT_AMD(VMEXIT_VINTR, "VM exits due to interrupt window"); 128 129 static int svm_setreg(void *arg, int vcpu, int ident, uint64_t val); 130 131 static __inline int 132 flush_by_asid(void) 133 { 134 135 return (svm_feature & AMD_CPUID_SVM_FLUSH_BY_ASID); 136 } 137 138 static __inline int 139 decode_assist(void) 140 { 141 142 return (svm_feature & AMD_CPUID_SVM_DECODE_ASSIST); 143 } 144 145 static void 146 svm_disable(void *arg __unused) 147 { 148 uint64_t efer; 149 150 efer = rdmsr(MSR_EFER); 151 efer &= ~EFER_SVM; 152 wrmsr(MSR_EFER, efer); 153 } 154 155 /* 156 * Disable SVM on all CPUs. 157 */ 158 static int 159 svm_cleanup(void) 160 { 161 162 smp_rendezvous(NULL, svm_disable, NULL, NULL); 163 return (0); 164 } 165 166 /* 167 * Verify that all the features required by bhyve are available. 168 */ 169 static int 170 check_svm_features(void) 171 { 172 u_int regs[4]; 173 174 /* CPUID Fn8000_000A is for SVM */ 175 do_cpuid(0x8000000A, regs); 176 svm_feature = regs[3]; 177 178 nasid = regs[1]; 179 KASSERT(nasid > 1, ("Insufficient ASIDs for guests: %#x", nasid)); 180 181 /* bhyve requires the Nested Paging feature */ 182 if (!(svm_feature & AMD_CPUID_SVM_NP)) { 183 printf("SVM: Nested Paging feature not available.\n"); 184 return (ENXIO); 185 } 186 187 /* bhyve requires the NRIP Save feature */ 188 if (!(svm_feature & AMD_CPUID_SVM_NRIP_SAVE)) { 189 printf("SVM: NRIP Save feature not available.\n"); 190 return (ENXIO); 191 } 192 193 return (0); 194 } 195 196 static void 197 svm_enable(void *arg __unused) 198 { 199 uint64_t efer; 200 201 efer = rdmsr(MSR_EFER); 202 efer |= EFER_SVM; 203 wrmsr(MSR_EFER, efer); 204 205 wrmsr(MSR_VM_HSAVE_PA, vtophys(hsave[curcpu])); 206 } 207 208 /* 209 * Return 1 if SVM is enabled on this processor and 0 otherwise. 210 */ 211 static int 212 svm_available(void) 213 { 214 uint64_t msr; 215 216 /* Section 15.4 Enabling SVM from APM2. */ 217 if ((amd_feature2 & AMDID2_SVM) == 0) { 218 printf("SVM: not available.\n"); 219 return (0); 220 } 221 222 msr = rdmsr(MSR_VM_CR); 223 if ((msr & VM_CR_SVMDIS) != 0) { 224 printf("SVM: disabled by BIOS.\n"); 225 return (0); 226 } 227 228 return (1); 229 } 230 231 static int 232 svm_init(int ipinum) 233 { 234 int error, cpu; 235 236 if (!svm_available()) 237 return (ENXIO); 238 239 error = check_svm_features(); 240 if (error) 241 return (error); 242 243 vmcb_clean &= VMCB_CACHE_DEFAULT; 244 245 for (cpu = 0; cpu < MAXCPU; cpu++) { 246 /* 247 * Initialize the host ASIDs to their "highest" valid values. 248 * 249 * The next ASID allocation will rollover both 'gen' and 'num' 250 * and start off the sequence at {1,1}. 251 */ 252 asid[cpu].gen = ~0UL; 253 asid[cpu].num = nasid - 1; 254 } 255 256 svm_msr_init(); 257 svm_npt_init(ipinum); 258 259 /* Enable SVM on all CPUs */ 260 smp_rendezvous(NULL, svm_enable, NULL, NULL); 261 262 return (0); 263 } 264 265 static void 266 svm_restore(void) 267 { 268 269 svm_enable(NULL); 270 } 271 272 /* Pentium compatible MSRs */ 273 #define MSR_PENTIUM_START 0 274 #define MSR_PENTIUM_END 0x1FFF 275 /* AMD 6th generation and Intel compatible MSRs */ 276 #define MSR_AMD6TH_START 0xC0000000UL 277 #define MSR_AMD6TH_END 0xC0001FFFUL 278 /* AMD 7th and 8th generation compatible MSRs */ 279 #define MSR_AMD7TH_START 0xC0010000UL 280 #define MSR_AMD7TH_END 0xC0011FFFUL 281 282 /* 283 * Get the index and bit position for a MSR in permission bitmap. 284 * Two bits are used for each MSR: lower bit for read and higher bit for write. 285 */ 286 static int 287 svm_msr_index(uint64_t msr, int *index, int *bit) 288 { 289 uint32_t base, off; 290 291 *index = -1; 292 *bit = (msr % 4) * 2; 293 base = 0; 294 295 if (msr >= MSR_PENTIUM_START && msr <= MSR_PENTIUM_END) { 296 *index = msr / 4; 297 return (0); 298 } 299 300 base += (MSR_PENTIUM_END - MSR_PENTIUM_START + 1); 301 if (msr >= MSR_AMD6TH_START && msr <= MSR_AMD6TH_END) { 302 off = (msr - MSR_AMD6TH_START); 303 *index = (off + base) / 4; 304 return (0); 305 } 306 307 base += (MSR_AMD6TH_END - MSR_AMD6TH_START + 1); 308 if (msr >= MSR_AMD7TH_START && msr <= MSR_AMD7TH_END) { 309 off = (msr - MSR_AMD7TH_START); 310 *index = (off + base) / 4; 311 return (0); 312 } 313 314 return (EINVAL); 315 } 316 317 /* 318 * Allow vcpu to read or write the 'msr' without trapping into the hypervisor. 319 */ 320 static void 321 svm_msr_perm(uint8_t *perm_bitmap, uint64_t msr, bool read, bool write) 322 { 323 int index, bit, error; 324 325 error = svm_msr_index(msr, &index, &bit); 326 KASSERT(error == 0, ("%s: invalid msr %#lx", __func__, msr)); 327 KASSERT(index >= 0 && index < SVM_MSR_BITMAP_SIZE, 328 ("%s: invalid index %d for msr %#lx", __func__, index, msr)); 329 KASSERT(bit >= 0 && bit <= 6, ("%s: invalid bit position %d " 330 "msr %#lx", __func__, bit, msr)); 331 332 if (read) 333 perm_bitmap[index] &= ~(1UL << bit); 334 335 if (write) 336 perm_bitmap[index] &= ~(2UL << bit); 337 } 338 339 static void 340 svm_msr_rw_ok(uint8_t *perm_bitmap, uint64_t msr) 341 { 342 343 svm_msr_perm(perm_bitmap, msr, true, true); 344 } 345 346 static void 347 svm_msr_rd_ok(uint8_t *perm_bitmap, uint64_t msr) 348 { 349 350 svm_msr_perm(perm_bitmap, msr, true, false); 351 } 352 353 static __inline int 354 svm_get_intercept(struct svm_softc *sc, int vcpu, int idx, uint32_t bitmask) 355 { 356 struct vmcb_ctrl *ctrl; 357 358 KASSERT(idx >=0 && idx < 5, ("invalid intercept index %d", idx)); 359 360 ctrl = svm_get_vmcb_ctrl(sc, vcpu); 361 return (ctrl->intercept[idx] & bitmask ? 1 : 0); 362 } 363 364 static __inline void 365 svm_set_intercept(struct svm_softc *sc, int vcpu, int idx, uint32_t bitmask, 366 int enabled) 367 { 368 struct vmcb_ctrl *ctrl; 369 uint32_t oldval; 370 371 KASSERT(idx >=0 && idx < 5, ("invalid intercept index %d", idx)); 372 373 ctrl = svm_get_vmcb_ctrl(sc, vcpu); 374 oldval = ctrl->intercept[idx]; 375 376 if (enabled) 377 ctrl->intercept[idx] |= bitmask; 378 else 379 ctrl->intercept[idx] &= ~bitmask; 380 381 if (ctrl->intercept[idx] != oldval) { 382 svm_set_dirty(sc, vcpu, VMCB_CACHE_I); 383 VCPU_CTR3(sc->vm, vcpu, "intercept[%d] modified " 384 "from %#x to %#x", idx, oldval, ctrl->intercept[idx]); 385 } 386 } 387 388 static __inline void 389 svm_disable_intercept(struct svm_softc *sc, int vcpu, int off, uint32_t bitmask) 390 { 391 392 svm_set_intercept(sc, vcpu, off, bitmask, 0); 393 } 394 395 static __inline void 396 svm_enable_intercept(struct svm_softc *sc, int vcpu, int off, uint32_t bitmask) 397 { 398 399 svm_set_intercept(sc, vcpu, off, bitmask, 1); 400 } 401 402 static void 403 vmcb_init(struct svm_softc *sc, int vcpu, uint64_t iopm_base_pa, 404 uint64_t msrpm_base_pa, uint64_t np_pml4) 405 { 406 struct vmcb_ctrl *ctrl; 407 struct vmcb_state *state; 408 uint32_t mask; 409 int n; 410 411 ctrl = svm_get_vmcb_ctrl(sc, vcpu); 412 state = svm_get_vmcb_state(sc, vcpu); 413 414 ctrl->iopm_base_pa = iopm_base_pa; 415 ctrl->msrpm_base_pa = msrpm_base_pa; 416 417 /* Enable nested paging */ 418 ctrl->np_enable = 1; 419 ctrl->n_cr3 = np_pml4; 420 421 /* 422 * Intercept accesses to the control registers that are not shadowed 423 * in the VMCB - i.e. all except cr0, cr2, cr3, cr4 and cr8. 424 */ 425 for (n = 0; n < 16; n++) { 426 mask = (BIT(n) << 16) | BIT(n); 427 if (n == 0 || n == 2 || n == 3 || n == 4 || n == 8) 428 svm_disable_intercept(sc, vcpu, VMCB_CR_INTCPT, mask); 429 else 430 svm_enable_intercept(sc, vcpu, VMCB_CR_INTCPT, mask); 431 } 432 433 434 /* 435 * Intercept everything when tracing guest exceptions otherwise 436 * just intercept machine check exception. 437 */ 438 if (vcpu_trace_exceptions(sc->vm, vcpu)) { 439 for (n = 0; n < 32; n++) { 440 /* 441 * Skip unimplemented vectors in the exception bitmap. 442 */ 443 if (n == 2 || n == 9) { 444 continue; 445 } 446 svm_enable_intercept(sc, vcpu, VMCB_EXC_INTCPT, BIT(n)); 447 } 448 } else { 449 svm_enable_intercept(sc, vcpu, VMCB_EXC_INTCPT, BIT(IDT_MC)); 450 } 451 452 /* Intercept various events (for e.g. I/O, MSR and CPUID accesses) */ 453 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_IO); 454 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_MSR); 455 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_CPUID); 456 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_INTR); 457 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_INIT); 458 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_NMI); 459 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_SMI); 460 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_SHUTDOWN); 461 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, 462 VMCB_INTCPT_FERR_FREEZE); 463 464 svm_enable_intercept(sc, vcpu, VMCB_CTRL2_INTCPT, VMCB_INTCPT_MONITOR); 465 svm_enable_intercept(sc, vcpu, VMCB_CTRL2_INTCPT, VMCB_INTCPT_MWAIT); 466 467 /* 468 * From section "Canonicalization and Consistency Checks" in APMv2 469 * the VMRUN intercept bit must be set to pass the consistency check. 470 */ 471 svm_enable_intercept(sc, vcpu, VMCB_CTRL2_INTCPT, VMCB_INTCPT_VMRUN); 472 473 /* 474 * The ASID will be set to a non-zero value just before VMRUN. 475 */ 476 ctrl->asid = 0; 477 478 /* 479 * Section 15.21.1, Interrupt Masking in EFLAGS 480 * Section 15.21.2, Virtualizing APIC.TPR 481 * 482 * This must be set for %rflag and %cr8 isolation of guest and host. 483 */ 484 ctrl->v_intr_masking = 1; 485 486 /* Enable Last Branch Record aka LBR for debugging */ 487 ctrl->lbr_virt_en = 1; 488 state->dbgctl = BIT(0); 489 490 /* EFER_SVM must always be set when the guest is executing */ 491 state->efer = EFER_SVM; 492 493 /* Set up the PAT to power-on state */ 494 state->g_pat = PAT_VALUE(0, PAT_WRITE_BACK) | 495 PAT_VALUE(1, PAT_WRITE_THROUGH) | 496 PAT_VALUE(2, PAT_UNCACHED) | 497 PAT_VALUE(3, PAT_UNCACHEABLE) | 498 PAT_VALUE(4, PAT_WRITE_BACK) | 499 PAT_VALUE(5, PAT_WRITE_THROUGH) | 500 PAT_VALUE(6, PAT_UNCACHED) | 501 PAT_VALUE(7, PAT_UNCACHEABLE); 502 } 503 504 /* 505 * Initialize a virtual machine. 506 */ 507 static void * 508 svm_vminit(struct vm *vm, pmap_t pmap) 509 { 510 struct svm_softc *svm_sc; 511 struct svm_vcpu *vcpu; 512 vm_paddr_t msrpm_pa, iopm_pa, pml4_pa; 513 int i; 514 515 svm_sc = malloc(sizeof (struct svm_softc), M_SVM, M_WAITOK | M_ZERO); 516 svm_sc->vm = vm; 517 svm_sc->nptp = (vm_offset_t)vtophys(pmap->pm_pml4); 518 519 /* 520 * Intercept read and write accesses to all MSRs. 521 */ 522 memset(svm_sc->msr_bitmap, 0xFF, sizeof(svm_sc->msr_bitmap)); 523 524 /* 525 * Access to the following MSRs is redirected to the VMCB when the 526 * guest is executing. Therefore it is safe to allow the guest to 527 * read/write these MSRs directly without hypervisor involvement. 528 */ 529 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_GSBASE); 530 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_FSBASE); 531 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_KGSBASE); 532 533 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_STAR); 534 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_LSTAR); 535 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_CSTAR); 536 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_SF_MASK); 537 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_SYSENTER_CS_MSR); 538 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_SYSENTER_ESP_MSR); 539 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_SYSENTER_EIP_MSR); 540 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_PAT); 541 542 svm_msr_rd_ok(svm_sc->msr_bitmap, MSR_TSC); 543 544 /* 545 * Intercept writes to make sure that the EFER_SVM bit is not cleared. 546 */ 547 svm_msr_rd_ok(svm_sc->msr_bitmap, MSR_EFER); 548 549 /* Intercept access to all I/O ports. */ 550 memset(svm_sc->iopm_bitmap, 0xFF, sizeof(svm_sc->iopm_bitmap)); 551 552 iopm_pa = vtophys(svm_sc->iopm_bitmap); 553 msrpm_pa = vtophys(svm_sc->msr_bitmap); 554 pml4_pa = svm_sc->nptp; 555 for (i = 0; i < VM_MAXCPU; i++) { 556 vcpu = svm_get_vcpu(svm_sc, i); 557 vcpu->nextrip = ~0; 558 vcpu->lastcpu = NOCPU; 559 vcpu->vmcb_pa = vtophys(&vcpu->vmcb); 560 vmcb_init(svm_sc, i, iopm_pa, msrpm_pa, pml4_pa); 561 svm_msr_guest_init(svm_sc, i); 562 } 563 return (svm_sc); 564 } 565 566 static int 567 svm_cpl(struct vmcb_state *state) 568 { 569 570 /* 571 * From APMv2: 572 * "Retrieve the CPL from the CPL field in the VMCB, not 573 * from any segment DPL" 574 */ 575 return (state->cpl); 576 } 577 578 static enum vm_cpu_mode 579 svm_vcpu_mode(struct vmcb *vmcb) 580 { 581 struct vmcb_segment seg; 582 struct vmcb_state *state; 583 int error; 584 585 state = &vmcb->state; 586 587 if (state->efer & EFER_LMA) { 588 error = vmcb_seg(vmcb, VM_REG_GUEST_CS, &seg); 589 KASSERT(error == 0, ("%s: vmcb_seg(cs) error %d", __func__, 590 error)); 591 592 /* 593 * Section 4.8.1 for APM2, check if Code Segment has 594 * Long attribute set in descriptor. 595 */ 596 if (seg.attrib & VMCB_CS_ATTRIB_L) 597 return (CPU_MODE_64BIT); 598 else 599 return (CPU_MODE_COMPATIBILITY); 600 } else if (state->cr0 & CR0_PE) { 601 return (CPU_MODE_PROTECTED); 602 } else { 603 return (CPU_MODE_REAL); 604 } 605 } 606 607 static enum vm_paging_mode 608 svm_paging_mode(uint64_t cr0, uint64_t cr4, uint64_t efer) 609 { 610 611 if ((cr0 & CR0_PG) == 0) 612 return (PAGING_MODE_FLAT); 613 if ((cr4 & CR4_PAE) == 0) 614 return (PAGING_MODE_32); 615 if (efer & EFER_LME) 616 return (PAGING_MODE_64); 617 else 618 return (PAGING_MODE_PAE); 619 } 620 621 /* 622 * ins/outs utility routines 623 */ 624 static uint64_t 625 svm_inout_str_index(struct svm_regctx *regs, int in) 626 { 627 uint64_t val; 628 629 val = in ? regs->sctx_rdi : regs->sctx_rsi; 630 631 return (val); 632 } 633 634 static uint64_t 635 svm_inout_str_count(struct svm_regctx *regs, int rep) 636 { 637 uint64_t val; 638 639 val = rep ? regs->sctx_rcx : 1; 640 641 return (val); 642 } 643 644 static void 645 svm_inout_str_seginfo(struct svm_softc *svm_sc, int vcpu, int64_t info1, 646 int in, struct vm_inout_str *vis) 647 { 648 int error, s; 649 650 if (in) { 651 vis->seg_name = VM_REG_GUEST_ES; 652 } else { 653 /* The segment field has standard encoding */ 654 s = (info1 >> 10) & 0x7; 655 vis->seg_name = vm_segment_name(s); 656 } 657 658 error = vmcb_getdesc(svm_sc, vcpu, vis->seg_name, &vis->seg_desc); 659 KASSERT(error == 0, ("%s: svm_getdesc error %d", __func__, error)); 660 } 661 662 static int 663 svm_inout_str_addrsize(uint64_t info1) 664 { 665 uint32_t size; 666 667 size = (info1 >> 7) & 0x7; 668 switch (size) { 669 case 1: 670 return (2); /* 16 bit */ 671 case 2: 672 return (4); /* 32 bit */ 673 case 4: 674 return (8); /* 64 bit */ 675 default: 676 panic("%s: invalid size encoding %d", __func__, size); 677 } 678 } 679 680 static void 681 svm_paging_info(struct vmcb *vmcb, struct vm_guest_paging *paging) 682 { 683 struct vmcb_state *state; 684 685 state = &vmcb->state; 686 paging->cr3 = state->cr3; 687 paging->cpl = svm_cpl(state); 688 paging->cpu_mode = svm_vcpu_mode(vmcb); 689 paging->paging_mode = svm_paging_mode(state->cr0, state->cr4, 690 state->efer); 691 } 692 693 #define UNHANDLED 0 694 695 /* 696 * Handle guest I/O intercept. 697 */ 698 static int 699 svm_handle_io(struct svm_softc *svm_sc, int vcpu, struct vm_exit *vmexit) 700 { 701 struct vmcb_ctrl *ctrl; 702 struct vmcb_state *state; 703 struct svm_regctx *regs; 704 struct vm_inout_str *vis; 705 uint64_t info1; 706 int inout_string; 707 708 state = svm_get_vmcb_state(svm_sc, vcpu); 709 ctrl = svm_get_vmcb_ctrl(svm_sc, vcpu); 710 regs = svm_get_guest_regctx(svm_sc, vcpu); 711 712 info1 = ctrl->exitinfo1; 713 inout_string = info1 & BIT(2) ? 1 : 0; 714 715 /* 716 * The effective segment number in EXITINFO1[12:10] is populated 717 * only if the processor has the DecodeAssist capability. 718 * 719 * XXX this is not specified explicitly in APMv2 but can be verified 720 * empirically. 721 */ 722 if (inout_string && !decode_assist()) 723 return (UNHANDLED); 724 725 vmexit->exitcode = VM_EXITCODE_INOUT; 726 vmexit->u.inout.in = (info1 & BIT(0)) ? 1 : 0; 727 vmexit->u.inout.string = inout_string; 728 vmexit->u.inout.rep = (info1 & BIT(3)) ? 1 : 0; 729 vmexit->u.inout.bytes = (info1 >> 4) & 0x7; 730 vmexit->u.inout.port = (uint16_t)(info1 >> 16); 731 vmexit->u.inout.eax = (uint32_t)(state->rax); 732 733 if (inout_string) { 734 vmexit->exitcode = VM_EXITCODE_INOUT_STR; 735 vis = &vmexit->u.inout_str; 736 svm_paging_info(svm_get_vmcb(svm_sc, vcpu), &vis->paging); 737 vis->rflags = state->rflags; 738 vis->cr0 = state->cr0; 739 vis->index = svm_inout_str_index(regs, vmexit->u.inout.in); 740 vis->count = svm_inout_str_count(regs, vmexit->u.inout.rep); 741 vis->addrsize = svm_inout_str_addrsize(info1); 742 svm_inout_str_seginfo(svm_sc, vcpu, info1, 743 vmexit->u.inout.in, vis); 744 } 745 746 return (UNHANDLED); 747 } 748 749 static int 750 npf_fault_type(uint64_t exitinfo1) 751 { 752 753 if (exitinfo1 & VMCB_NPF_INFO1_W) 754 return (VM_PROT_WRITE); 755 else if (exitinfo1 & VMCB_NPF_INFO1_ID) 756 return (VM_PROT_EXECUTE); 757 else 758 return (VM_PROT_READ); 759 } 760 761 static bool 762 svm_npf_emul_fault(uint64_t exitinfo1) 763 { 764 765 if (exitinfo1 & VMCB_NPF_INFO1_ID) { 766 return (false); 767 } 768 769 if (exitinfo1 & VMCB_NPF_INFO1_GPT) { 770 return (false); 771 } 772 773 if ((exitinfo1 & VMCB_NPF_INFO1_GPA) == 0) { 774 return (false); 775 } 776 777 return (true); 778 } 779 780 static void 781 svm_handle_inst_emul(struct vmcb *vmcb, uint64_t gpa, struct vm_exit *vmexit) 782 { 783 struct vm_guest_paging *paging; 784 struct vmcb_segment seg; 785 struct vmcb_ctrl *ctrl; 786 char *inst_bytes; 787 int error, inst_len; 788 789 ctrl = &vmcb->ctrl; 790 paging = &vmexit->u.inst_emul.paging; 791 792 vmexit->exitcode = VM_EXITCODE_INST_EMUL; 793 vmexit->u.inst_emul.gpa = gpa; 794 vmexit->u.inst_emul.gla = VIE_INVALID_GLA; 795 svm_paging_info(vmcb, paging); 796 797 error = vmcb_seg(vmcb, VM_REG_GUEST_CS, &seg); 798 KASSERT(error == 0, ("%s: vmcb_seg(CS) error %d", __func__, error)); 799 800 switch(paging->cpu_mode) { 801 case CPU_MODE_PROTECTED: 802 case CPU_MODE_COMPATIBILITY: 803 /* 804 * Section 4.8.1 of APM2, Default Operand Size or D bit. 805 */ 806 vmexit->u.inst_emul.cs_d = (seg.attrib & VMCB_CS_ATTRIB_D) ? 807 1 : 0; 808 break; 809 default: 810 vmexit->u.inst_emul.cs_d = 0; 811 break; 812 } 813 814 /* 815 * Copy the instruction bytes into 'vie' if available. 816 */ 817 if (decode_assist() && !disable_npf_assist) { 818 inst_len = ctrl->inst_len; 819 inst_bytes = ctrl->inst_bytes; 820 } else { 821 inst_len = 0; 822 inst_bytes = NULL; 823 } 824 vie_init(&vmexit->u.inst_emul.vie, inst_bytes, inst_len); 825 } 826 827 #ifdef KTR 828 static const char * 829 intrtype_to_str(int intr_type) 830 { 831 switch (intr_type) { 832 case VMCB_EVENTINJ_TYPE_INTR: 833 return ("hwintr"); 834 case VMCB_EVENTINJ_TYPE_NMI: 835 return ("nmi"); 836 case VMCB_EVENTINJ_TYPE_INTn: 837 return ("swintr"); 838 case VMCB_EVENTINJ_TYPE_EXCEPTION: 839 return ("exception"); 840 default: 841 panic("%s: unknown intr_type %d", __func__, intr_type); 842 } 843 } 844 #endif 845 846 /* 847 * Inject an event to vcpu as described in section 15.20, "Event injection". 848 */ 849 static void 850 svm_eventinject(struct svm_softc *sc, int vcpu, int intr_type, int vector, 851 uint32_t error, bool ec_valid) 852 { 853 struct vmcb_ctrl *ctrl; 854 855 ctrl = svm_get_vmcb_ctrl(sc, vcpu); 856 857 KASSERT((ctrl->eventinj & VMCB_EVENTINJ_VALID) == 0, 858 ("%s: event already pending %#lx", __func__, ctrl->eventinj)); 859 860 KASSERT(vector >=0 && vector <= 255, ("%s: invalid vector %d", 861 __func__, vector)); 862 863 switch (intr_type) { 864 case VMCB_EVENTINJ_TYPE_INTR: 865 case VMCB_EVENTINJ_TYPE_NMI: 866 case VMCB_EVENTINJ_TYPE_INTn: 867 break; 868 case VMCB_EVENTINJ_TYPE_EXCEPTION: 869 if (vector >= 0 && vector <= 31 && vector != 2) 870 break; 871 /* FALLTHROUGH */ 872 default: 873 panic("%s: invalid intr_type/vector: %d/%d", __func__, 874 intr_type, vector); 875 } 876 ctrl->eventinj = vector | (intr_type << 8) | VMCB_EVENTINJ_VALID; 877 if (ec_valid) { 878 ctrl->eventinj |= VMCB_EVENTINJ_EC_VALID; 879 ctrl->eventinj |= (uint64_t)error << 32; 880 VCPU_CTR3(sc->vm, vcpu, "Injecting %s at vector %d errcode %#x", 881 intrtype_to_str(intr_type), vector, error); 882 } else { 883 VCPU_CTR2(sc->vm, vcpu, "Injecting %s at vector %d", 884 intrtype_to_str(intr_type), vector); 885 } 886 } 887 888 static void 889 svm_update_virqinfo(struct svm_softc *sc, int vcpu) 890 { 891 struct vm *vm; 892 struct vlapic *vlapic; 893 struct vmcb_ctrl *ctrl; 894 int pending; 895 896 vm = sc->vm; 897 vlapic = vm_lapic(vm, vcpu); 898 ctrl = svm_get_vmcb_ctrl(sc, vcpu); 899 900 /* Update %cr8 in the emulated vlapic */ 901 vlapic_set_cr8(vlapic, ctrl->v_tpr); 902 903 /* 904 * If V_IRQ indicates that the interrupt injection attempted on then 905 * last VMRUN was successful then update the vlapic accordingly. 906 */ 907 if (ctrl->v_intr_vector != 0) { 908 pending = ctrl->v_irq; 909 KASSERT(ctrl->v_intr_vector >= 16, ("%s: invalid " 910 "v_intr_vector %d", __func__, ctrl->v_intr_vector)); 911 KASSERT(!ctrl->v_ign_tpr, ("%s: invalid v_ign_tpr", __func__)); 912 VCPU_CTR2(vm, vcpu, "v_intr_vector %d %s", ctrl->v_intr_vector, 913 pending ? "pending" : "accepted"); 914 if (!pending) 915 vlapic_intr_accepted(vlapic, ctrl->v_intr_vector); 916 } 917 } 918 919 static void 920 svm_save_intinfo(struct svm_softc *svm_sc, int vcpu) 921 { 922 struct vmcb_ctrl *ctrl; 923 uint64_t intinfo; 924 925 ctrl = svm_get_vmcb_ctrl(svm_sc, vcpu); 926 intinfo = ctrl->exitintinfo; 927 if (!VMCB_EXITINTINFO_VALID(intinfo)) 928 return; 929 930 /* 931 * From APMv2, Section "Intercepts during IDT interrupt delivery" 932 * 933 * If a #VMEXIT happened during event delivery then record the event 934 * that was being delivered. 935 */ 936 VCPU_CTR2(svm_sc->vm, vcpu, "SVM:Pending INTINFO(0x%lx), vector=%d.\n", 937 intinfo, VMCB_EXITINTINFO_VECTOR(intinfo)); 938 vmm_stat_incr(svm_sc->vm, vcpu, VCPU_EXITINTINFO, 1); 939 vm_exit_intinfo(svm_sc->vm, vcpu, intinfo); 940 } 941 942 static __inline int 943 vintr_intercept_enabled(struct svm_softc *sc, int vcpu) 944 { 945 946 return (svm_get_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, 947 VMCB_INTCPT_VINTR)); 948 } 949 950 static __inline void 951 enable_intr_window_exiting(struct svm_softc *sc, int vcpu) 952 { 953 struct vmcb_ctrl *ctrl; 954 955 ctrl = svm_get_vmcb_ctrl(sc, vcpu); 956 957 if (ctrl->v_irq && ctrl->v_intr_vector == 0) { 958 KASSERT(ctrl->v_ign_tpr, ("%s: invalid v_ign_tpr", __func__)); 959 KASSERT(vintr_intercept_enabled(sc, vcpu), 960 ("%s: vintr intercept should be enabled", __func__)); 961 return; 962 } 963 964 VCPU_CTR0(sc->vm, vcpu, "Enable intr window exiting"); 965 ctrl->v_irq = 1; 966 ctrl->v_ign_tpr = 1; 967 ctrl->v_intr_vector = 0; 968 svm_set_dirty(sc, vcpu, VMCB_CACHE_TPR); 969 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_VINTR); 970 } 971 972 static __inline void 973 disable_intr_window_exiting(struct svm_softc *sc, int vcpu) 974 { 975 struct vmcb_ctrl *ctrl; 976 977 ctrl = svm_get_vmcb_ctrl(sc, vcpu); 978 979 if (!ctrl->v_irq && ctrl->v_intr_vector == 0) { 980 KASSERT(!vintr_intercept_enabled(sc, vcpu), 981 ("%s: vintr intercept should be disabled", __func__)); 982 return; 983 } 984 985 #ifdef KTR 986 if (ctrl->v_intr_vector == 0) 987 VCPU_CTR0(sc->vm, vcpu, "Disable intr window exiting"); 988 else 989 VCPU_CTR0(sc->vm, vcpu, "Clearing V_IRQ interrupt injection"); 990 #endif 991 ctrl->v_irq = 0; 992 ctrl->v_intr_vector = 0; 993 svm_set_dirty(sc, vcpu, VMCB_CACHE_TPR); 994 svm_disable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_VINTR); 995 } 996 997 static int 998 svm_modify_intr_shadow(struct svm_softc *sc, int vcpu, uint64_t val) 999 { 1000 struct vmcb_ctrl *ctrl; 1001 int oldval, newval; 1002 1003 ctrl = svm_get_vmcb_ctrl(sc, vcpu); 1004 oldval = ctrl->intr_shadow; 1005 newval = val ? 1 : 0; 1006 if (newval != oldval) { 1007 ctrl->intr_shadow = newval; 1008 VCPU_CTR1(sc->vm, vcpu, "Setting intr_shadow to %d", newval); 1009 } 1010 return (0); 1011 } 1012 1013 static int 1014 svm_get_intr_shadow(struct svm_softc *sc, int vcpu, uint64_t *val) 1015 { 1016 struct vmcb_ctrl *ctrl; 1017 1018 ctrl = svm_get_vmcb_ctrl(sc, vcpu); 1019 *val = ctrl->intr_shadow; 1020 return (0); 1021 } 1022 1023 /* 1024 * Once an NMI is injected it blocks delivery of further NMIs until the handler 1025 * executes an IRET. The IRET intercept is enabled when an NMI is injected to 1026 * to track when the vcpu is done handling the NMI. 1027 */ 1028 static int 1029 nmi_blocked(struct svm_softc *sc, int vcpu) 1030 { 1031 int blocked; 1032 1033 blocked = svm_get_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, 1034 VMCB_INTCPT_IRET); 1035 return (blocked); 1036 } 1037 1038 static void 1039 enable_nmi_blocking(struct svm_softc *sc, int vcpu) 1040 { 1041 1042 KASSERT(!nmi_blocked(sc, vcpu), ("vNMI already blocked")); 1043 VCPU_CTR0(sc->vm, vcpu, "vNMI blocking enabled"); 1044 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_IRET); 1045 } 1046 1047 static void 1048 clear_nmi_blocking(struct svm_softc *sc, int vcpu) 1049 { 1050 int error; 1051 1052 KASSERT(nmi_blocked(sc, vcpu), ("vNMI already unblocked")); 1053 VCPU_CTR0(sc->vm, vcpu, "vNMI blocking cleared"); 1054 /* 1055 * When the IRET intercept is cleared the vcpu will attempt to execute 1056 * the "iret" when it runs next. However, it is possible to inject 1057 * another NMI into the vcpu before the "iret" has actually executed. 1058 * 1059 * For e.g. if the "iret" encounters a #NPF when accessing the stack 1060 * it will trap back into the hypervisor. If an NMI is pending for 1061 * the vcpu it will be injected into the guest. 1062 * 1063 * XXX this needs to be fixed 1064 */ 1065 svm_disable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_IRET); 1066 1067 /* 1068 * Set 'intr_shadow' to prevent an NMI from being injected on the 1069 * immediate VMRUN. 1070 */ 1071 error = svm_modify_intr_shadow(sc, vcpu, 1); 1072 KASSERT(!error, ("%s: error %d setting intr_shadow", __func__, error)); 1073 } 1074 1075 static int 1076 emulate_wrmsr(struct svm_softc *sc, int vcpu, u_int num, uint64_t val, 1077 bool *retu) 1078 { 1079 int error; 1080 1081 if (lapic_msr(num)) 1082 error = lapic_wrmsr(sc->vm, vcpu, num, val, retu); 1083 else if (num == MSR_EFER) 1084 error = svm_setreg(sc, vcpu, VM_REG_GUEST_EFER, val); 1085 else 1086 error = svm_wrmsr(sc, vcpu, num, val, retu); 1087 1088 return (error); 1089 } 1090 1091 static int 1092 emulate_rdmsr(struct svm_softc *sc, int vcpu, u_int num, bool *retu) 1093 { 1094 struct vmcb_state *state; 1095 struct svm_regctx *ctx; 1096 uint64_t result; 1097 int error; 1098 1099 if (lapic_msr(num)) 1100 error = lapic_rdmsr(sc->vm, vcpu, num, &result, retu); 1101 else 1102 error = svm_rdmsr(sc, vcpu, num, &result, retu); 1103 1104 if (error == 0) { 1105 state = svm_get_vmcb_state(sc, vcpu); 1106 ctx = svm_get_guest_regctx(sc, vcpu); 1107 state->rax = result & 0xffffffff; 1108 ctx->sctx_rdx = result >> 32; 1109 } 1110 1111 return (error); 1112 } 1113 1114 #ifdef KTR 1115 static const char * 1116 exit_reason_to_str(uint64_t reason) 1117 { 1118 static char reasonbuf[32]; 1119 1120 switch (reason) { 1121 case VMCB_EXIT_INVALID: 1122 return ("invalvmcb"); 1123 case VMCB_EXIT_SHUTDOWN: 1124 return ("shutdown"); 1125 case VMCB_EXIT_NPF: 1126 return ("nptfault"); 1127 case VMCB_EXIT_PAUSE: 1128 return ("pause"); 1129 case VMCB_EXIT_HLT: 1130 return ("hlt"); 1131 case VMCB_EXIT_CPUID: 1132 return ("cpuid"); 1133 case VMCB_EXIT_IO: 1134 return ("inout"); 1135 case VMCB_EXIT_MC: 1136 return ("mchk"); 1137 case VMCB_EXIT_INTR: 1138 return ("extintr"); 1139 case VMCB_EXIT_NMI: 1140 return ("nmi"); 1141 case VMCB_EXIT_VINTR: 1142 return ("vintr"); 1143 case VMCB_EXIT_MSR: 1144 return ("msr"); 1145 case VMCB_EXIT_IRET: 1146 return ("iret"); 1147 case VMCB_EXIT_MONITOR: 1148 return ("monitor"); 1149 case VMCB_EXIT_MWAIT: 1150 return ("mwait"); 1151 default: 1152 snprintf(reasonbuf, sizeof(reasonbuf), "%#lx", reason); 1153 return (reasonbuf); 1154 } 1155 } 1156 #endif /* KTR */ 1157 1158 /* 1159 * From section "State Saved on Exit" in APMv2: nRIP is saved for all #VMEXITs 1160 * that are due to instruction intercepts as well as MSR and IOIO intercepts 1161 * and exceptions caused by INT3, INTO and BOUND instructions. 1162 * 1163 * Return 1 if the nRIP is valid and 0 otherwise. 1164 */ 1165 static int 1166 nrip_valid(uint64_t exitcode) 1167 { 1168 switch (exitcode) { 1169 case 0x00 ... 0x0F: /* read of CR0 through CR15 */ 1170 case 0x10 ... 0x1F: /* write of CR0 through CR15 */ 1171 case 0x20 ... 0x2F: /* read of DR0 through DR15 */ 1172 case 0x30 ... 0x3F: /* write of DR0 through DR15 */ 1173 case 0x43: /* INT3 */ 1174 case 0x44: /* INTO */ 1175 case 0x45: /* BOUND */ 1176 case 0x65 ... 0x7C: /* VMEXIT_CR0_SEL_WRITE ... VMEXIT_MSR */ 1177 case 0x80 ... 0x8D: /* VMEXIT_VMRUN ... VMEXIT_XSETBV */ 1178 return (1); 1179 default: 1180 return (0); 1181 } 1182 } 1183 1184 /* 1185 * Collateral for a generic SVM VM-exit. 1186 */ 1187 static void 1188 vm_exit_svm(struct vm_exit *vme, uint64_t code, uint64_t info1, uint64_t info2) 1189 { 1190 1191 vme->exitcode = VM_EXITCODE_SVM; 1192 vme->u.svm.exitcode = code; 1193 vme->u.svm.exitinfo1 = info1; 1194 vme->u.svm.exitinfo2 = info2; 1195 } 1196 1197 static int 1198 svm_vmexit(struct svm_softc *svm_sc, int vcpu, struct vm_exit *vmexit) 1199 { 1200 struct vmcb *vmcb; 1201 struct vmcb_state *state; 1202 struct vmcb_ctrl *ctrl; 1203 struct svm_regctx *ctx; 1204 uint64_t code, info1, info2, val; 1205 uint32_t eax, ecx, edx; 1206 int error, errcode_valid, handled, idtvec, reflect; 1207 bool retu; 1208 1209 ctx = svm_get_guest_regctx(svm_sc, vcpu); 1210 vmcb = svm_get_vmcb(svm_sc, vcpu); 1211 state = &vmcb->state; 1212 ctrl = &vmcb->ctrl; 1213 1214 handled = 0; 1215 code = ctrl->exitcode; 1216 info1 = ctrl->exitinfo1; 1217 info2 = ctrl->exitinfo2; 1218 1219 vmexit->exitcode = VM_EXITCODE_BOGUS; 1220 vmexit->rip = state->rip; 1221 vmexit->inst_length = nrip_valid(code) ? ctrl->nrip - state->rip : 0; 1222 1223 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_COUNT, 1); 1224 1225 /* 1226 * #VMEXIT(INVALID) needs to be handled early because the VMCB is 1227 * in an inconsistent state and can trigger assertions that would 1228 * never happen otherwise. 1229 */ 1230 if (code == VMCB_EXIT_INVALID) { 1231 vm_exit_svm(vmexit, code, info1, info2); 1232 return (0); 1233 } 1234 1235 KASSERT((ctrl->eventinj & VMCB_EVENTINJ_VALID) == 0, ("%s: event " 1236 "injection valid bit is set %#lx", __func__, ctrl->eventinj)); 1237 1238 KASSERT(vmexit->inst_length >= 0 && vmexit->inst_length <= 15, 1239 ("invalid inst_length %d: code (%#lx), info1 (%#lx), info2 (%#lx)", 1240 vmexit->inst_length, code, info1, info2)); 1241 1242 svm_update_virqinfo(svm_sc, vcpu); 1243 svm_save_intinfo(svm_sc, vcpu); 1244 1245 switch (code) { 1246 case VMCB_EXIT_IRET: 1247 /* 1248 * Restart execution at "iret" but with the intercept cleared. 1249 */ 1250 vmexit->inst_length = 0; 1251 clear_nmi_blocking(svm_sc, vcpu); 1252 handled = 1; 1253 break; 1254 case VMCB_EXIT_VINTR: /* interrupt window exiting */ 1255 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_VINTR, 1); 1256 handled = 1; 1257 break; 1258 case VMCB_EXIT_INTR: /* external interrupt */ 1259 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_EXTINT, 1); 1260 handled = 1; 1261 break; 1262 case VMCB_EXIT_NMI: /* external NMI */ 1263 handled = 1; 1264 break; 1265 case 0x40 ... 0x5F: 1266 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_EXCEPTION, 1); 1267 reflect = 1; 1268 idtvec = code - 0x40; 1269 switch (idtvec) { 1270 case IDT_MC: 1271 /* 1272 * Call the machine check handler by hand. Also don't 1273 * reflect the machine check back into the guest. 1274 */ 1275 reflect = 0; 1276 VCPU_CTR0(svm_sc->vm, vcpu, "Vectoring to MCE handler"); 1277 __asm __volatile("int $18"); 1278 break; 1279 case IDT_PF: 1280 error = svm_setreg(svm_sc, vcpu, VM_REG_GUEST_CR2, 1281 info2); 1282 KASSERT(error == 0, ("%s: error %d updating cr2", 1283 __func__, error)); 1284 /* fallthru */ 1285 case IDT_NP: 1286 case IDT_SS: 1287 case IDT_GP: 1288 case IDT_AC: 1289 case IDT_TS: 1290 errcode_valid = 1; 1291 break; 1292 1293 case IDT_DF: 1294 errcode_valid = 1; 1295 info1 = 0; 1296 break; 1297 1298 case IDT_BP: 1299 case IDT_OF: 1300 case IDT_BR: 1301 /* 1302 * The 'nrip' field is populated for INT3, INTO and 1303 * BOUND exceptions and this also implies that 1304 * 'inst_length' is non-zero. 1305 * 1306 * Reset 'inst_length' to zero so the guest %rip at 1307 * event injection is identical to what it was when 1308 * the exception originally happened. 1309 */ 1310 VCPU_CTR2(svm_sc->vm, vcpu, "Reset inst_length from %d " 1311 "to zero before injecting exception %d", 1312 vmexit->inst_length, idtvec); 1313 vmexit->inst_length = 0; 1314 /* fallthru */ 1315 default: 1316 errcode_valid = 0; 1317 info1 = 0; 1318 break; 1319 } 1320 KASSERT(vmexit->inst_length == 0, ("invalid inst_length (%d) " 1321 "when reflecting exception %d into guest", 1322 vmexit->inst_length, idtvec)); 1323 1324 if (reflect) { 1325 /* Reflect the exception back into the guest */ 1326 VCPU_CTR2(svm_sc->vm, vcpu, "Reflecting exception " 1327 "%d/%#x into the guest", idtvec, (int)info1); 1328 error = vm_inject_exception(svm_sc->vm, vcpu, idtvec, 1329 errcode_valid, info1, 0); 1330 KASSERT(error == 0, ("%s: vm_inject_exception error %d", 1331 __func__, error)); 1332 } 1333 handled = 1; 1334 break; 1335 case VMCB_EXIT_MSR: /* MSR access. */ 1336 eax = state->rax; 1337 ecx = ctx->sctx_rcx; 1338 edx = ctx->sctx_rdx; 1339 retu = false; 1340 1341 if (info1) { 1342 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_WRMSR, 1); 1343 val = (uint64_t)edx << 32 | eax; 1344 VCPU_CTR2(svm_sc->vm, vcpu, "wrmsr %#x val %#lx", 1345 ecx, val); 1346 if (emulate_wrmsr(svm_sc, vcpu, ecx, val, &retu)) { 1347 vmexit->exitcode = VM_EXITCODE_WRMSR; 1348 vmexit->u.msr.code = ecx; 1349 vmexit->u.msr.wval = val; 1350 } else if (!retu) { 1351 handled = 1; 1352 } else { 1353 KASSERT(vmexit->exitcode != VM_EXITCODE_BOGUS, 1354 ("emulate_wrmsr retu with bogus exitcode")); 1355 } 1356 } else { 1357 VCPU_CTR1(svm_sc->vm, vcpu, "rdmsr %#x", ecx); 1358 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_RDMSR, 1); 1359 if (emulate_rdmsr(svm_sc, vcpu, ecx, &retu)) { 1360 vmexit->exitcode = VM_EXITCODE_RDMSR; 1361 vmexit->u.msr.code = ecx; 1362 } else if (!retu) { 1363 handled = 1; 1364 } else { 1365 KASSERT(vmexit->exitcode != VM_EXITCODE_BOGUS, 1366 ("emulate_rdmsr retu with bogus exitcode")); 1367 } 1368 } 1369 break; 1370 case VMCB_EXIT_IO: 1371 handled = svm_handle_io(svm_sc, vcpu, vmexit); 1372 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_INOUT, 1); 1373 break; 1374 case VMCB_EXIT_CPUID: 1375 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_CPUID, 1); 1376 handled = x86_emulate_cpuid(svm_sc->vm, vcpu, 1377 (uint32_t *)&state->rax, 1378 (uint32_t *)&ctx->sctx_rbx, 1379 (uint32_t *)&ctx->sctx_rcx, 1380 (uint32_t *)&ctx->sctx_rdx); 1381 break; 1382 case VMCB_EXIT_HLT: 1383 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_HLT, 1); 1384 vmexit->exitcode = VM_EXITCODE_HLT; 1385 vmexit->u.hlt.rflags = state->rflags; 1386 break; 1387 case VMCB_EXIT_PAUSE: 1388 vmexit->exitcode = VM_EXITCODE_PAUSE; 1389 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_PAUSE, 1); 1390 break; 1391 case VMCB_EXIT_NPF: 1392 /* EXITINFO2 contains the faulting guest physical address */ 1393 if (info1 & VMCB_NPF_INFO1_RSV) { 1394 VCPU_CTR2(svm_sc->vm, vcpu, "nested page fault with " 1395 "reserved bits set: info1(%#lx) info2(%#lx)", 1396 info1, info2); 1397 } else if (vm_mem_allocated(svm_sc->vm, info2)) { 1398 vmexit->exitcode = VM_EXITCODE_PAGING; 1399 vmexit->u.paging.gpa = info2; 1400 vmexit->u.paging.fault_type = npf_fault_type(info1); 1401 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_NESTED_FAULT, 1); 1402 VCPU_CTR3(svm_sc->vm, vcpu, "nested page fault " 1403 "on gpa %#lx/%#lx at rip %#lx", 1404 info2, info1, state->rip); 1405 } else if (svm_npf_emul_fault(info1)) { 1406 svm_handle_inst_emul(vmcb, info2, vmexit); 1407 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_INST_EMUL, 1); 1408 VCPU_CTR3(svm_sc->vm, vcpu, "inst_emul fault " 1409 "for gpa %#lx/%#lx at rip %#lx", 1410 info2, info1, state->rip); 1411 } 1412 break; 1413 case VMCB_EXIT_MONITOR: 1414 vmexit->exitcode = VM_EXITCODE_MONITOR; 1415 break; 1416 case VMCB_EXIT_MWAIT: 1417 vmexit->exitcode = VM_EXITCODE_MWAIT; 1418 break; 1419 default: 1420 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_UNKNOWN, 1); 1421 break; 1422 } 1423 1424 VCPU_CTR4(svm_sc->vm, vcpu, "%s %s vmexit at %#lx/%d", 1425 handled ? "handled" : "unhandled", exit_reason_to_str(code), 1426 vmexit->rip, vmexit->inst_length); 1427 1428 if (handled) { 1429 vmexit->rip += vmexit->inst_length; 1430 vmexit->inst_length = 0; 1431 state->rip = vmexit->rip; 1432 } else { 1433 if (vmexit->exitcode == VM_EXITCODE_BOGUS) { 1434 /* 1435 * If this VM exit was not claimed by anybody then 1436 * treat it as a generic SVM exit. 1437 */ 1438 vm_exit_svm(vmexit, code, info1, info2); 1439 } else { 1440 /* 1441 * The exitcode and collateral have been populated. 1442 * The VM exit will be processed further in userland. 1443 */ 1444 } 1445 } 1446 return (handled); 1447 } 1448 1449 static void 1450 svm_inj_intinfo(struct svm_softc *svm_sc, int vcpu) 1451 { 1452 uint64_t intinfo; 1453 1454 if (!vm_entry_intinfo(svm_sc->vm, vcpu, &intinfo)) 1455 return; 1456 1457 KASSERT(VMCB_EXITINTINFO_VALID(intinfo), ("%s: entry intinfo is not " 1458 "valid: %#lx", __func__, intinfo)); 1459 1460 svm_eventinject(svm_sc, vcpu, VMCB_EXITINTINFO_TYPE(intinfo), 1461 VMCB_EXITINTINFO_VECTOR(intinfo), 1462 VMCB_EXITINTINFO_EC(intinfo), 1463 VMCB_EXITINTINFO_EC_VALID(intinfo)); 1464 vmm_stat_incr(svm_sc->vm, vcpu, VCPU_INTINFO_INJECTED, 1); 1465 VCPU_CTR1(svm_sc->vm, vcpu, "Injected entry intinfo: %#lx", intinfo); 1466 } 1467 1468 /* 1469 * Inject event to virtual cpu. 1470 */ 1471 static void 1472 svm_inj_interrupts(struct svm_softc *sc, int vcpu, struct vlapic *vlapic) 1473 { 1474 struct vmcb_ctrl *ctrl; 1475 struct vmcb_state *state; 1476 struct svm_vcpu *vcpustate; 1477 uint8_t v_tpr; 1478 int vector, need_intr_window, pending_apic_vector; 1479 1480 state = svm_get_vmcb_state(sc, vcpu); 1481 ctrl = svm_get_vmcb_ctrl(sc, vcpu); 1482 vcpustate = svm_get_vcpu(sc, vcpu); 1483 1484 need_intr_window = 0; 1485 pending_apic_vector = 0; 1486 1487 if (vcpustate->nextrip != state->rip) { 1488 ctrl->intr_shadow = 0; 1489 VCPU_CTR2(sc->vm, vcpu, "Guest interrupt blocking " 1490 "cleared due to rip change: %#lx/%#lx", 1491 vcpustate->nextrip, state->rip); 1492 } 1493 1494 /* 1495 * Inject pending events or exceptions for this vcpu. 1496 * 1497 * An event might be pending because the previous #VMEXIT happened 1498 * during event delivery (i.e. ctrl->exitintinfo). 1499 * 1500 * An event might also be pending because an exception was injected 1501 * by the hypervisor (e.g. #PF during instruction emulation). 1502 */ 1503 svm_inj_intinfo(sc, vcpu); 1504 1505 /* NMI event has priority over interrupts. */ 1506 if (vm_nmi_pending(sc->vm, vcpu)) { 1507 if (nmi_blocked(sc, vcpu)) { 1508 /* 1509 * Can't inject another NMI if the guest has not 1510 * yet executed an "iret" after the last NMI. 1511 */ 1512 VCPU_CTR0(sc->vm, vcpu, "Cannot inject NMI due " 1513 "to NMI-blocking"); 1514 } else if (ctrl->intr_shadow) { 1515 /* 1516 * Can't inject an NMI if the vcpu is in an intr_shadow. 1517 */ 1518 VCPU_CTR0(sc->vm, vcpu, "Cannot inject NMI due to " 1519 "interrupt shadow"); 1520 need_intr_window = 1; 1521 goto done; 1522 } else if (ctrl->eventinj & VMCB_EVENTINJ_VALID) { 1523 /* 1524 * If there is already an exception/interrupt pending 1525 * then defer the NMI until after that. 1526 */ 1527 VCPU_CTR1(sc->vm, vcpu, "Cannot inject NMI due to " 1528 "eventinj %#lx", ctrl->eventinj); 1529 1530 /* 1531 * Use self-IPI to trigger a VM-exit as soon as 1532 * possible after the event injection is completed. 1533 * 1534 * This works only if the external interrupt exiting 1535 * is at a lower priority than the event injection. 1536 * 1537 * Although not explicitly specified in APMv2 the 1538 * relative priorities were verified empirically. 1539 */ 1540 ipi_cpu(curcpu, IPI_AST); /* XXX vmm_ipinum? */ 1541 } else { 1542 vm_nmi_clear(sc->vm, vcpu); 1543 1544 /* Inject NMI, vector number is not used */ 1545 svm_eventinject(sc, vcpu, VMCB_EVENTINJ_TYPE_NMI, 1546 IDT_NMI, 0, false); 1547 1548 /* virtual NMI blocking is now in effect */ 1549 enable_nmi_blocking(sc, vcpu); 1550 1551 VCPU_CTR0(sc->vm, vcpu, "Injecting vNMI"); 1552 } 1553 } 1554 1555 if (!vm_extint_pending(sc->vm, vcpu)) { 1556 /* 1557 * APIC interrupts are delivered using the V_IRQ offload. 1558 * 1559 * The primary benefit is that the hypervisor doesn't need to 1560 * deal with the various conditions that inhibit interrupts. 1561 * It also means that TPR changes via CR8 will be handled 1562 * without any hypervisor involvement. 1563 * 1564 * Note that the APIC vector must remain pending in the vIRR 1565 * until it is confirmed that it was delivered to the guest. 1566 * This can be confirmed based on the value of V_IRQ at the 1567 * next #VMEXIT (1 = pending, 0 = delivered). 1568 * 1569 * Also note that it is possible that another higher priority 1570 * vector can become pending before this vector is delivered 1571 * to the guest. This is alright because vcpu_notify_event() 1572 * will send an IPI and force the vcpu to trap back into the 1573 * hypervisor. The higher priority vector will be injected on 1574 * the next VMRUN. 1575 */ 1576 if (vlapic_pending_intr(vlapic, &vector)) { 1577 KASSERT(vector >= 16 && vector <= 255, 1578 ("invalid vector %d from local APIC", vector)); 1579 pending_apic_vector = vector; 1580 } 1581 goto done; 1582 } 1583 1584 /* Ask the legacy pic for a vector to inject */ 1585 vatpic_pending_intr(sc->vm, &vector); 1586 KASSERT(vector >= 0 && vector <= 255, ("invalid vector %d from INTR", 1587 vector)); 1588 1589 /* 1590 * If the guest has disabled interrupts or is in an interrupt shadow 1591 * then we cannot inject the pending interrupt. 1592 */ 1593 if ((state->rflags & PSL_I) == 0) { 1594 VCPU_CTR2(sc->vm, vcpu, "Cannot inject vector %d due to " 1595 "rflags %#lx", vector, state->rflags); 1596 need_intr_window = 1; 1597 goto done; 1598 } 1599 1600 if (ctrl->intr_shadow) { 1601 VCPU_CTR1(sc->vm, vcpu, "Cannot inject vector %d due to " 1602 "interrupt shadow", vector); 1603 need_intr_window = 1; 1604 goto done; 1605 } 1606 1607 if (ctrl->eventinj & VMCB_EVENTINJ_VALID) { 1608 VCPU_CTR2(sc->vm, vcpu, "Cannot inject vector %d due to " 1609 "eventinj %#lx", vector, ctrl->eventinj); 1610 need_intr_window = 1; 1611 goto done; 1612 } 1613 1614 /* 1615 * Legacy PIC interrupts are delivered via the event injection 1616 * mechanism. 1617 */ 1618 svm_eventinject(sc, vcpu, VMCB_EVENTINJ_TYPE_INTR, vector, 0, false); 1619 1620 vm_extint_clear(sc->vm, vcpu); 1621 vatpic_intr_accepted(sc->vm, vector); 1622 1623 /* 1624 * Force a VM-exit as soon as the vcpu is ready to accept another 1625 * interrupt. This is done because the PIC might have another vector 1626 * that it wants to inject. Also, if the APIC has a pending interrupt 1627 * that was preempted by the ExtInt then it allows us to inject the 1628 * APIC vector as soon as possible. 1629 */ 1630 need_intr_window = 1; 1631 done: 1632 /* 1633 * The guest can modify the TPR by writing to %CR8. In guest mode 1634 * the processor reflects this write to V_TPR without hypervisor 1635 * intervention. 1636 * 1637 * The guest can also modify the TPR by writing to it via the memory 1638 * mapped APIC page. In this case, the write will be emulated by the 1639 * hypervisor. For this reason V_TPR must be updated before every 1640 * VMRUN. 1641 */ 1642 v_tpr = vlapic_get_cr8(vlapic); 1643 KASSERT(v_tpr >= 0 && v_tpr <= 15, ("invalid v_tpr %#x", v_tpr)); 1644 if (ctrl->v_tpr != v_tpr) { 1645 VCPU_CTR2(sc->vm, vcpu, "VMCB V_TPR changed from %#x to %#x", 1646 ctrl->v_tpr, v_tpr); 1647 ctrl->v_tpr = v_tpr; 1648 svm_set_dirty(sc, vcpu, VMCB_CACHE_TPR); 1649 } 1650 1651 if (pending_apic_vector) { 1652 /* 1653 * If an APIC vector is being injected then interrupt window 1654 * exiting is not possible on this VMRUN. 1655 */ 1656 KASSERT(!need_intr_window, ("intr_window exiting impossible")); 1657 VCPU_CTR1(sc->vm, vcpu, "Injecting vector %d using V_IRQ", 1658 pending_apic_vector); 1659 1660 ctrl->v_irq = 1; 1661 ctrl->v_ign_tpr = 0; 1662 ctrl->v_intr_vector = pending_apic_vector; 1663 ctrl->v_intr_prio = pending_apic_vector >> 4; 1664 svm_set_dirty(sc, vcpu, VMCB_CACHE_TPR); 1665 } else if (need_intr_window) { 1666 /* 1667 * We use V_IRQ in conjunction with the VINTR intercept to 1668 * trap into the hypervisor as soon as a virtual interrupt 1669 * can be delivered. 1670 * 1671 * Since injected events are not subject to intercept checks 1672 * we need to ensure that the V_IRQ is not actually going to 1673 * be delivered on VM entry. The KASSERT below enforces this. 1674 */ 1675 KASSERT((ctrl->eventinj & VMCB_EVENTINJ_VALID) != 0 || 1676 (state->rflags & PSL_I) == 0 || ctrl->intr_shadow, 1677 ("Bogus intr_window_exiting: eventinj (%#lx), " 1678 "intr_shadow (%u), rflags (%#lx)", 1679 ctrl->eventinj, ctrl->intr_shadow, state->rflags)); 1680 enable_intr_window_exiting(sc, vcpu); 1681 } else { 1682 disable_intr_window_exiting(sc, vcpu); 1683 } 1684 } 1685 1686 static __inline void 1687 restore_host_tss(void) 1688 { 1689 struct system_segment_descriptor *tss_sd; 1690 1691 /* 1692 * The TSS descriptor was in use prior to launching the guest so it 1693 * has been marked busy. 1694 * 1695 * 'ltr' requires the descriptor to be marked available so change the 1696 * type to "64-bit available TSS". 1697 */ 1698 tss_sd = PCPU_GET(tss); 1699 tss_sd->sd_type = SDT_SYSTSS; 1700 ltr(GSEL(GPROC0_SEL, SEL_KPL)); 1701 } 1702 1703 static void 1704 check_asid(struct svm_softc *sc, int vcpuid, pmap_t pmap, u_int thiscpu) 1705 { 1706 struct svm_vcpu *vcpustate; 1707 struct vmcb_ctrl *ctrl; 1708 long eptgen; 1709 bool alloc_asid; 1710 1711 KASSERT(CPU_ISSET(thiscpu, &pmap->pm_active), ("%s: nested pmap not " 1712 "active on cpu %u", __func__, thiscpu)); 1713 1714 vcpustate = svm_get_vcpu(sc, vcpuid); 1715 ctrl = svm_get_vmcb_ctrl(sc, vcpuid); 1716 1717 /* 1718 * The TLB entries associated with the vcpu's ASID are not valid 1719 * if either of the following conditions is true: 1720 * 1721 * 1. The vcpu's ASID generation is different than the host cpu's 1722 * ASID generation. This happens when the vcpu migrates to a new 1723 * host cpu. It can also happen when the number of vcpus executing 1724 * on a host cpu is greater than the number of ASIDs available. 1725 * 1726 * 2. The pmap generation number is different than the value cached in 1727 * the 'vcpustate'. This happens when the host invalidates pages 1728 * belonging to the guest. 1729 * 1730 * asidgen eptgen Action 1731 * mismatch mismatch 1732 * 0 0 (a) 1733 * 0 1 (b1) or (b2) 1734 * 1 0 (c) 1735 * 1 1 (d) 1736 * 1737 * (a) There is no mismatch in eptgen or ASID generation and therefore 1738 * no further action is needed. 1739 * 1740 * (b1) If the cpu supports FlushByAsid then the vcpu's ASID is 1741 * retained and the TLB entries associated with this ASID 1742 * are flushed by VMRUN. 1743 * 1744 * (b2) If the cpu does not support FlushByAsid then a new ASID is 1745 * allocated. 1746 * 1747 * (c) A new ASID is allocated. 1748 * 1749 * (d) A new ASID is allocated. 1750 */ 1751 1752 alloc_asid = false; 1753 eptgen = pmap->pm_eptgen; 1754 ctrl->tlb_ctrl = VMCB_TLB_FLUSH_NOTHING; 1755 1756 if (vcpustate->asid.gen != asid[thiscpu].gen) { 1757 alloc_asid = true; /* (c) and (d) */ 1758 } else if (vcpustate->eptgen != eptgen) { 1759 if (flush_by_asid()) 1760 ctrl->tlb_ctrl = VMCB_TLB_FLUSH_GUEST; /* (b1) */ 1761 else 1762 alloc_asid = true; /* (b2) */ 1763 } else { 1764 /* 1765 * This is the common case (a). 1766 */ 1767 KASSERT(!alloc_asid, ("ASID allocation not necessary")); 1768 KASSERT(ctrl->tlb_ctrl == VMCB_TLB_FLUSH_NOTHING, 1769 ("Invalid VMCB tlb_ctrl: %#x", ctrl->tlb_ctrl)); 1770 } 1771 1772 if (alloc_asid) { 1773 if (++asid[thiscpu].num >= nasid) { 1774 asid[thiscpu].num = 1; 1775 if (++asid[thiscpu].gen == 0) 1776 asid[thiscpu].gen = 1; 1777 /* 1778 * If this cpu does not support "flush-by-asid" 1779 * then flush the entire TLB on a generation 1780 * bump. Subsequent ASID allocation in this 1781 * generation can be done without a TLB flush. 1782 */ 1783 if (!flush_by_asid()) 1784 ctrl->tlb_ctrl = VMCB_TLB_FLUSH_ALL; 1785 } 1786 vcpustate->asid.gen = asid[thiscpu].gen; 1787 vcpustate->asid.num = asid[thiscpu].num; 1788 1789 ctrl->asid = vcpustate->asid.num; 1790 svm_set_dirty(sc, vcpuid, VMCB_CACHE_ASID); 1791 /* 1792 * If this cpu supports "flush-by-asid" then the TLB 1793 * was not flushed after the generation bump. The TLB 1794 * is flushed selectively after every new ASID allocation. 1795 */ 1796 if (flush_by_asid()) 1797 ctrl->tlb_ctrl = VMCB_TLB_FLUSH_GUEST; 1798 } 1799 vcpustate->eptgen = eptgen; 1800 1801 KASSERT(ctrl->asid != 0, ("Guest ASID must be non-zero")); 1802 KASSERT(ctrl->asid == vcpustate->asid.num, 1803 ("ASID mismatch: %u/%u", ctrl->asid, vcpustate->asid.num)); 1804 } 1805 1806 static __inline void 1807 disable_gintr(void) 1808 { 1809 1810 __asm __volatile("clgi" : : :); 1811 } 1812 1813 static __inline void 1814 enable_gintr(void) 1815 { 1816 1817 __asm __volatile("stgi" : : :); 1818 } 1819 1820 /* 1821 * Start vcpu with specified RIP. 1822 */ 1823 static int 1824 svm_vmrun(void *arg, int vcpu, register_t rip, pmap_t pmap, 1825 void *rend_cookie, void *suspended_cookie) 1826 { 1827 struct svm_regctx *gctx; 1828 struct svm_softc *svm_sc; 1829 struct svm_vcpu *vcpustate; 1830 struct vmcb_state *state; 1831 struct vmcb_ctrl *ctrl; 1832 struct vm_exit *vmexit; 1833 struct vlapic *vlapic; 1834 struct vm *vm; 1835 uint64_t vmcb_pa; 1836 u_int thiscpu; 1837 int handled; 1838 1839 svm_sc = arg; 1840 vm = svm_sc->vm; 1841 1842 vcpustate = svm_get_vcpu(svm_sc, vcpu); 1843 state = svm_get_vmcb_state(svm_sc, vcpu); 1844 ctrl = svm_get_vmcb_ctrl(svm_sc, vcpu); 1845 vmexit = vm_exitinfo(vm, vcpu); 1846 vlapic = vm_lapic(vm, vcpu); 1847 1848 /* 1849 * Stash 'curcpu' on the stack as 'thiscpu'. 1850 * 1851 * The per-cpu data area is not accessible until MSR_GSBASE is restored 1852 * after the #VMEXIT. Since VMRUN is executed inside a critical section 1853 * 'curcpu' and 'thiscpu' are guaranteed to identical. 1854 */ 1855 thiscpu = curcpu; 1856 1857 gctx = svm_get_guest_regctx(svm_sc, vcpu); 1858 vmcb_pa = svm_sc->vcpu[vcpu].vmcb_pa; 1859 1860 if (vcpustate->lastcpu != thiscpu) { 1861 /* 1862 * Force new ASID allocation by invalidating the generation. 1863 */ 1864 vcpustate->asid.gen = 0; 1865 1866 /* 1867 * Invalidate the VMCB state cache by marking all fields dirty. 1868 */ 1869 svm_set_dirty(svm_sc, vcpu, 0xffffffff); 1870 1871 /* 1872 * XXX 1873 * Setting 'vcpustate->lastcpu' here is bit premature because 1874 * we may return from this function without actually executing 1875 * the VMRUN instruction. This could happen if a rendezvous 1876 * or an AST is pending on the first time through the loop. 1877 * 1878 * This works for now but any new side-effects of vcpu 1879 * migration should take this case into account. 1880 */ 1881 vcpustate->lastcpu = thiscpu; 1882 vmm_stat_incr(vm, vcpu, VCPU_MIGRATIONS, 1); 1883 } 1884 1885 svm_msr_guest_enter(svm_sc, vcpu); 1886 1887 /* Update Guest RIP */ 1888 state->rip = rip; 1889 1890 do { 1891 /* 1892 * Disable global interrupts to guarantee atomicity during 1893 * loading of guest state. This includes not only the state 1894 * loaded by the "vmrun" instruction but also software state 1895 * maintained by the hypervisor: suspended and rendezvous 1896 * state, NPT generation number, vlapic interrupts etc. 1897 */ 1898 disable_gintr(); 1899 1900 if (vcpu_suspended(suspended_cookie)) { 1901 enable_gintr(); 1902 vm_exit_suspended(vm, vcpu, state->rip); 1903 break; 1904 } 1905 1906 if (vcpu_rendezvous_pending(rend_cookie)) { 1907 enable_gintr(); 1908 vm_exit_rendezvous(vm, vcpu, state->rip); 1909 break; 1910 } 1911 1912 /* We are asked to give the cpu by scheduler. */ 1913 if (curthread->td_flags & (TDF_ASTPENDING | TDF_NEEDRESCHED)) { 1914 enable_gintr(); 1915 vm_exit_astpending(vm, vcpu, state->rip); 1916 break; 1917 } 1918 1919 svm_inj_interrupts(svm_sc, vcpu, vlapic); 1920 1921 /* Activate the nested pmap on 'thiscpu' */ 1922 CPU_SET_ATOMIC_ACQ(thiscpu, &pmap->pm_active); 1923 1924 /* 1925 * Check the pmap generation and the ASID generation to 1926 * ensure that the vcpu does not use stale TLB mappings. 1927 */ 1928 check_asid(svm_sc, vcpu, pmap, thiscpu); 1929 1930 ctrl->vmcb_clean = vmcb_clean & ~vcpustate->dirty; 1931 vcpustate->dirty = 0; 1932 VCPU_CTR1(vm, vcpu, "vmcb clean %#x", ctrl->vmcb_clean); 1933 1934 /* Launch Virtual Machine. */ 1935 VCPU_CTR1(vm, vcpu, "Resume execution at %#lx", state->rip); 1936 svm_launch(vmcb_pa, gctx); 1937 1938 CPU_CLR_ATOMIC(thiscpu, &pmap->pm_active); 1939 1940 /* 1941 * Restore MSR_GSBASE to point to the pcpu data area. 1942 * 1943 * Note that accesses done via PCPU_GET/PCPU_SET will work 1944 * only after MSR_GSBASE is restored. 1945 * 1946 * Also note that we don't bother restoring MSR_KGSBASE 1947 * since it is not used in the kernel and will be restored 1948 * when the VMRUN ioctl returns to userspace. 1949 */ 1950 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[thiscpu]); 1951 KASSERT(curcpu == thiscpu, ("thiscpu/curcpu (%u/%u) mismatch", 1952 thiscpu, curcpu)); 1953 1954 /* 1955 * The host GDTR and IDTR is saved by VMRUN and restored 1956 * automatically on #VMEXIT. However, the host TSS needs 1957 * to be restored explicitly. 1958 */ 1959 restore_host_tss(); 1960 1961 /* #VMEXIT disables interrupts so re-enable them here. */ 1962 enable_gintr(); 1963 1964 /* Update 'nextrip' */ 1965 vcpustate->nextrip = state->rip; 1966 1967 /* Handle #VMEXIT and if required return to user space. */ 1968 handled = svm_vmexit(svm_sc, vcpu, vmexit); 1969 } while (handled); 1970 1971 svm_msr_guest_exit(svm_sc, vcpu); 1972 1973 return (0); 1974 } 1975 1976 static void 1977 svm_vmcleanup(void *arg) 1978 { 1979 struct svm_softc *sc = arg; 1980 1981 free(sc, M_SVM); 1982 } 1983 1984 static register_t * 1985 swctx_regptr(struct svm_regctx *regctx, int reg) 1986 { 1987 1988 switch (reg) { 1989 case VM_REG_GUEST_RBX: 1990 return (®ctx->sctx_rbx); 1991 case VM_REG_GUEST_RCX: 1992 return (®ctx->sctx_rcx); 1993 case VM_REG_GUEST_RDX: 1994 return (®ctx->sctx_rdx); 1995 case VM_REG_GUEST_RDI: 1996 return (®ctx->sctx_rdi); 1997 case VM_REG_GUEST_RSI: 1998 return (®ctx->sctx_rsi); 1999 case VM_REG_GUEST_RBP: 2000 return (®ctx->sctx_rbp); 2001 case VM_REG_GUEST_R8: 2002 return (®ctx->sctx_r8); 2003 case VM_REG_GUEST_R9: 2004 return (®ctx->sctx_r9); 2005 case VM_REG_GUEST_R10: 2006 return (®ctx->sctx_r10); 2007 case VM_REG_GUEST_R11: 2008 return (®ctx->sctx_r11); 2009 case VM_REG_GUEST_R12: 2010 return (®ctx->sctx_r12); 2011 case VM_REG_GUEST_R13: 2012 return (®ctx->sctx_r13); 2013 case VM_REG_GUEST_R14: 2014 return (®ctx->sctx_r14); 2015 case VM_REG_GUEST_R15: 2016 return (®ctx->sctx_r15); 2017 default: 2018 return (NULL); 2019 } 2020 } 2021 2022 static int 2023 svm_getreg(void *arg, int vcpu, int ident, uint64_t *val) 2024 { 2025 struct svm_softc *svm_sc; 2026 register_t *reg; 2027 2028 svm_sc = arg; 2029 2030 if (ident == VM_REG_GUEST_INTR_SHADOW) { 2031 return (svm_get_intr_shadow(svm_sc, vcpu, val)); 2032 } 2033 2034 if (vmcb_read(svm_sc, vcpu, ident, val) == 0) { 2035 return (0); 2036 } 2037 2038 reg = swctx_regptr(svm_get_guest_regctx(svm_sc, vcpu), ident); 2039 2040 if (reg != NULL) { 2041 *val = *reg; 2042 return (0); 2043 } 2044 2045 VCPU_CTR1(svm_sc->vm, vcpu, "svm_getreg: unknown register %#x", ident); 2046 return (EINVAL); 2047 } 2048 2049 static int 2050 svm_setreg(void *arg, int vcpu, int ident, uint64_t val) 2051 { 2052 struct svm_softc *svm_sc; 2053 register_t *reg; 2054 2055 svm_sc = arg; 2056 2057 if (ident == VM_REG_GUEST_INTR_SHADOW) { 2058 return (svm_modify_intr_shadow(svm_sc, vcpu, val)); 2059 } 2060 2061 if (vmcb_write(svm_sc, vcpu, ident, val) == 0) { 2062 return (0); 2063 } 2064 2065 reg = swctx_regptr(svm_get_guest_regctx(svm_sc, vcpu), ident); 2066 2067 if (reg != NULL) { 2068 *reg = val; 2069 return (0); 2070 } 2071 2072 /* 2073 * XXX deal with CR3 and invalidate TLB entries tagged with the 2074 * vcpu's ASID. This needs to be treated differently depending on 2075 * whether 'running' is true/false. 2076 */ 2077 2078 VCPU_CTR1(svm_sc->vm, vcpu, "svm_setreg: unknown register %#x", ident); 2079 return (EINVAL); 2080 } 2081 2082 static int 2083 svm_setcap(void *arg, int vcpu, int type, int val) 2084 { 2085 struct svm_softc *sc; 2086 int error; 2087 2088 sc = arg; 2089 error = 0; 2090 switch (type) { 2091 case VM_CAP_HALT_EXIT: 2092 svm_set_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, 2093 VMCB_INTCPT_HLT, val); 2094 break; 2095 case VM_CAP_PAUSE_EXIT: 2096 svm_set_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, 2097 VMCB_INTCPT_PAUSE, val); 2098 break; 2099 case VM_CAP_UNRESTRICTED_GUEST: 2100 /* Unrestricted guest execution cannot be disabled in SVM */ 2101 if (val == 0) 2102 error = EINVAL; 2103 break; 2104 default: 2105 error = ENOENT; 2106 break; 2107 } 2108 return (error); 2109 } 2110 2111 static int 2112 svm_getcap(void *arg, int vcpu, int type, int *retval) 2113 { 2114 struct svm_softc *sc; 2115 int error; 2116 2117 sc = arg; 2118 error = 0; 2119 2120 switch (type) { 2121 case VM_CAP_HALT_EXIT: 2122 *retval = svm_get_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, 2123 VMCB_INTCPT_HLT); 2124 break; 2125 case VM_CAP_PAUSE_EXIT: 2126 *retval = svm_get_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, 2127 VMCB_INTCPT_PAUSE); 2128 break; 2129 case VM_CAP_UNRESTRICTED_GUEST: 2130 *retval = 1; /* unrestricted guest is always enabled */ 2131 break; 2132 default: 2133 error = ENOENT; 2134 break; 2135 } 2136 return (error); 2137 } 2138 2139 static struct vlapic * 2140 svm_vlapic_init(void *arg, int vcpuid) 2141 { 2142 struct svm_softc *svm_sc; 2143 struct vlapic *vlapic; 2144 2145 svm_sc = arg; 2146 vlapic = malloc(sizeof(struct vlapic), M_SVM_VLAPIC, M_WAITOK | M_ZERO); 2147 vlapic->vm = svm_sc->vm; 2148 vlapic->vcpuid = vcpuid; 2149 vlapic->apic_page = (struct LAPIC *)&svm_sc->apic_page[vcpuid]; 2150 2151 vlapic_init(vlapic); 2152 2153 return (vlapic); 2154 } 2155 2156 static void 2157 svm_vlapic_cleanup(void *arg, struct vlapic *vlapic) 2158 { 2159 2160 vlapic_cleanup(vlapic); 2161 free(vlapic, M_SVM_VLAPIC); 2162 } 2163 2164 struct vmm_ops vmm_ops_amd = { 2165 svm_init, 2166 svm_cleanup, 2167 svm_restore, 2168 svm_vminit, 2169 svm_vmrun, 2170 svm_vmcleanup, 2171 svm_getreg, 2172 svm_setreg, 2173 vmcb_getdesc, 2174 vmcb_setdesc, 2175 svm_getcap, 2176 svm_setcap, 2177 svm_npt_alloc, 2178 svm_npt_free, 2179 svm_vlapic_init, 2180 svm_vlapic_cleanup 2181 }; 2182