1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 1990 The Regents of the University of California. 5 * All rights reserved. 6 * Copyright (c) 1994 John S. Dyson 7 * All rights reserved. 8 * Copyright (c) 2003 Peter Wemm 9 * All rights reserved. 10 * 11 * This code is derived from software contributed to Berkeley by 12 * William Jolitz. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 3. All advertising materials mentioning features or use of this software 23 * must display the following acknowledgement: 24 * This product includes software developed by the University of 25 * California, Berkeley and its contributors. 26 * 4. Neither the name of the University nor the names of its contributors 27 * may be used to endorse or promote products derived from this software 28 * without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 33 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 38 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 39 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 40 * SUCH DAMAGE. 41 * 42 * from: @(#)vmparam.h 5.9 (Berkeley) 5/12/91 43 * $FreeBSD$ 44 */ 45 46 47 #ifndef _MACHINE_VMPARAM_H_ 48 #define _MACHINE_VMPARAM_H_ 1 49 50 /* 51 * Machine dependent constants for AMD64. 52 */ 53 54 /* 55 * Virtual memory related constants, all in bytes 56 */ 57 #define MAXTSIZ (32768UL*1024*1024) /* max text size */ 58 #ifndef DFLDSIZ 59 #define DFLDSIZ (32768UL*1024*1024) /* initial data size limit */ 60 #endif 61 #ifndef MAXDSIZ 62 #define MAXDSIZ (32768UL*1024*1024) /* max data size */ 63 #endif 64 #ifndef DFLSSIZ 65 #define DFLSSIZ (8UL*1024*1024) /* initial stack size limit */ 66 #endif 67 #ifndef MAXSSIZ 68 #define MAXSSIZ (512UL*1024*1024) /* max stack size */ 69 #endif 70 #ifndef SGROWSIZ 71 #define SGROWSIZ (128UL*1024) /* amount to grow stack */ 72 #endif 73 74 /* 75 * We provide a machine specific single page allocator through the use 76 * of the direct mapped segment. This uses 2MB pages for reduced 77 * TLB pressure. 78 */ 79 #define UMA_MD_SMALL_ALLOC 80 81 /* 82 * The physical address space is densely populated. 83 */ 84 #define VM_PHYSSEG_DENSE 85 86 /* 87 * The number of PHYSSEG entries must be one greater than the number 88 * of phys_avail entries because the phys_avail entry that spans the 89 * largest physical address that is accessible by ISA DMA is split 90 * into two PHYSSEG entries. 91 */ 92 #define VM_PHYSSEG_MAX 63 93 94 /* 95 * Create two free page pools: VM_FREEPOOL_DEFAULT is the default pool 96 * from which physical pages are allocated and VM_FREEPOOL_DIRECT is 97 * the pool from which physical pages for page tables and small UMA 98 * objects are allocated. 99 */ 100 #define VM_NFREEPOOL 2 101 #define VM_FREEPOOL_DEFAULT 0 102 #define VM_FREEPOOL_DIRECT 1 103 104 /* 105 * Create up to three free page lists: VM_FREELIST_DMA32 is for physical pages 106 * that have physical addresses below 4G but are not accessible by ISA DMA, 107 * and VM_FREELIST_ISADMA is for physical pages that are accessible by ISA 108 * DMA. 109 */ 110 #define VM_NFREELIST 3 111 #define VM_FREELIST_DEFAULT 0 112 #define VM_FREELIST_DMA32 1 113 #define VM_FREELIST_LOWMEM 2 114 115 #define VM_LOWMEM_BOUNDARY (16 << 20) /* 16MB ISA DMA limit */ 116 117 /* 118 * Create the DMA32 free list only if the number of physical pages above 119 * physical address 4G is at least 16M, which amounts to 64GB of physical 120 * memory. 121 */ 122 #define VM_DMA32_NPAGES_THRESHOLD 16777216 123 124 /* 125 * An allocation size of 16MB is supported in order to optimize the 126 * use of the direct map by UMA. Specifically, a cache line contains 127 * at most 8 PDEs, collectively mapping 16MB of physical memory. By 128 * reducing the number of distinct 16MB "pages" that are used by UMA, 129 * the physical memory allocator reduces the likelihood of both 2MB 130 * page TLB misses and cache misses caused by 2MB page TLB misses. 131 */ 132 #define VM_NFREEORDER 13 133 134 /* 135 * Enable superpage reservations: 1 level. 136 */ 137 #ifndef VM_NRESERVLEVEL 138 #define VM_NRESERVLEVEL 1 139 #endif 140 141 /* 142 * Level 0 reservations consist of 512 pages. 143 */ 144 #ifndef VM_LEVEL_0_ORDER 145 #define VM_LEVEL_0_ORDER 9 146 #endif 147 148 #ifdef SMP 149 #define PA_LOCK_COUNT 256 150 #endif 151 152 /* 153 * Virtual addresses of things. Derived from the page directory and 154 * page table indexes from pmap.h for precision. 155 * 156 * 0x0000000000000000 - 0x00007fffffffffff user map 157 * 0x0000800000000000 - 0xffff7fffffffffff does not exist (hole) 158 * 0xffff800000000000 - 0xffff804020100fff recursive page table (512GB slot) 159 * 0xffff804020101000 - 0xfffff7ffffffffff unused 160 * 0xfffff80000000000 - 0xfffffbffffffffff 4TB direct map 161 * 0xfffffc0000000000 - 0xfffffdffffffffff unused 162 * 0xfffffe0000000000 - 0xffffffffffffffff 2TB kernel map 163 * 164 * Within the kernel map: 165 * 166 * 0xffffffff80000000 KERNBASE 167 */ 168 169 #define VM_MIN_KERNEL_ADDRESS KVADDR(KPML4BASE, 0, 0, 0) 170 #define VM_MAX_KERNEL_ADDRESS KVADDR(KPML4BASE + NKPML4E - 1, \ 171 NPDPEPG-1, NPDEPG-1, NPTEPG-1) 172 173 #define DMAP_MIN_ADDRESS KVADDR(DMPML4I, 0, 0, 0) 174 #define DMAP_MAX_ADDRESS KVADDR(DMPML4I + NDMPML4E, 0, 0, 0) 175 176 #define KERNBASE KVADDR(KPML4I, KPDPI, 0, 0) 177 178 #define UPT_MAX_ADDRESS KVADDR(PML4PML4I, PML4PML4I, PML4PML4I, PML4PML4I) 179 #define UPT_MIN_ADDRESS KVADDR(PML4PML4I, 0, 0, 0) 180 181 #define VM_MAXUSER_ADDRESS UVADDR(NUPML4E, 0, 0, 0) 182 183 #define SHAREDPAGE (VM_MAXUSER_ADDRESS - PAGE_SIZE) 184 #define USRSTACK SHAREDPAGE 185 186 #define VM_MAX_ADDRESS UPT_MAX_ADDRESS 187 #define VM_MIN_ADDRESS (0) 188 189 /* 190 * XXX Allowing dmaplimit == 0 is a temporary workaround for vt(4) efifb's 191 * early use of PHYS_TO_DMAP before the mapping is actually setup. This works 192 * because the result is not actually accessed until later, but the early 193 * vt fb startup needs to be reworked. 194 */ 195 #define PMAP_HAS_DMAP 1 196 #define PHYS_TO_DMAP(x) ({ \ 197 KASSERT(dmaplimit == 0 || (x) < dmaplimit, \ 198 ("physical address %#jx not covered by the DMAP", \ 199 (uintmax_t)x)); \ 200 (x) | DMAP_MIN_ADDRESS; }) 201 202 #define DMAP_TO_PHYS(x) ({ \ 203 KASSERT((x) < (DMAP_MIN_ADDRESS + dmaplimit) && \ 204 (x) >= DMAP_MIN_ADDRESS, \ 205 ("virtual address %#jx not covered by the DMAP", \ 206 (uintmax_t)x)); \ 207 (x) & ~DMAP_MIN_ADDRESS; }) 208 209 /* 210 * How many physical pages per kmem arena virtual page. 211 */ 212 #ifndef VM_KMEM_SIZE_SCALE 213 #define VM_KMEM_SIZE_SCALE (1) 214 #endif 215 216 /* 217 * Optional ceiling (in bytes) on the size of the kmem arena: 60% of the 218 * kernel map. 219 */ 220 #ifndef VM_KMEM_SIZE_MAX 221 #define VM_KMEM_SIZE_MAX ((VM_MAX_KERNEL_ADDRESS - \ 222 VM_MIN_KERNEL_ADDRESS + 1) * 3 / 5) 223 #endif 224 225 /* initial pagein size of beginning of executable file */ 226 #ifndef VM_INITIAL_PAGEIN 227 #define VM_INITIAL_PAGEIN 16 228 #endif 229 230 #define ZERO_REGION_SIZE (2 * 1024 * 1024) /* 2MB */ 231 232 /* 233 * Use a fairly large batch size since we expect amd64 systems to have lots of 234 * memory. 235 */ 236 #define VM_BATCHQUEUE_SIZE 31 237 238 #endif /* _MACHINE_VMPARAM_H_ */ 239