1ba9b7bf7SNeel Natu /*- 2ba9b7bf7SNeel Natu * Copyright (c) 2012 NetApp, Inc. 3ba9b7bf7SNeel Natu * All rights reserved. 4ba9b7bf7SNeel Natu * 5ba9b7bf7SNeel Natu * Redistribution and use in source and binary forms, with or without 6ba9b7bf7SNeel Natu * modification, are permitted provided that the following conditions 7ba9b7bf7SNeel Natu * are met: 8ba9b7bf7SNeel Natu * 1. Redistributions of source code must retain the above copyright 9ba9b7bf7SNeel Natu * notice, this list of conditions and the following disclaimer. 10ba9b7bf7SNeel Natu * 2. Redistributions in binary form must reproduce the above copyright 11ba9b7bf7SNeel Natu * notice, this list of conditions and the following disclaimer in the 12ba9b7bf7SNeel Natu * documentation and/or other materials provided with the distribution. 13ba9b7bf7SNeel Natu * 14ba9b7bf7SNeel Natu * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 15ba9b7bf7SNeel Natu * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16ba9b7bf7SNeel Natu * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17ba9b7bf7SNeel Natu * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 18ba9b7bf7SNeel Natu * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19ba9b7bf7SNeel Natu * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20ba9b7bf7SNeel Natu * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21ba9b7bf7SNeel Natu * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22ba9b7bf7SNeel Natu * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23ba9b7bf7SNeel Natu * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24ba9b7bf7SNeel Natu * SUCH DAMAGE. 25ba9b7bf7SNeel Natu * 26ba9b7bf7SNeel Natu * $FreeBSD$ 27ba9b7bf7SNeel Natu */ 28ba9b7bf7SNeel Natu 29ba9b7bf7SNeel Natu #ifndef _VMM_INSTRUCTION_EMUL_H_ 30ba9b7bf7SNeel Natu #define _VMM_INSTRUCTION_EMUL_H_ 31ba9b7bf7SNeel Natu 32ba9b7bf7SNeel Natu /* 33ba9b7bf7SNeel Natu * The data structures 'vie' and 'vie_op' are meant to be opaque to the 34ba9b7bf7SNeel Natu * consumers of instruction decoding. The only reason why their contents 35ba9b7bf7SNeel Natu * need to be exposed is because they are part of the 'vm_exit' structure. 36ba9b7bf7SNeel Natu */ 37ba9b7bf7SNeel Natu struct vie_op { 38ba9b7bf7SNeel Natu uint8_t op_byte; /* actual opcode byte */ 39ba9b7bf7SNeel Natu uint8_t op_type; /* type of operation (e.g. MOV) */ 40ba9b7bf7SNeel Natu uint16_t op_flags; 41ba9b7bf7SNeel Natu }; 42ba9b7bf7SNeel Natu 43ba9b7bf7SNeel Natu #define VIE_INST_SIZE 15 44ba9b7bf7SNeel Natu struct vie { 45ba9b7bf7SNeel Natu uint8_t inst[VIE_INST_SIZE]; /* instruction bytes */ 46ba9b7bf7SNeel Natu uint8_t num_valid; /* size of the instruction */ 47ba9b7bf7SNeel Natu uint8_t num_processed; 48ba9b7bf7SNeel Natu 49ba9b7bf7SNeel Natu uint8_t rex_w:1, /* REX prefix */ 50ba9b7bf7SNeel Natu rex_r:1, 51ba9b7bf7SNeel Natu rex_x:1, 528faceb32SNeel Natu rex_b:1, 538faceb32SNeel Natu rex_present:1; 54ba9b7bf7SNeel Natu 55ba9b7bf7SNeel Natu uint8_t mod:2, /* ModRM byte */ 56ba9b7bf7SNeel Natu reg:4, 57ba9b7bf7SNeel Natu rm:4; 58ba9b7bf7SNeel Natu 59ba9b7bf7SNeel Natu uint8_t ss:2, /* SIB byte */ 60ba9b7bf7SNeel Natu index:4, 61ba9b7bf7SNeel Natu base:4; 62ba9b7bf7SNeel Natu 63ba9b7bf7SNeel Natu uint8_t disp_bytes; 64ba9b7bf7SNeel Natu uint8_t imm_bytes; 65ba9b7bf7SNeel Natu 66ba9b7bf7SNeel Natu uint8_t scale; 67ba9b7bf7SNeel Natu int base_register; /* VM_REG_GUEST_xyz */ 68ba9b7bf7SNeel Natu int index_register; /* VM_REG_GUEST_xyz */ 69ba9b7bf7SNeel Natu 70ba9b7bf7SNeel Natu int64_t displacement; /* optional addr displacement */ 71ba9b7bf7SNeel Natu int64_t immediate; /* optional immediate operand */ 72ba9b7bf7SNeel Natu 73ba9b7bf7SNeel Natu uint8_t decoded; /* set to 1 if successfully decoded */ 74ba9b7bf7SNeel Natu 75ba9b7bf7SNeel Natu struct vie_op op; /* opcode description */ 76ba9b7bf7SNeel Natu }; 77ba9b7bf7SNeel Natu 78ba9b7bf7SNeel Natu /* 79ba9b7bf7SNeel Natu * Callback functions to read and write memory regions. 80ba9b7bf7SNeel Natu */ 81ba9b7bf7SNeel Natu typedef int (*mem_region_read_t)(void *vm, int cpuid, uint64_t gpa, 82ba9b7bf7SNeel Natu uint64_t *rval, int rsize, void *arg); 83ba9b7bf7SNeel Natu 84ba9b7bf7SNeel Natu typedef int (*mem_region_write_t)(void *vm, int cpuid, uint64_t gpa, 85ba9b7bf7SNeel Natu uint64_t wval, int wsize, void *arg); 86ba9b7bf7SNeel Natu 87ba9b7bf7SNeel Natu /* 88ba9b7bf7SNeel Natu * Emulate the decoded 'vie' instruction. 89ba9b7bf7SNeel Natu * 90ba9b7bf7SNeel Natu * The callbacks 'mrr' and 'mrw' emulate reads and writes to the memory region 91ba9b7bf7SNeel Natu * containing 'gpa'. 'mrarg' is an opaque argument that is passed into the 92ba9b7bf7SNeel Natu * callback functions. 93ba9b7bf7SNeel Natu * 94ba9b7bf7SNeel Natu * 'void *vm' should be 'struct vm *' when called from kernel context and 95ba9b7bf7SNeel Natu * 'struct vmctx *' when called from user context. 96ba9b7bf7SNeel Natu * s 97ba9b7bf7SNeel Natu */ 98ba9b7bf7SNeel Natu int vmm_emulate_instruction(void *vm, int cpuid, uint64_t gpa, struct vie *vie, 99ba9b7bf7SNeel Natu mem_region_read_t mrr, mem_region_write_t mrw, 100ba9b7bf7SNeel Natu void *mrarg); 101ba9b7bf7SNeel Natu 102ba9b7bf7SNeel Natu #ifdef _KERNEL 103ba9b7bf7SNeel Natu /* 104ba9b7bf7SNeel Natu * APIs to fetch and decode the instruction from nested page fault handler. 105*318224bbSNeel Natu * 106*318224bbSNeel Natu * 'vie' must be initialized before calling 'vmm_fetch_instruction()' 107ba9b7bf7SNeel Natu */ 108ba9b7bf7SNeel Natu int vmm_fetch_instruction(struct vm *vm, int cpuid, 109ba9b7bf7SNeel Natu uint64_t rip, int inst_length, uint64_t cr3, 110ba9b7bf7SNeel Natu struct vie *vie); 111ba9b7bf7SNeel Natu 112*318224bbSNeel Natu void vie_init(struct vie *vie); 113*318224bbSNeel Natu 11466f71b7dSNeel Natu /* 11566f71b7dSNeel Natu * Decode the instruction fetched into 'vie' so it can be emulated. 11666f71b7dSNeel Natu * 11766f71b7dSNeel Natu * 'gla' is the guest linear address provided by the hardware assist 11866f71b7dSNeel Natu * that caused the nested page table fault. It is used to verify that 11966f71b7dSNeel Natu * the software instruction decoding is in agreement with the hardware. 12066f71b7dSNeel Natu * 12166f71b7dSNeel Natu * Some hardware assists do not provide the 'gla' to the hypervisor. 12266f71b7dSNeel Natu * To skip the 'gla' verification for this or any other reason pass 12366f71b7dSNeel Natu * in VIE_INVALID_GLA instead. 12466f71b7dSNeel Natu */ 12566f71b7dSNeel Natu #define VIE_INVALID_GLA (1UL << 63) /* a non-canonical address */ 126ba9b7bf7SNeel Natu int vmm_decode_instruction(struct vm *vm, int cpuid, 127ba9b7bf7SNeel Natu uint64_t gla, struct vie *vie); 128ba9b7bf7SNeel Natu #endif /* _KERNEL */ 129ba9b7bf7SNeel Natu 130ba9b7bf7SNeel Natu #endif /* _VMM_INSTRUCTION_EMUL_H_ */ 131