1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 NetApp, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #ifndef _VMM_DEV_H_ 32 #define _VMM_DEV_H_ 33 34 struct vm_snapshot_meta; 35 36 #ifdef _KERNEL 37 void vmmdev_init(void); 38 int vmmdev_cleanup(void); 39 #endif 40 41 struct vm_memmap { 42 vm_paddr_t gpa; 43 int segid; /* memory segment */ 44 vm_ooffset_t segoff; /* offset into memory segment */ 45 size_t len; /* mmap length */ 46 int prot; /* RWX */ 47 int flags; 48 }; 49 #define VM_MEMMAP_F_WIRED 0x01 50 #define VM_MEMMAP_F_IOMMU 0x02 51 52 #define VM_MEMSEG_NAME(m) ((m)->name[0] != '\0' ? (m)->name : NULL) 53 struct vm_memseg { 54 int segid; 55 size_t len; 56 char name[VM_MAX_SUFFIXLEN + 1]; 57 }; 58 59 struct vm_register { 60 int cpuid; 61 int regnum; /* enum vm_reg_name */ 62 uint64_t regval; 63 }; 64 65 struct vm_seg_desc { /* data or code segment */ 66 int cpuid; 67 int regnum; /* enum vm_reg_name */ 68 struct seg_desc desc; 69 }; 70 71 struct vm_register_set { 72 int cpuid; 73 unsigned int count; 74 const int *regnums; /* enum vm_reg_name */ 75 uint64_t *regvals; 76 }; 77 78 struct vm_run { 79 int cpuid; 80 struct vm_exit vm_exit; 81 }; 82 83 struct vm_exception { 84 int cpuid; 85 int vector; 86 uint32_t error_code; 87 int error_code_valid; 88 int restart_instruction; 89 }; 90 91 struct vm_lapic_msi { 92 uint64_t msg; 93 uint64_t addr; 94 }; 95 96 struct vm_lapic_irq { 97 int cpuid; 98 int vector; 99 }; 100 101 struct vm_ioapic_irq { 102 int irq; 103 }; 104 105 struct vm_isa_irq { 106 int atpic_irq; 107 int ioapic_irq; 108 }; 109 110 struct vm_isa_irq_trigger { 111 int atpic_irq; 112 enum vm_intr_trigger trigger; 113 }; 114 115 struct vm_capability { 116 int cpuid; 117 enum vm_cap_type captype; 118 int capval; 119 int allcpus; 120 }; 121 122 struct vm_pptdev { 123 int bus; 124 int slot; 125 int func; 126 }; 127 128 struct vm_pptdev_mmio { 129 int bus; 130 int slot; 131 int func; 132 vm_paddr_t gpa; 133 vm_paddr_t hpa; 134 size_t len; 135 }; 136 137 struct vm_pptdev_msi { 138 int vcpu; 139 int bus; 140 int slot; 141 int func; 142 int numvec; /* 0 means disabled */ 143 uint64_t msg; 144 uint64_t addr; 145 }; 146 147 struct vm_pptdev_msix { 148 int vcpu; 149 int bus; 150 int slot; 151 int func; 152 int idx; 153 uint64_t msg; 154 uint32_t vector_control; 155 uint64_t addr; 156 }; 157 158 struct vm_nmi { 159 int cpuid; 160 }; 161 162 #define MAX_VM_STATS 64 163 struct vm_stats { 164 int cpuid; /* in */ 165 int num_entries; /* out */ 166 struct timeval tv; 167 uint64_t statbuf[MAX_VM_STATS]; 168 }; 169 170 struct vm_stat_desc { 171 int index; /* in */ 172 char desc[128]; /* out */ 173 }; 174 175 struct vm_x2apic { 176 int cpuid; 177 enum x2apic_state state; 178 }; 179 180 struct vm_gpa_pte { 181 uint64_t gpa; /* in */ 182 uint64_t pte[4]; /* out */ 183 int ptenum; 184 }; 185 186 struct vm_hpet_cap { 187 uint32_t capabilities; /* lower 32 bits of HPET capabilities */ 188 }; 189 190 struct vm_suspend { 191 enum vm_suspend_how how; 192 }; 193 194 struct vm_gla2gpa { 195 int vcpuid; /* inputs */ 196 int prot; /* PROT_READ or PROT_WRITE */ 197 uint64_t gla; 198 struct vm_guest_paging paging; 199 int fault; /* outputs */ 200 uint64_t gpa; 201 }; 202 203 struct vm_activate_cpu { 204 int vcpuid; 205 }; 206 207 struct vm_cpuset { 208 int which; 209 int cpusetsize; 210 cpuset_t *cpus; 211 }; 212 #define VM_ACTIVE_CPUS 0 213 #define VM_SUSPENDED_CPUS 1 214 #define VM_DEBUG_CPUS 2 215 216 struct vm_intinfo { 217 int vcpuid; 218 uint64_t info1; 219 uint64_t info2; 220 }; 221 222 struct vm_rtc_time { 223 time_t secs; 224 }; 225 226 struct vm_rtc_data { 227 int offset; 228 uint8_t value; 229 }; 230 231 struct vm_cpu_topology { 232 uint16_t sockets; 233 uint16_t cores; 234 uint16_t threads; 235 uint16_t maxcpus; 236 }; 237 238 enum { 239 /* general routines */ 240 IOCNUM_ABIVERS = 0, 241 IOCNUM_RUN = 1, 242 IOCNUM_SET_CAPABILITY = 2, 243 IOCNUM_GET_CAPABILITY = 3, 244 IOCNUM_SUSPEND = 4, 245 IOCNUM_REINIT = 5, 246 247 /* memory apis */ 248 IOCNUM_MAP_MEMORY = 10, /* deprecated */ 249 IOCNUM_GET_MEMORY_SEG = 11, /* deprecated */ 250 IOCNUM_GET_GPA_PMAP = 12, 251 IOCNUM_GLA2GPA = 13, 252 IOCNUM_ALLOC_MEMSEG = 14, 253 IOCNUM_GET_MEMSEG = 15, 254 IOCNUM_MMAP_MEMSEG = 16, 255 IOCNUM_MMAP_GETNEXT = 17, 256 IOCNUM_GLA2GPA_NOFAULT = 18, 257 258 /* register/state accessors */ 259 IOCNUM_SET_REGISTER = 20, 260 IOCNUM_GET_REGISTER = 21, 261 IOCNUM_SET_SEGMENT_DESCRIPTOR = 22, 262 IOCNUM_GET_SEGMENT_DESCRIPTOR = 23, 263 IOCNUM_SET_REGISTER_SET = 24, 264 IOCNUM_GET_REGISTER_SET = 25, 265 266 /* interrupt injection */ 267 IOCNUM_GET_INTINFO = 28, 268 IOCNUM_SET_INTINFO = 29, 269 IOCNUM_INJECT_EXCEPTION = 30, 270 IOCNUM_LAPIC_IRQ = 31, 271 IOCNUM_INJECT_NMI = 32, 272 IOCNUM_IOAPIC_ASSERT_IRQ = 33, 273 IOCNUM_IOAPIC_DEASSERT_IRQ = 34, 274 IOCNUM_IOAPIC_PULSE_IRQ = 35, 275 IOCNUM_LAPIC_MSI = 36, 276 IOCNUM_LAPIC_LOCAL_IRQ = 37, 277 IOCNUM_IOAPIC_PINCOUNT = 38, 278 IOCNUM_RESTART_INSTRUCTION = 39, 279 280 /* PCI pass-thru */ 281 IOCNUM_BIND_PPTDEV = 40, 282 IOCNUM_UNBIND_PPTDEV = 41, 283 IOCNUM_MAP_PPTDEV_MMIO = 42, 284 IOCNUM_PPTDEV_MSI = 43, 285 IOCNUM_PPTDEV_MSIX = 44, 286 287 /* statistics */ 288 IOCNUM_VM_STATS = 50, 289 IOCNUM_VM_STAT_DESC = 51, 290 291 /* kernel device state */ 292 IOCNUM_SET_X2APIC_STATE = 60, 293 IOCNUM_GET_X2APIC_STATE = 61, 294 IOCNUM_GET_HPET_CAPABILITIES = 62, 295 296 /* CPU Topology */ 297 IOCNUM_SET_TOPOLOGY = 63, 298 IOCNUM_GET_TOPOLOGY = 64, 299 300 /* legacy interrupt injection */ 301 IOCNUM_ISA_ASSERT_IRQ = 80, 302 IOCNUM_ISA_DEASSERT_IRQ = 81, 303 IOCNUM_ISA_PULSE_IRQ = 82, 304 IOCNUM_ISA_SET_IRQ_TRIGGER = 83, 305 306 /* vm_cpuset */ 307 IOCNUM_ACTIVATE_CPU = 90, 308 IOCNUM_GET_CPUSET = 91, 309 IOCNUM_SUSPEND_CPU = 92, 310 IOCNUM_RESUME_CPU = 93, 311 312 /* RTC */ 313 IOCNUM_RTC_READ = 100, 314 IOCNUM_RTC_WRITE = 101, 315 IOCNUM_RTC_SETTIME = 102, 316 IOCNUM_RTC_GETTIME = 103, 317 318 /* checkpoint */ 319 IOCNUM_SNAPSHOT_REQ = 113, 320 321 IOCNUM_RESTORE_TIME = 115 322 }; 323 324 #define VM_RUN \ 325 _IOWR('v', IOCNUM_RUN, struct vm_run) 326 #define VM_SUSPEND \ 327 _IOW('v', IOCNUM_SUSPEND, struct vm_suspend) 328 #define VM_REINIT \ 329 _IO('v', IOCNUM_REINIT) 330 #define VM_ALLOC_MEMSEG \ 331 _IOW('v', IOCNUM_ALLOC_MEMSEG, struct vm_memseg) 332 #define VM_GET_MEMSEG \ 333 _IOWR('v', IOCNUM_GET_MEMSEG, struct vm_memseg) 334 #define VM_MMAP_MEMSEG \ 335 _IOW('v', IOCNUM_MMAP_MEMSEG, struct vm_memmap) 336 #define VM_MMAP_GETNEXT \ 337 _IOWR('v', IOCNUM_MMAP_GETNEXT, struct vm_memmap) 338 #define VM_SET_REGISTER \ 339 _IOW('v', IOCNUM_SET_REGISTER, struct vm_register) 340 #define VM_GET_REGISTER \ 341 _IOWR('v', IOCNUM_GET_REGISTER, struct vm_register) 342 #define VM_SET_SEGMENT_DESCRIPTOR \ 343 _IOW('v', IOCNUM_SET_SEGMENT_DESCRIPTOR, struct vm_seg_desc) 344 #define VM_GET_SEGMENT_DESCRIPTOR \ 345 _IOWR('v', IOCNUM_GET_SEGMENT_DESCRIPTOR, struct vm_seg_desc) 346 #define VM_SET_REGISTER_SET \ 347 _IOW('v', IOCNUM_SET_REGISTER_SET, struct vm_register_set) 348 #define VM_GET_REGISTER_SET \ 349 _IOWR('v', IOCNUM_GET_REGISTER_SET, struct vm_register_set) 350 #define VM_INJECT_EXCEPTION \ 351 _IOW('v', IOCNUM_INJECT_EXCEPTION, struct vm_exception) 352 #define VM_LAPIC_IRQ \ 353 _IOW('v', IOCNUM_LAPIC_IRQ, struct vm_lapic_irq) 354 #define VM_LAPIC_LOCAL_IRQ \ 355 _IOW('v', IOCNUM_LAPIC_LOCAL_IRQ, struct vm_lapic_irq) 356 #define VM_LAPIC_MSI \ 357 _IOW('v', IOCNUM_LAPIC_MSI, struct vm_lapic_msi) 358 #define VM_IOAPIC_ASSERT_IRQ \ 359 _IOW('v', IOCNUM_IOAPIC_ASSERT_IRQ, struct vm_ioapic_irq) 360 #define VM_IOAPIC_DEASSERT_IRQ \ 361 _IOW('v', IOCNUM_IOAPIC_DEASSERT_IRQ, struct vm_ioapic_irq) 362 #define VM_IOAPIC_PULSE_IRQ \ 363 _IOW('v', IOCNUM_IOAPIC_PULSE_IRQ, struct vm_ioapic_irq) 364 #define VM_IOAPIC_PINCOUNT \ 365 _IOR('v', IOCNUM_IOAPIC_PINCOUNT, int) 366 #define VM_ISA_ASSERT_IRQ \ 367 _IOW('v', IOCNUM_ISA_ASSERT_IRQ, struct vm_isa_irq) 368 #define VM_ISA_DEASSERT_IRQ \ 369 _IOW('v', IOCNUM_ISA_DEASSERT_IRQ, struct vm_isa_irq) 370 #define VM_ISA_PULSE_IRQ \ 371 _IOW('v', IOCNUM_ISA_PULSE_IRQ, struct vm_isa_irq) 372 #define VM_ISA_SET_IRQ_TRIGGER \ 373 _IOW('v', IOCNUM_ISA_SET_IRQ_TRIGGER, struct vm_isa_irq_trigger) 374 #define VM_SET_CAPABILITY \ 375 _IOW('v', IOCNUM_SET_CAPABILITY, struct vm_capability) 376 #define VM_GET_CAPABILITY \ 377 _IOWR('v', IOCNUM_GET_CAPABILITY, struct vm_capability) 378 #define VM_BIND_PPTDEV \ 379 _IOW('v', IOCNUM_BIND_PPTDEV, struct vm_pptdev) 380 #define VM_UNBIND_PPTDEV \ 381 _IOW('v', IOCNUM_UNBIND_PPTDEV, struct vm_pptdev) 382 #define VM_MAP_PPTDEV_MMIO \ 383 _IOW('v', IOCNUM_MAP_PPTDEV_MMIO, struct vm_pptdev_mmio) 384 #define VM_PPTDEV_MSI \ 385 _IOW('v', IOCNUM_PPTDEV_MSI, struct vm_pptdev_msi) 386 #define VM_PPTDEV_MSIX \ 387 _IOW('v', IOCNUM_PPTDEV_MSIX, struct vm_pptdev_msix) 388 #define VM_INJECT_NMI \ 389 _IOW('v', IOCNUM_INJECT_NMI, struct vm_nmi) 390 #define VM_STATS \ 391 _IOWR('v', IOCNUM_VM_STATS, struct vm_stats) 392 #define VM_STAT_DESC \ 393 _IOWR('v', IOCNUM_VM_STAT_DESC, struct vm_stat_desc) 394 #define VM_SET_X2APIC_STATE \ 395 _IOW('v', IOCNUM_SET_X2APIC_STATE, struct vm_x2apic) 396 #define VM_GET_X2APIC_STATE \ 397 _IOWR('v', IOCNUM_GET_X2APIC_STATE, struct vm_x2apic) 398 #define VM_GET_HPET_CAPABILITIES \ 399 _IOR('v', IOCNUM_GET_HPET_CAPABILITIES, struct vm_hpet_cap) 400 #define VM_SET_TOPOLOGY \ 401 _IOW('v', IOCNUM_SET_TOPOLOGY, struct vm_cpu_topology) 402 #define VM_GET_TOPOLOGY \ 403 _IOR('v', IOCNUM_GET_TOPOLOGY, struct vm_cpu_topology) 404 #define VM_GET_GPA_PMAP \ 405 _IOWR('v', IOCNUM_GET_GPA_PMAP, struct vm_gpa_pte) 406 #define VM_GLA2GPA \ 407 _IOWR('v', IOCNUM_GLA2GPA, struct vm_gla2gpa) 408 #define VM_GLA2GPA_NOFAULT \ 409 _IOWR('v', IOCNUM_GLA2GPA_NOFAULT, struct vm_gla2gpa) 410 #define VM_ACTIVATE_CPU \ 411 _IOW('v', IOCNUM_ACTIVATE_CPU, struct vm_activate_cpu) 412 #define VM_GET_CPUS \ 413 _IOW('v', IOCNUM_GET_CPUSET, struct vm_cpuset) 414 #define VM_SUSPEND_CPU \ 415 _IOW('v', IOCNUM_SUSPEND_CPU, struct vm_activate_cpu) 416 #define VM_RESUME_CPU \ 417 _IOW('v', IOCNUM_RESUME_CPU, struct vm_activate_cpu) 418 #define VM_SET_INTINFO \ 419 _IOW('v', IOCNUM_SET_INTINFO, struct vm_intinfo) 420 #define VM_GET_INTINFO \ 421 _IOWR('v', IOCNUM_GET_INTINFO, struct vm_intinfo) 422 #define VM_RTC_WRITE \ 423 _IOW('v', IOCNUM_RTC_WRITE, struct vm_rtc_data) 424 #define VM_RTC_READ \ 425 _IOWR('v', IOCNUM_RTC_READ, struct vm_rtc_data) 426 #define VM_RTC_SETTIME \ 427 _IOW('v', IOCNUM_RTC_SETTIME, struct vm_rtc_time) 428 #define VM_RTC_GETTIME \ 429 _IOR('v', IOCNUM_RTC_GETTIME, struct vm_rtc_time) 430 #define VM_RESTART_INSTRUCTION \ 431 _IOW('v', IOCNUM_RESTART_INSTRUCTION, int) 432 #define VM_SNAPSHOT_REQ \ 433 _IOWR('v', IOCNUM_SNAPSHOT_REQ, struct vm_snapshot_meta) 434 #define VM_RESTORE_TIME \ 435 _IOWR('v', IOCNUM_RESTORE_TIME, int) 436 #endif 437