1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 NetApp, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #ifndef _VMM_DEV_H_ 32 #define _VMM_DEV_H_ 33 34 struct vm_snapshot_meta; 35 36 #ifdef _KERNEL 37 void vmmdev_init(void); 38 int vmmdev_cleanup(void); 39 #endif 40 41 struct vm_memmap { 42 vm_paddr_t gpa; 43 int segid; /* memory segment */ 44 vm_ooffset_t segoff; /* offset into memory segment */ 45 size_t len; /* mmap length */ 46 int prot; /* RWX */ 47 int flags; 48 }; 49 #define VM_MEMMAP_F_WIRED 0x01 50 #define VM_MEMMAP_F_IOMMU 0x02 51 52 struct vm_munmap { 53 vm_paddr_t gpa; 54 size_t len; 55 }; 56 57 #define VM_MEMSEG_NAME(m) ((m)->name[0] != '\0' ? (m)->name : NULL) 58 struct vm_memseg { 59 int segid; 60 size_t len; 61 char name[VM_MAX_SUFFIXLEN + 1]; 62 }; 63 64 struct vm_memseg_fbsd12 { 65 int segid; 66 size_t len; 67 char name[64]; 68 }; 69 _Static_assert(sizeof(struct vm_memseg_fbsd12) == 80, "COMPAT_FREEBSD12 ABI"); 70 71 struct vm_register { 72 int cpuid; 73 int regnum; /* enum vm_reg_name */ 74 uint64_t regval; 75 }; 76 77 struct vm_seg_desc { /* data or code segment */ 78 int cpuid; 79 int regnum; /* enum vm_reg_name */ 80 struct seg_desc desc; 81 }; 82 83 struct vm_register_set { 84 int cpuid; 85 unsigned int count; 86 const int *regnums; /* enum vm_reg_name */ 87 uint64_t *regvals; 88 }; 89 90 struct vm_run { 91 int cpuid; 92 struct vm_exit vm_exit; 93 }; 94 95 struct vm_exception { 96 int cpuid; 97 int vector; 98 uint32_t error_code; 99 int error_code_valid; 100 int restart_instruction; 101 }; 102 103 struct vm_lapic_msi { 104 uint64_t msg; 105 uint64_t addr; 106 }; 107 108 struct vm_lapic_irq { 109 int cpuid; 110 int vector; 111 }; 112 113 struct vm_ioapic_irq { 114 int irq; 115 }; 116 117 struct vm_isa_irq { 118 int atpic_irq; 119 int ioapic_irq; 120 }; 121 122 struct vm_isa_irq_trigger { 123 int atpic_irq; 124 enum vm_intr_trigger trigger; 125 }; 126 127 struct vm_capability { 128 int cpuid; 129 enum vm_cap_type captype; 130 int capval; 131 int allcpus; 132 }; 133 134 struct vm_pptdev { 135 int bus; 136 int slot; 137 int func; 138 }; 139 140 struct vm_pptdev_mmio { 141 int bus; 142 int slot; 143 int func; 144 vm_paddr_t gpa; 145 vm_paddr_t hpa; 146 size_t len; 147 }; 148 149 struct vm_pptdev_msi { 150 int vcpu; 151 int bus; 152 int slot; 153 int func; 154 int numvec; /* 0 means disabled */ 155 uint64_t msg; 156 uint64_t addr; 157 }; 158 159 struct vm_pptdev_msix { 160 int vcpu; 161 int bus; 162 int slot; 163 int func; 164 int idx; 165 uint64_t msg; 166 uint32_t vector_control; 167 uint64_t addr; 168 }; 169 170 struct vm_nmi { 171 int cpuid; 172 }; 173 174 #define MAX_VM_STATS 64 175 struct vm_stats { 176 int cpuid; /* in */ 177 int num_entries; /* out */ 178 struct timeval tv; 179 uint64_t statbuf[MAX_VM_STATS]; 180 }; 181 182 struct vm_stat_desc { 183 int index; /* in */ 184 char desc[128]; /* out */ 185 }; 186 187 struct vm_x2apic { 188 int cpuid; 189 enum x2apic_state state; 190 }; 191 192 struct vm_gpa_pte { 193 uint64_t gpa; /* in */ 194 uint64_t pte[4]; /* out */ 195 int ptenum; 196 }; 197 198 struct vm_hpet_cap { 199 uint32_t capabilities; /* lower 32 bits of HPET capabilities */ 200 }; 201 202 struct vm_suspend { 203 enum vm_suspend_how how; 204 }; 205 206 struct vm_gla2gpa { 207 int vcpuid; /* inputs */ 208 int prot; /* PROT_READ or PROT_WRITE */ 209 uint64_t gla; 210 struct vm_guest_paging paging; 211 int fault; /* outputs */ 212 uint64_t gpa; 213 }; 214 215 struct vm_activate_cpu { 216 int vcpuid; 217 }; 218 219 struct vm_cpuset { 220 int which; 221 int cpusetsize; 222 cpuset_t *cpus; 223 }; 224 #define VM_ACTIVE_CPUS 0 225 #define VM_SUSPENDED_CPUS 1 226 #define VM_DEBUG_CPUS 2 227 228 struct vm_intinfo { 229 int vcpuid; 230 uint64_t info1; 231 uint64_t info2; 232 }; 233 234 struct vm_rtc_time { 235 time_t secs; 236 }; 237 238 struct vm_rtc_data { 239 int offset; 240 uint8_t value; 241 }; 242 243 struct vm_cpu_topology { 244 uint16_t sockets; 245 uint16_t cores; 246 uint16_t threads; 247 uint16_t maxcpus; 248 }; 249 250 struct vm_readwrite_kernemu_device { 251 int vcpuid; 252 unsigned access_width : 3; 253 unsigned _unused : 29; 254 uint64_t gpa; 255 uint64_t value; 256 }; 257 _Static_assert(sizeof(struct vm_readwrite_kernemu_device) == 24, "ABI"); 258 259 enum { 260 /* general routines */ 261 IOCNUM_ABIVERS = 0, 262 IOCNUM_RUN = 1, 263 IOCNUM_SET_CAPABILITY = 2, 264 IOCNUM_GET_CAPABILITY = 3, 265 IOCNUM_SUSPEND = 4, 266 IOCNUM_REINIT = 5, 267 268 /* memory apis */ 269 IOCNUM_MAP_MEMORY = 10, /* deprecated */ 270 IOCNUM_GET_MEMORY_SEG = 11, /* deprecated */ 271 IOCNUM_GET_GPA_PMAP = 12, 272 IOCNUM_GLA2GPA = 13, 273 IOCNUM_ALLOC_MEMSEG = 14, 274 IOCNUM_GET_MEMSEG = 15, 275 IOCNUM_MMAP_MEMSEG = 16, 276 IOCNUM_MMAP_GETNEXT = 17, 277 IOCNUM_GLA2GPA_NOFAULT = 18, 278 IOCNUM_MUNMAP_MEMSEG = 19, 279 280 /* register/state accessors */ 281 IOCNUM_SET_REGISTER = 20, 282 IOCNUM_GET_REGISTER = 21, 283 IOCNUM_SET_SEGMENT_DESCRIPTOR = 22, 284 IOCNUM_GET_SEGMENT_DESCRIPTOR = 23, 285 IOCNUM_SET_REGISTER_SET = 24, 286 IOCNUM_GET_REGISTER_SET = 25, 287 IOCNUM_GET_KERNEMU_DEV = 26, 288 IOCNUM_SET_KERNEMU_DEV = 27, 289 290 /* interrupt injection */ 291 IOCNUM_GET_INTINFO = 28, 292 IOCNUM_SET_INTINFO = 29, 293 IOCNUM_INJECT_EXCEPTION = 30, 294 IOCNUM_LAPIC_IRQ = 31, 295 IOCNUM_INJECT_NMI = 32, 296 IOCNUM_IOAPIC_ASSERT_IRQ = 33, 297 IOCNUM_IOAPIC_DEASSERT_IRQ = 34, 298 IOCNUM_IOAPIC_PULSE_IRQ = 35, 299 IOCNUM_LAPIC_MSI = 36, 300 IOCNUM_LAPIC_LOCAL_IRQ = 37, 301 IOCNUM_IOAPIC_PINCOUNT = 38, 302 IOCNUM_RESTART_INSTRUCTION = 39, 303 304 /* PCI pass-thru */ 305 IOCNUM_BIND_PPTDEV = 40, 306 IOCNUM_UNBIND_PPTDEV = 41, 307 IOCNUM_MAP_PPTDEV_MMIO = 42, 308 IOCNUM_PPTDEV_MSI = 43, 309 IOCNUM_PPTDEV_MSIX = 44, 310 IOCNUM_PPTDEV_DISABLE_MSIX = 45, 311 IOCNUM_UNMAP_PPTDEV_MMIO = 46, 312 313 /* statistics */ 314 IOCNUM_VM_STATS = 50, 315 IOCNUM_VM_STAT_DESC = 51, 316 317 /* kernel device state */ 318 IOCNUM_SET_X2APIC_STATE = 60, 319 IOCNUM_GET_X2APIC_STATE = 61, 320 IOCNUM_GET_HPET_CAPABILITIES = 62, 321 322 /* CPU Topology */ 323 IOCNUM_SET_TOPOLOGY = 63, 324 IOCNUM_GET_TOPOLOGY = 64, 325 326 /* legacy interrupt injection */ 327 IOCNUM_ISA_ASSERT_IRQ = 80, 328 IOCNUM_ISA_DEASSERT_IRQ = 81, 329 IOCNUM_ISA_PULSE_IRQ = 82, 330 IOCNUM_ISA_SET_IRQ_TRIGGER = 83, 331 332 /* vm_cpuset */ 333 IOCNUM_ACTIVATE_CPU = 90, 334 IOCNUM_GET_CPUSET = 91, 335 IOCNUM_SUSPEND_CPU = 92, 336 IOCNUM_RESUME_CPU = 93, 337 338 /* RTC */ 339 IOCNUM_RTC_READ = 100, 340 IOCNUM_RTC_WRITE = 101, 341 IOCNUM_RTC_SETTIME = 102, 342 IOCNUM_RTC_GETTIME = 103, 343 344 /* checkpoint */ 345 IOCNUM_SNAPSHOT_REQ = 113, 346 347 IOCNUM_RESTORE_TIME = 115 348 }; 349 350 #define VM_RUN \ 351 _IOWR('v', IOCNUM_RUN, struct vm_run) 352 #define VM_SUSPEND \ 353 _IOW('v', IOCNUM_SUSPEND, struct vm_suspend) 354 #define VM_REINIT \ 355 _IO('v', IOCNUM_REINIT) 356 #define VM_ALLOC_MEMSEG_FBSD12 \ 357 _IOW('v', IOCNUM_ALLOC_MEMSEG, struct vm_memseg_fbsd12) 358 #define VM_ALLOC_MEMSEG \ 359 _IOW('v', IOCNUM_ALLOC_MEMSEG, struct vm_memseg) 360 #define VM_GET_MEMSEG_FBSD12 \ 361 _IOWR('v', IOCNUM_GET_MEMSEG, struct vm_memseg_fbsd12) 362 #define VM_GET_MEMSEG \ 363 _IOWR('v', IOCNUM_GET_MEMSEG, struct vm_memseg) 364 #define VM_MMAP_MEMSEG \ 365 _IOW('v', IOCNUM_MMAP_MEMSEG, struct vm_memmap) 366 #define VM_MMAP_GETNEXT \ 367 _IOWR('v', IOCNUM_MMAP_GETNEXT, struct vm_memmap) 368 #define VM_MUNMAP_MEMSEG \ 369 _IOW('v', IOCNUM_MUNMAP_MEMSEG, struct vm_munmap) 370 #define VM_SET_REGISTER \ 371 _IOW('v', IOCNUM_SET_REGISTER, struct vm_register) 372 #define VM_GET_REGISTER \ 373 _IOWR('v', IOCNUM_GET_REGISTER, struct vm_register) 374 #define VM_SET_SEGMENT_DESCRIPTOR \ 375 _IOW('v', IOCNUM_SET_SEGMENT_DESCRIPTOR, struct vm_seg_desc) 376 #define VM_GET_SEGMENT_DESCRIPTOR \ 377 _IOWR('v', IOCNUM_GET_SEGMENT_DESCRIPTOR, struct vm_seg_desc) 378 #define VM_SET_REGISTER_SET \ 379 _IOW('v', IOCNUM_SET_REGISTER_SET, struct vm_register_set) 380 #define VM_GET_REGISTER_SET \ 381 _IOWR('v', IOCNUM_GET_REGISTER_SET, struct vm_register_set) 382 #define VM_SET_KERNEMU_DEV \ 383 _IOW('v', IOCNUM_SET_KERNEMU_DEV, \ 384 struct vm_readwrite_kernemu_device) 385 #define VM_GET_KERNEMU_DEV \ 386 _IOWR('v', IOCNUM_GET_KERNEMU_DEV, \ 387 struct vm_readwrite_kernemu_device) 388 #define VM_INJECT_EXCEPTION \ 389 _IOW('v', IOCNUM_INJECT_EXCEPTION, struct vm_exception) 390 #define VM_LAPIC_IRQ \ 391 _IOW('v', IOCNUM_LAPIC_IRQ, struct vm_lapic_irq) 392 #define VM_LAPIC_LOCAL_IRQ \ 393 _IOW('v', IOCNUM_LAPIC_LOCAL_IRQ, struct vm_lapic_irq) 394 #define VM_LAPIC_MSI \ 395 _IOW('v', IOCNUM_LAPIC_MSI, struct vm_lapic_msi) 396 #define VM_IOAPIC_ASSERT_IRQ \ 397 _IOW('v', IOCNUM_IOAPIC_ASSERT_IRQ, struct vm_ioapic_irq) 398 #define VM_IOAPIC_DEASSERT_IRQ \ 399 _IOW('v', IOCNUM_IOAPIC_DEASSERT_IRQ, struct vm_ioapic_irq) 400 #define VM_IOAPIC_PULSE_IRQ \ 401 _IOW('v', IOCNUM_IOAPIC_PULSE_IRQ, struct vm_ioapic_irq) 402 #define VM_IOAPIC_PINCOUNT \ 403 _IOR('v', IOCNUM_IOAPIC_PINCOUNT, int) 404 #define VM_ISA_ASSERT_IRQ \ 405 _IOW('v', IOCNUM_ISA_ASSERT_IRQ, struct vm_isa_irq) 406 #define VM_ISA_DEASSERT_IRQ \ 407 _IOW('v', IOCNUM_ISA_DEASSERT_IRQ, struct vm_isa_irq) 408 #define VM_ISA_PULSE_IRQ \ 409 _IOW('v', IOCNUM_ISA_PULSE_IRQ, struct vm_isa_irq) 410 #define VM_ISA_SET_IRQ_TRIGGER \ 411 _IOW('v', IOCNUM_ISA_SET_IRQ_TRIGGER, struct vm_isa_irq_trigger) 412 #define VM_SET_CAPABILITY \ 413 _IOW('v', IOCNUM_SET_CAPABILITY, struct vm_capability) 414 #define VM_GET_CAPABILITY \ 415 _IOWR('v', IOCNUM_GET_CAPABILITY, struct vm_capability) 416 #define VM_BIND_PPTDEV \ 417 _IOW('v', IOCNUM_BIND_PPTDEV, struct vm_pptdev) 418 #define VM_UNBIND_PPTDEV \ 419 _IOW('v', IOCNUM_UNBIND_PPTDEV, struct vm_pptdev) 420 #define VM_MAP_PPTDEV_MMIO \ 421 _IOW('v', IOCNUM_MAP_PPTDEV_MMIO, struct vm_pptdev_mmio) 422 #define VM_PPTDEV_MSI \ 423 _IOW('v', IOCNUM_PPTDEV_MSI, struct vm_pptdev_msi) 424 #define VM_PPTDEV_MSIX \ 425 _IOW('v', IOCNUM_PPTDEV_MSIX, struct vm_pptdev_msix) 426 #define VM_PPTDEV_DISABLE_MSIX \ 427 _IOW('v', IOCNUM_PPTDEV_DISABLE_MSIX, struct vm_pptdev) 428 #define VM_UNMAP_PPTDEV_MMIO \ 429 _IOW('v', IOCNUM_UNMAP_PPTDEV_MMIO, struct vm_pptdev_mmio) 430 #define VM_INJECT_NMI \ 431 _IOW('v', IOCNUM_INJECT_NMI, struct vm_nmi) 432 #define VM_STATS \ 433 _IOWR('v', IOCNUM_VM_STATS, struct vm_stats) 434 #define VM_STAT_DESC \ 435 _IOWR('v', IOCNUM_VM_STAT_DESC, struct vm_stat_desc) 436 #define VM_SET_X2APIC_STATE \ 437 _IOW('v', IOCNUM_SET_X2APIC_STATE, struct vm_x2apic) 438 #define VM_GET_X2APIC_STATE \ 439 _IOWR('v', IOCNUM_GET_X2APIC_STATE, struct vm_x2apic) 440 #define VM_GET_HPET_CAPABILITIES \ 441 _IOR('v', IOCNUM_GET_HPET_CAPABILITIES, struct vm_hpet_cap) 442 #define VM_SET_TOPOLOGY \ 443 _IOW('v', IOCNUM_SET_TOPOLOGY, struct vm_cpu_topology) 444 #define VM_GET_TOPOLOGY \ 445 _IOR('v', IOCNUM_GET_TOPOLOGY, struct vm_cpu_topology) 446 #define VM_GET_GPA_PMAP \ 447 _IOWR('v', IOCNUM_GET_GPA_PMAP, struct vm_gpa_pte) 448 #define VM_GLA2GPA \ 449 _IOWR('v', IOCNUM_GLA2GPA, struct vm_gla2gpa) 450 #define VM_GLA2GPA_NOFAULT \ 451 _IOWR('v', IOCNUM_GLA2GPA_NOFAULT, struct vm_gla2gpa) 452 #define VM_ACTIVATE_CPU \ 453 _IOW('v', IOCNUM_ACTIVATE_CPU, struct vm_activate_cpu) 454 #define VM_GET_CPUS \ 455 _IOW('v', IOCNUM_GET_CPUSET, struct vm_cpuset) 456 #define VM_SUSPEND_CPU \ 457 _IOW('v', IOCNUM_SUSPEND_CPU, struct vm_activate_cpu) 458 #define VM_RESUME_CPU \ 459 _IOW('v', IOCNUM_RESUME_CPU, struct vm_activate_cpu) 460 #define VM_SET_INTINFO \ 461 _IOW('v', IOCNUM_SET_INTINFO, struct vm_intinfo) 462 #define VM_GET_INTINFO \ 463 _IOWR('v', IOCNUM_GET_INTINFO, struct vm_intinfo) 464 #define VM_RTC_WRITE \ 465 _IOW('v', IOCNUM_RTC_WRITE, struct vm_rtc_data) 466 #define VM_RTC_READ \ 467 _IOWR('v', IOCNUM_RTC_READ, struct vm_rtc_data) 468 #define VM_RTC_SETTIME \ 469 _IOW('v', IOCNUM_RTC_SETTIME, struct vm_rtc_time) 470 #define VM_RTC_GETTIME \ 471 _IOR('v', IOCNUM_RTC_GETTIME, struct vm_rtc_time) 472 #define VM_RESTART_INSTRUCTION \ 473 _IOW('v', IOCNUM_RESTART_INSTRUCTION, int) 474 #define VM_SNAPSHOT_REQ \ 475 _IOWR('v', IOCNUM_SNAPSHOT_REQ, struct vm_snapshot_meta) 476 #define VM_RESTORE_TIME \ 477 _IOWR('v', IOCNUM_RESTORE_TIME, int) 478 #endif 479