1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011 NetApp, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _VMM_DEV_H_ 30 #define _VMM_DEV_H_ 31 32 #include <sys/domainset.h> 33 34 #include <machine/vmm.h> 35 #include <machine/vmm_snapshot.h> 36 37 #include <dev/vmm/vmm_param.h> 38 39 struct vm_memmap { 40 vm_paddr_t gpa; 41 int segid; /* memory segment */ 42 vm_ooffset_t segoff; /* offset into memory segment */ 43 size_t len; /* mmap length */ 44 int prot; /* RWX */ 45 int flags; 46 }; 47 #define VM_MEMMAP_F_WIRED 0x01 48 #define VM_MEMMAP_F_IOMMU 0x02 49 50 struct vm_munmap { 51 vm_paddr_t gpa; 52 size_t len; 53 }; 54 55 #define VM_MEMSEG_NAME(m) ((m)->name[0] != '\0' ? (m)->name : NULL) 56 struct vm_memseg { 57 int segid; 58 size_t len; 59 char name[VM_MAX_SUFFIXLEN + 1]; 60 domainset_t *ds_mask; 61 size_t ds_mask_size; 62 int ds_policy; 63 }; 64 65 struct vm_register { 66 int cpuid; 67 int regnum; /* enum vm_reg_name */ 68 uint64_t regval; 69 }; 70 71 struct vm_seg_desc { /* data or code segment */ 72 int cpuid; 73 int regnum; /* enum vm_reg_name */ 74 struct seg_desc desc; 75 }; 76 77 struct vm_register_set { 78 int cpuid; 79 unsigned int count; 80 const int *regnums; /* enum vm_reg_name */ 81 uint64_t *regvals; 82 }; 83 84 struct vm_run { 85 int cpuid; 86 cpuset_t *cpuset; /* CPU set storage */ 87 size_t cpusetsize; 88 struct vm_exit *vm_exit; 89 }; 90 91 struct vm_exception { 92 int cpuid; 93 int vector; 94 uint32_t error_code; 95 int error_code_valid; 96 int restart_instruction; 97 }; 98 99 struct vm_lapic_msi { 100 uint64_t msg; 101 uint64_t addr; 102 }; 103 104 struct vm_lapic_irq { 105 int cpuid; 106 int vector; 107 }; 108 109 struct vm_ioapic_irq { 110 int irq; 111 }; 112 113 struct vm_isa_irq { 114 int atpic_irq; 115 int ioapic_irq; 116 }; 117 118 struct vm_isa_irq_trigger { 119 int atpic_irq; 120 enum vm_intr_trigger trigger; 121 }; 122 123 struct vm_capability { 124 int cpuid; 125 enum vm_cap_type captype; 126 int capval; 127 int allcpus; 128 }; 129 130 struct vm_pptdev { 131 int bus; 132 int slot; 133 int func; 134 }; 135 136 struct vm_pptdev_mmio { 137 int bus; 138 int slot; 139 int func; 140 vm_paddr_t gpa; 141 vm_paddr_t hpa; 142 size_t len; 143 }; 144 145 struct vm_pptdev_msi { 146 int vcpu; /* unused */ 147 int bus; 148 int slot; 149 int func; 150 int numvec; /* 0 means disabled */ 151 uint64_t msg; 152 uint64_t addr; 153 }; 154 155 struct vm_pptdev_msix { 156 int vcpu; /* unused */ 157 int bus; 158 int slot; 159 int func; 160 int idx; 161 uint64_t msg; 162 uint32_t vector_control; 163 uint64_t addr; 164 }; 165 166 struct vm_nmi { 167 int cpuid; 168 }; 169 170 #define MAX_VM_STATS 64 171 struct vm_stats { 172 int cpuid; /* in */ 173 int index; /* in */ 174 int num_entries; /* out */ 175 struct timeval tv; 176 uint64_t statbuf[MAX_VM_STATS]; 177 }; 178 179 struct vm_stat_desc { 180 int index; /* in */ 181 char desc[128]; /* out */ 182 }; 183 184 struct vm_x2apic { 185 int cpuid; 186 enum x2apic_state state; 187 }; 188 189 struct vm_gpa_pte { 190 uint64_t gpa; /* in */ 191 uint64_t pte[4]; /* out */ 192 int ptenum; 193 }; 194 195 struct vm_hpet_cap { 196 uint32_t capabilities; /* lower 32 bits of HPET capabilities */ 197 }; 198 199 struct vm_suspend { 200 enum vm_suspend_how how; 201 }; 202 203 struct vm_gla2gpa { 204 int vcpuid; /* inputs */ 205 int prot; /* PROT_READ or PROT_WRITE */ 206 uint64_t gla; 207 struct vm_guest_paging paging; 208 int fault; /* outputs */ 209 uint64_t gpa; 210 }; 211 212 struct vm_activate_cpu { 213 int vcpuid; 214 }; 215 216 struct vm_cpuset { 217 int which; 218 int cpusetsize; 219 cpuset_t *cpus; 220 }; 221 #define VM_ACTIVE_CPUS 0 222 #define VM_SUSPENDED_CPUS 1 223 #define VM_DEBUG_CPUS 2 224 225 struct vm_intinfo { 226 int vcpuid; 227 uint64_t info1; 228 uint64_t info2; 229 }; 230 231 struct vm_rtc_time { 232 time_t secs; 233 }; 234 235 struct vm_rtc_data { 236 int offset; 237 uint8_t value; 238 }; 239 240 struct vm_cpu_topology { 241 uint16_t sockets; 242 uint16_t cores; 243 uint16_t threads; 244 uint16_t maxcpus; 245 }; 246 247 struct vm_readwrite_kernemu_device { 248 int vcpuid; 249 unsigned access_width : 3; 250 unsigned _unused : 29; 251 uint64_t gpa; 252 uint64_t value; 253 }; 254 _Static_assert(sizeof(struct vm_readwrite_kernemu_device) == 24, "ABI"); 255 256 enum { 257 /* general routines */ 258 IOCNUM_ABIVERS = 0, 259 IOCNUM_RUN = 1, 260 IOCNUM_SET_CAPABILITY = 2, 261 IOCNUM_GET_CAPABILITY = 3, 262 IOCNUM_SUSPEND = 4, 263 IOCNUM_REINIT = 5, 264 265 /* memory apis */ 266 IOCNUM_MAP_MEMORY = 10, /* deprecated */ 267 IOCNUM_GET_MEMORY_SEG = 11, /* deprecated */ 268 IOCNUM_GET_GPA_PMAP = 12, 269 IOCNUM_GLA2GPA = 13, 270 IOCNUM_ALLOC_MEMSEG = 14, 271 IOCNUM_GET_MEMSEG = 15, 272 IOCNUM_MMAP_MEMSEG = 16, 273 IOCNUM_MMAP_GETNEXT = 17, 274 IOCNUM_GLA2GPA_NOFAULT = 18, 275 IOCNUM_MUNMAP_MEMSEG = 19, 276 277 /* register/state accessors */ 278 IOCNUM_SET_REGISTER = 20, 279 IOCNUM_GET_REGISTER = 21, 280 IOCNUM_SET_SEGMENT_DESCRIPTOR = 22, 281 IOCNUM_GET_SEGMENT_DESCRIPTOR = 23, 282 IOCNUM_SET_REGISTER_SET = 24, 283 IOCNUM_GET_REGISTER_SET = 25, 284 IOCNUM_GET_KERNEMU_DEV = 26, 285 IOCNUM_SET_KERNEMU_DEV = 27, 286 287 /* interrupt injection */ 288 IOCNUM_GET_INTINFO = 28, 289 IOCNUM_SET_INTINFO = 29, 290 IOCNUM_INJECT_EXCEPTION = 30, 291 IOCNUM_LAPIC_IRQ = 31, 292 IOCNUM_INJECT_NMI = 32, 293 IOCNUM_IOAPIC_ASSERT_IRQ = 33, 294 IOCNUM_IOAPIC_DEASSERT_IRQ = 34, 295 IOCNUM_IOAPIC_PULSE_IRQ = 35, 296 IOCNUM_LAPIC_MSI = 36, 297 IOCNUM_LAPIC_LOCAL_IRQ = 37, 298 IOCNUM_IOAPIC_PINCOUNT = 38, 299 IOCNUM_RESTART_INSTRUCTION = 39, 300 301 /* PCI pass-thru */ 302 IOCNUM_BIND_PPTDEV = 40, 303 IOCNUM_UNBIND_PPTDEV = 41, 304 IOCNUM_MAP_PPTDEV_MMIO = 42, 305 IOCNUM_PPTDEV_MSI = 43, 306 IOCNUM_PPTDEV_MSIX = 44, 307 IOCNUM_PPTDEV_DISABLE_MSIX = 45, 308 IOCNUM_UNMAP_PPTDEV_MMIO = 46, 309 IOCNUM_RESET_PPTDEV = 47, 310 311 /* statistics */ 312 IOCNUM_VM_STATS = 50, 313 IOCNUM_VM_STAT_DESC = 51, 314 315 /* kernel device state */ 316 IOCNUM_SET_X2APIC_STATE = 60, 317 IOCNUM_GET_X2APIC_STATE = 61, 318 IOCNUM_GET_HPET_CAPABILITIES = 62, 319 320 /* CPU Topology */ 321 IOCNUM_SET_TOPOLOGY = 63, 322 IOCNUM_GET_TOPOLOGY = 64, 323 324 /* legacy interrupt injection */ 325 IOCNUM_ISA_ASSERT_IRQ = 80, 326 IOCNUM_ISA_DEASSERT_IRQ = 81, 327 IOCNUM_ISA_PULSE_IRQ = 82, 328 IOCNUM_ISA_SET_IRQ_TRIGGER = 83, 329 330 /* vm_cpuset */ 331 IOCNUM_ACTIVATE_CPU = 90, 332 IOCNUM_GET_CPUSET = 91, 333 IOCNUM_SUSPEND_CPU = 92, 334 IOCNUM_RESUME_CPU = 93, 335 336 /* RTC */ 337 IOCNUM_RTC_READ = 100, 338 IOCNUM_RTC_WRITE = 101, 339 IOCNUM_RTC_SETTIME = 102, 340 IOCNUM_RTC_GETTIME = 103, 341 342 /* checkpoint */ 343 IOCNUM_SNAPSHOT_REQ = 113, 344 345 IOCNUM_RESTORE_TIME = 115 346 }; 347 348 #define VM_RUN \ 349 _IOW('v', IOCNUM_RUN, struct vm_run) 350 #define VM_SUSPEND \ 351 _IOW('v', IOCNUM_SUSPEND, struct vm_suspend) 352 #define VM_REINIT \ 353 _IO('v', IOCNUM_REINIT) 354 #define VM_ALLOC_MEMSEG \ 355 _IOW('v', IOCNUM_ALLOC_MEMSEG, struct vm_memseg) 356 #define VM_GET_MEMSEG \ 357 _IOWR('v', IOCNUM_GET_MEMSEG, struct vm_memseg) 358 #define VM_MMAP_MEMSEG \ 359 _IOW('v', IOCNUM_MMAP_MEMSEG, struct vm_memmap) 360 #define VM_MMAP_GETNEXT \ 361 _IOWR('v', IOCNUM_MMAP_GETNEXT, struct vm_memmap) 362 #define VM_MUNMAP_MEMSEG \ 363 _IOW('v', IOCNUM_MUNMAP_MEMSEG, struct vm_munmap) 364 #define VM_SET_REGISTER \ 365 _IOW('v', IOCNUM_SET_REGISTER, struct vm_register) 366 #define VM_GET_REGISTER \ 367 _IOWR('v', IOCNUM_GET_REGISTER, struct vm_register) 368 #define VM_SET_SEGMENT_DESCRIPTOR \ 369 _IOW('v', IOCNUM_SET_SEGMENT_DESCRIPTOR, struct vm_seg_desc) 370 #define VM_GET_SEGMENT_DESCRIPTOR \ 371 _IOWR('v', IOCNUM_GET_SEGMENT_DESCRIPTOR, struct vm_seg_desc) 372 #define VM_SET_REGISTER_SET \ 373 _IOW('v', IOCNUM_SET_REGISTER_SET, struct vm_register_set) 374 #define VM_GET_REGISTER_SET \ 375 _IOWR('v', IOCNUM_GET_REGISTER_SET, struct vm_register_set) 376 #define VM_SET_KERNEMU_DEV \ 377 _IOW('v', IOCNUM_SET_KERNEMU_DEV, \ 378 struct vm_readwrite_kernemu_device) 379 #define VM_GET_KERNEMU_DEV \ 380 _IOWR('v', IOCNUM_GET_KERNEMU_DEV, \ 381 struct vm_readwrite_kernemu_device) 382 #define VM_INJECT_EXCEPTION \ 383 _IOW('v', IOCNUM_INJECT_EXCEPTION, struct vm_exception) 384 #define VM_LAPIC_IRQ \ 385 _IOW('v', IOCNUM_LAPIC_IRQ, struct vm_lapic_irq) 386 #define VM_LAPIC_LOCAL_IRQ \ 387 _IOW('v', IOCNUM_LAPIC_LOCAL_IRQ, struct vm_lapic_irq) 388 #define VM_LAPIC_MSI \ 389 _IOW('v', IOCNUM_LAPIC_MSI, struct vm_lapic_msi) 390 #define VM_IOAPIC_ASSERT_IRQ \ 391 _IOW('v', IOCNUM_IOAPIC_ASSERT_IRQ, struct vm_ioapic_irq) 392 #define VM_IOAPIC_DEASSERT_IRQ \ 393 _IOW('v', IOCNUM_IOAPIC_DEASSERT_IRQ, struct vm_ioapic_irq) 394 #define VM_IOAPIC_PULSE_IRQ \ 395 _IOW('v', IOCNUM_IOAPIC_PULSE_IRQ, struct vm_ioapic_irq) 396 #define VM_IOAPIC_PINCOUNT \ 397 _IOR('v', IOCNUM_IOAPIC_PINCOUNT, int) 398 #define VM_ISA_ASSERT_IRQ \ 399 _IOW('v', IOCNUM_ISA_ASSERT_IRQ, struct vm_isa_irq) 400 #define VM_ISA_DEASSERT_IRQ \ 401 _IOW('v', IOCNUM_ISA_DEASSERT_IRQ, struct vm_isa_irq) 402 #define VM_ISA_PULSE_IRQ \ 403 _IOW('v', IOCNUM_ISA_PULSE_IRQ, struct vm_isa_irq) 404 #define VM_ISA_SET_IRQ_TRIGGER \ 405 _IOW('v', IOCNUM_ISA_SET_IRQ_TRIGGER, struct vm_isa_irq_trigger) 406 #define VM_SET_CAPABILITY \ 407 _IOW('v', IOCNUM_SET_CAPABILITY, struct vm_capability) 408 #define VM_GET_CAPABILITY \ 409 _IOWR('v', IOCNUM_GET_CAPABILITY, struct vm_capability) 410 #define VM_BIND_PPTDEV \ 411 _IOW('v', IOCNUM_BIND_PPTDEV, struct vm_pptdev) 412 #define VM_UNBIND_PPTDEV \ 413 _IOW('v', IOCNUM_UNBIND_PPTDEV, struct vm_pptdev) 414 #define VM_MAP_PPTDEV_MMIO \ 415 _IOW('v', IOCNUM_MAP_PPTDEV_MMIO, struct vm_pptdev_mmio) 416 #define VM_PPTDEV_MSI \ 417 _IOW('v', IOCNUM_PPTDEV_MSI, struct vm_pptdev_msi) 418 #define VM_PPTDEV_MSIX \ 419 _IOW('v', IOCNUM_PPTDEV_MSIX, struct vm_pptdev_msix) 420 #define VM_PPTDEV_DISABLE_MSIX \ 421 _IOW('v', IOCNUM_PPTDEV_DISABLE_MSIX, struct vm_pptdev) 422 #define VM_UNMAP_PPTDEV_MMIO \ 423 _IOW('v', IOCNUM_UNMAP_PPTDEV_MMIO, struct vm_pptdev_mmio) 424 #define VM_RESET_PPTDEV \ 425 _IOW('v', IOCNUM_RESET_PPTDEV, struct vm_pptdev) 426 #define VM_INJECT_NMI \ 427 _IOW('v', IOCNUM_INJECT_NMI, struct vm_nmi) 428 #define VM_STATS \ 429 _IOWR('v', IOCNUM_VM_STATS, struct vm_stats) 430 #define VM_STAT_DESC \ 431 _IOWR('v', IOCNUM_VM_STAT_DESC, struct vm_stat_desc) 432 #define VM_SET_X2APIC_STATE \ 433 _IOW('v', IOCNUM_SET_X2APIC_STATE, struct vm_x2apic) 434 #define VM_GET_X2APIC_STATE \ 435 _IOWR('v', IOCNUM_GET_X2APIC_STATE, struct vm_x2apic) 436 #define VM_GET_HPET_CAPABILITIES \ 437 _IOR('v', IOCNUM_GET_HPET_CAPABILITIES, struct vm_hpet_cap) 438 #define VM_SET_TOPOLOGY \ 439 _IOW('v', IOCNUM_SET_TOPOLOGY, struct vm_cpu_topology) 440 #define VM_GET_TOPOLOGY \ 441 _IOR('v', IOCNUM_GET_TOPOLOGY, struct vm_cpu_topology) 442 #define VM_GET_GPA_PMAP \ 443 _IOWR('v', IOCNUM_GET_GPA_PMAP, struct vm_gpa_pte) 444 #define VM_GLA2GPA \ 445 _IOWR('v', IOCNUM_GLA2GPA, struct vm_gla2gpa) 446 #define VM_GLA2GPA_NOFAULT \ 447 _IOWR('v', IOCNUM_GLA2GPA_NOFAULT, struct vm_gla2gpa) 448 #define VM_ACTIVATE_CPU \ 449 _IOW('v', IOCNUM_ACTIVATE_CPU, struct vm_activate_cpu) 450 #define VM_GET_CPUS \ 451 _IOW('v', IOCNUM_GET_CPUSET, struct vm_cpuset) 452 #define VM_SUSPEND_CPU \ 453 _IOW('v', IOCNUM_SUSPEND_CPU, struct vm_activate_cpu) 454 #define VM_RESUME_CPU \ 455 _IOW('v', IOCNUM_RESUME_CPU, struct vm_activate_cpu) 456 #define VM_SET_INTINFO \ 457 _IOW('v', IOCNUM_SET_INTINFO, struct vm_intinfo) 458 #define VM_GET_INTINFO \ 459 _IOWR('v', IOCNUM_GET_INTINFO, struct vm_intinfo) 460 #define VM_RTC_WRITE \ 461 _IOW('v', IOCNUM_RTC_WRITE, struct vm_rtc_data) 462 #define VM_RTC_READ \ 463 _IOWR('v', IOCNUM_RTC_READ, struct vm_rtc_data) 464 #define VM_RTC_SETTIME \ 465 _IOW('v', IOCNUM_RTC_SETTIME, struct vm_rtc_time) 466 #define VM_RTC_GETTIME \ 467 _IOR('v', IOCNUM_RTC_GETTIME, struct vm_rtc_time) 468 #define VM_RESTART_INSTRUCTION \ 469 _IOW('v', IOCNUM_RESTART_INSTRUCTION, int) 470 #define VM_SNAPSHOT_REQ \ 471 _IOWR('v', IOCNUM_SNAPSHOT_REQ, struct vm_snapshot_meta) 472 #define VM_RESTORE_TIME \ 473 _IOWR('v', IOCNUM_RESTORE_TIME, int) 474 #endif 475