1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 NetApp, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #ifndef _VMM_DEV_H_ 32 #define _VMM_DEV_H_ 33 34 #ifdef _KERNEL 35 void vmmdev_init(void); 36 int vmmdev_cleanup(void); 37 #endif 38 39 struct vm_memmap { 40 vm_paddr_t gpa; 41 int segid; /* memory segment */ 42 vm_ooffset_t segoff; /* offset into memory segment */ 43 size_t len; /* mmap length */ 44 int prot; /* RWX */ 45 int flags; 46 }; 47 #define VM_MEMMAP_F_WIRED 0x01 48 #define VM_MEMMAP_F_IOMMU 0x02 49 50 #define VM_MEMSEG_NAME(m) ((m)->name[0] != '\0' ? (m)->name : NULL) 51 struct vm_memseg { 52 int segid; 53 size_t len; 54 char name[SPECNAMELEN + 1]; 55 }; 56 57 struct vm_register { 58 int cpuid; 59 int regnum; /* enum vm_reg_name */ 60 uint64_t regval; 61 }; 62 63 struct vm_seg_desc { /* data or code segment */ 64 int cpuid; 65 int regnum; /* enum vm_reg_name */ 66 struct seg_desc desc; 67 }; 68 69 struct vm_run { 70 int cpuid; 71 struct vm_exit vm_exit; 72 }; 73 74 struct vm_exception { 75 int cpuid; 76 int vector; 77 uint32_t error_code; 78 int error_code_valid; 79 int restart_instruction; 80 }; 81 82 struct vm_lapic_msi { 83 uint64_t msg; 84 uint64_t addr; 85 }; 86 87 struct vm_lapic_irq { 88 int cpuid; 89 int vector; 90 }; 91 92 struct vm_ioapic_irq { 93 int irq; 94 }; 95 96 struct vm_isa_irq { 97 int atpic_irq; 98 int ioapic_irq; 99 }; 100 101 struct vm_isa_irq_trigger { 102 int atpic_irq; 103 enum vm_intr_trigger trigger; 104 }; 105 106 struct vm_capability { 107 int cpuid; 108 enum vm_cap_type captype; 109 int capval; 110 int allcpus; 111 }; 112 113 struct vm_pptdev { 114 int bus; 115 int slot; 116 int func; 117 }; 118 119 struct vm_pptdev_mmio { 120 int bus; 121 int slot; 122 int func; 123 vm_paddr_t gpa; 124 vm_paddr_t hpa; 125 size_t len; 126 }; 127 128 struct vm_pptdev_msi { 129 int vcpu; 130 int bus; 131 int slot; 132 int func; 133 int numvec; /* 0 means disabled */ 134 uint64_t msg; 135 uint64_t addr; 136 }; 137 138 struct vm_pptdev_msix { 139 int vcpu; 140 int bus; 141 int slot; 142 int func; 143 int idx; 144 uint64_t msg; 145 uint32_t vector_control; 146 uint64_t addr; 147 }; 148 149 struct vm_nmi { 150 int cpuid; 151 }; 152 153 #define MAX_VM_STATS 64 154 struct vm_stats { 155 int cpuid; /* in */ 156 int num_entries; /* out */ 157 struct timeval tv; 158 uint64_t statbuf[MAX_VM_STATS]; 159 }; 160 161 struct vm_stat_desc { 162 int index; /* in */ 163 char desc[128]; /* out */ 164 }; 165 166 struct vm_x2apic { 167 int cpuid; 168 enum x2apic_state state; 169 }; 170 171 struct vm_gpa_pte { 172 uint64_t gpa; /* in */ 173 uint64_t pte[4]; /* out */ 174 int ptenum; 175 }; 176 177 struct vm_hpet_cap { 178 uint32_t capabilities; /* lower 32 bits of HPET capabilities */ 179 }; 180 181 struct vm_suspend { 182 enum vm_suspend_how how; 183 }; 184 185 struct vm_gla2gpa { 186 int vcpuid; /* inputs */ 187 int prot; /* PROT_READ or PROT_WRITE */ 188 uint64_t gla; 189 struct vm_guest_paging paging; 190 int fault; /* outputs */ 191 uint64_t gpa; 192 }; 193 194 struct vm_activate_cpu { 195 int vcpuid; 196 }; 197 198 struct vm_cpuset { 199 int which; 200 int cpusetsize; 201 cpuset_t *cpus; 202 }; 203 #define VM_ACTIVE_CPUS 0 204 #define VM_SUSPENDED_CPUS 1 205 206 struct vm_intinfo { 207 int vcpuid; 208 uint64_t info1; 209 uint64_t info2; 210 }; 211 212 struct vm_rtc_time { 213 time_t secs; 214 }; 215 216 struct vm_rtc_data { 217 int offset; 218 uint8_t value; 219 }; 220 221 enum { 222 /* general routines */ 223 IOCNUM_ABIVERS = 0, 224 IOCNUM_RUN = 1, 225 IOCNUM_SET_CAPABILITY = 2, 226 IOCNUM_GET_CAPABILITY = 3, 227 IOCNUM_SUSPEND = 4, 228 IOCNUM_REINIT = 5, 229 230 /* memory apis */ 231 IOCNUM_MAP_MEMORY = 10, /* deprecated */ 232 IOCNUM_GET_MEMORY_SEG = 11, /* deprecated */ 233 IOCNUM_GET_GPA_PMAP = 12, 234 IOCNUM_GLA2GPA = 13, 235 IOCNUM_ALLOC_MEMSEG = 14, 236 IOCNUM_GET_MEMSEG = 15, 237 IOCNUM_MMAP_MEMSEG = 16, 238 IOCNUM_MMAP_GETNEXT = 17, 239 240 /* register/state accessors */ 241 IOCNUM_SET_REGISTER = 20, 242 IOCNUM_GET_REGISTER = 21, 243 IOCNUM_SET_SEGMENT_DESCRIPTOR = 22, 244 IOCNUM_GET_SEGMENT_DESCRIPTOR = 23, 245 246 /* interrupt injection */ 247 IOCNUM_GET_INTINFO = 28, 248 IOCNUM_SET_INTINFO = 29, 249 IOCNUM_INJECT_EXCEPTION = 30, 250 IOCNUM_LAPIC_IRQ = 31, 251 IOCNUM_INJECT_NMI = 32, 252 IOCNUM_IOAPIC_ASSERT_IRQ = 33, 253 IOCNUM_IOAPIC_DEASSERT_IRQ = 34, 254 IOCNUM_IOAPIC_PULSE_IRQ = 35, 255 IOCNUM_LAPIC_MSI = 36, 256 IOCNUM_LAPIC_LOCAL_IRQ = 37, 257 IOCNUM_IOAPIC_PINCOUNT = 38, 258 IOCNUM_RESTART_INSTRUCTION = 39, 259 260 /* PCI pass-thru */ 261 IOCNUM_BIND_PPTDEV = 40, 262 IOCNUM_UNBIND_PPTDEV = 41, 263 IOCNUM_MAP_PPTDEV_MMIO = 42, 264 IOCNUM_PPTDEV_MSI = 43, 265 IOCNUM_PPTDEV_MSIX = 44, 266 267 /* statistics */ 268 IOCNUM_VM_STATS = 50, 269 IOCNUM_VM_STAT_DESC = 51, 270 271 /* kernel device state */ 272 IOCNUM_SET_X2APIC_STATE = 60, 273 IOCNUM_GET_X2APIC_STATE = 61, 274 IOCNUM_GET_HPET_CAPABILITIES = 62, 275 276 /* legacy interrupt injection */ 277 IOCNUM_ISA_ASSERT_IRQ = 80, 278 IOCNUM_ISA_DEASSERT_IRQ = 81, 279 IOCNUM_ISA_PULSE_IRQ = 82, 280 IOCNUM_ISA_SET_IRQ_TRIGGER = 83, 281 282 /* vm_cpuset */ 283 IOCNUM_ACTIVATE_CPU = 90, 284 IOCNUM_GET_CPUSET = 91, 285 286 /* RTC */ 287 IOCNUM_RTC_READ = 100, 288 IOCNUM_RTC_WRITE = 101, 289 IOCNUM_RTC_SETTIME = 102, 290 IOCNUM_RTC_GETTIME = 103, 291 }; 292 293 #define VM_RUN \ 294 _IOWR('v', IOCNUM_RUN, struct vm_run) 295 #define VM_SUSPEND \ 296 _IOW('v', IOCNUM_SUSPEND, struct vm_suspend) 297 #define VM_REINIT \ 298 _IO('v', IOCNUM_REINIT) 299 #define VM_ALLOC_MEMSEG \ 300 _IOW('v', IOCNUM_ALLOC_MEMSEG, struct vm_memseg) 301 #define VM_GET_MEMSEG \ 302 _IOWR('v', IOCNUM_GET_MEMSEG, struct vm_memseg) 303 #define VM_MMAP_MEMSEG \ 304 _IOW('v', IOCNUM_MMAP_MEMSEG, struct vm_memmap) 305 #define VM_MMAP_GETNEXT \ 306 _IOWR('v', IOCNUM_MMAP_GETNEXT, struct vm_memmap) 307 #define VM_SET_REGISTER \ 308 _IOW('v', IOCNUM_SET_REGISTER, struct vm_register) 309 #define VM_GET_REGISTER \ 310 _IOWR('v', IOCNUM_GET_REGISTER, struct vm_register) 311 #define VM_SET_SEGMENT_DESCRIPTOR \ 312 _IOW('v', IOCNUM_SET_SEGMENT_DESCRIPTOR, struct vm_seg_desc) 313 #define VM_GET_SEGMENT_DESCRIPTOR \ 314 _IOWR('v', IOCNUM_GET_SEGMENT_DESCRIPTOR, struct vm_seg_desc) 315 #define VM_INJECT_EXCEPTION \ 316 _IOW('v', IOCNUM_INJECT_EXCEPTION, struct vm_exception) 317 #define VM_LAPIC_IRQ \ 318 _IOW('v', IOCNUM_LAPIC_IRQ, struct vm_lapic_irq) 319 #define VM_LAPIC_LOCAL_IRQ \ 320 _IOW('v', IOCNUM_LAPIC_LOCAL_IRQ, struct vm_lapic_irq) 321 #define VM_LAPIC_MSI \ 322 _IOW('v', IOCNUM_LAPIC_MSI, struct vm_lapic_msi) 323 #define VM_IOAPIC_ASSERT_IRQ \ 324 _IOW('v', IOCNUM_IOAPIC_ASSERT_IRQ, struct vm_ioapic_irq) 325 #define VM_IOAPIC_DEASSERT_IRQ \ 326 _IOW('v', IOCNUM_IOAPIC_DEASSERT_IRQ, struct vm_ioapic_irq) 327 #define VM_IOAPIC_PULSE_IRQ \ 328 _IOW('v', IOCNUM_IOAPIC_PULSE_IRQ, struct vm_ioapic_irq) 329 #define VM_IOAPIC_PINCOUNT \ 330 _IOR('v', IOCNUM_IOAPIC_PINCOUNT, int) 331 #define VM_ISA_ASSERT_IRQ \ 332 _IOW('v', IOCNUM_ISA_ASSERT_IRQ, struct vm_isa_irq) 333 #define VM_ISA_DEASSERT_IRQ \ 334 _IOW('v', IOCNUM_ISA_DEASSERT_IRQ, struct vm_isa_irq) 335 #define VM_ISA_PULSE_IRQ \ 336 _IOW('v', IOCNUM_ISA_PULSE_IRQ, struct vm_isa_irq) 337 #define VM_ISA_SET_IRQ_TRIGGER \ 338 _IOW('v', IOCNUM_ISA_SET_IRQ_TRIGGER, struct vm_isa_irq_trigger) 339 #define VM_SET_CAPABILITY \ 340 _IOW('v', IOCNUM_SET_CAPABILITY, struct vm_capability) 341 #define VM_GET_CAPABILITY \ 342 _IOWR('v', IOCNUM_GET_CAPABILITY, struct vm_capability) 343 #define VM_BIND_PPTDEV \ 344 _IOW('v', IOCNUM_BIND_PPTDEV, struct vm_pptdev) 345 #define VM_UNBIND_PPTDEV \ 346 _IOW('v', IOCNUM_UNBIND_PPTDEV, struct vm_pptdev) 347 #define VM_MAP_PPTDEV_MMIO \ 348 _IOW('v', IOCNUM_MAP_PPTDEV_MMIO, struct vm_pptdev_mmio) 349 #define VM_PPTDEV_MSI \ 350 _IOW('v', IOCNUM_PPTDEV_MSI, struct vm_pptdev_msi) 351 #define VM_PPTDEV_MSIX \ 352 _IOW('v', IOCNUM_PPTDEV_MSIX, struct vm_pptdev_msix) 353 #define VM_INJECT_NMI \ 354 _IOW('v', IOCNUM_INJECT_NMI, struct vm_nmi) 355 #define VM_STATS \ 356 _IOWR('v', IOCNUM_VM_STATS, struct vm_stats) 357 #define VM_STAT_DESC \ 358 _IOWR('v', IOCNUM_VM_STAT_DESC, struct vm_stat_desc) 359 #define VM_SET_X2APIC_STATE \ 360 _IOW('v', IOCNUM_SET_X2APIC_STATE, struct vm_x2apic) 361 #define VM_GET_X2APIC_STATE \ 362 _IOWR('v', IOCNUM_GET_X2APIC_STATE, struct vm_x2apic) 363 #define VM_GET_HPET_CAPABILITIES \ 364 _IOR('v', IOCNUM_GET_HPET_CAPABILITIES, struct vm_hpet_cap) 365 #define VM_GET_GPA_PMAP \ 366 _IOWR('v', IOCNUM_GET_GPA_PMAP, struct vm_gpa_pte) 367 #define VM_GLA2GPA \ 368 _IOWR('v', IOCNUM_GLA2GPA, struct vm_gla2gpa) 369 #define VM_ACTIVATE_CPU \ 370 _IOW('v', IOCNUM_ACTIVATE_CPU, struct vm_activate_cpu) 371 #define VM_GET_CPUS \ 372 _IOW('v', IOCNUM_GET_CPUSET, struct vm_cpuset) 373 #define VM_SET_INTINFO \ 374 _IOW('v', IOCNUM_SET_INTINFO, struct vm_intinfo) 375 #define VM_GET_INTINFO \ 376 _IOWR('v', IOCNUM_GET_INTINFO, struct vm_intinfo) 377 #define VM_RTC_WRITE \ 378 _IOW('v', IOCNUM_RTC_WRITE, struct vm_rtc_data) 379 #define VM_RTC_READ \ 380 _IOWR('v', IOCNUM_RTC_READ, struct vm_rtc_data) 381 #define VM_RTC_SETTIME \ 382 _IOW('v', IOCNUM_RTC_SETTIME, struct vm_rtc_time) 383 #define VM_RTC_GETTIME \ 384 _IOR('v', IOCNUM_RTC_GETTIME, struct vm_rtc_time) 385 #define VM_RESTART_INSTRUCTION \ 386 _IOW('v', IOCNUM_RESTART_INSTRUCTION, int) 387 #endif 388