1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011 NetApp, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _VMM_DEV_H_ 30 #define _VMM_DEV_H_ 31 32 struct vm_snapshot_meta; 33 34 struct vm_memmap { 35 vm_paddr_t gpa; 36 int segid; /* memory segment */ 37 vm_ooffset_t segoff; /* offset into memory segment */ 38 size_t len; /* mmap length */ 39 int prot; /* RWX */ 40 int flags; 41 }; 42 #define VM_MEMMAP_F_WIRED 0x01 43 #define VM_MEMMAP_F_IOMMU 0x02 44 45 struct vm_munmap { 46 vm_paddr_t gpa; 47 size_t len; 48 }; 49 50 #define VM_MEMSEG_NAME(m) ((m)->name[0] != '\0' ? (m)->name : NULL) 51 struct vm_memseg { 52 int segid; 53 size_t len; 54 char name[VM_MAX_SUFFIXLEN + 1]; 55 }; 56 57 struct vm_register { 58 int cpuid; 59 int regnum; /* enum vm_reg_name */ 60 uint64_t regval; 61 }; 62 63 struct vm_seg_desc { /* data or code segment */ 64 int cpuid; 65 int regnum; /* enum vm_reg_name */ 66 struct seg_desc desc; 67 }; 68 69 struct vm_register_set { 70 int cpuid; 71 unsigned int count; 72 const int *regnums; /* enum vm_reg_name */ 73 uint64_t *regvals; 74 }; 75 76 struct vm_run { 77 int cpuid; 78 cpuset_t *cpuset; /* CPU set storage */ 79 size_t cpusetsize; 80 struct vm_exit *vm_exit; 81 }; 82 83 struct vm_exception { 84 int cpuid; 85 int vector; 86 uint32_t error_code; 87 int error_code_valid; 88 int restart_instruction; 89 }; 90 91 struct vm_lapic_msi { 92 uint64_t msg; 93 uint64_t addr; 94 }; 95 96 struct vm_lapic_irq { 97 int cpuid; 98 int vector; 99 }; 100 101 struct vm_ioapic_irq { 102 int irq; 103 }; 104 105 struct vm_isa_irq { 106 int atpic_irq; 107 int ioapic_irq; 108 }; 109 110 struct vm_isa_irq_trigger { 111 int atpic_irq; 112 enum vm_intr_trigger trigger; 113 }; 114 115 struct vm_capability { 116 int cpuid; 117 enum vm_cap_type captype; 118 int capval; 119 int allcpus; 120 }; 121 122 struct vm_pptdev { 123 int bus; 124 int slot; 125 int func; 126 }; 127 128 struct vm_pptdev_mmio { 129 int bus; 130 int slot; 131 int func; 132 vm_paddr_t gpa; 133 vm_paddr_t hpa; 134 size_t len; 135 }; 136 137 struct vm_pptdev_msi { 138 int vcpu; /* unused */ 139 int bus; 140 int slot; 141 int func; 142 int numvec; /* 0 means disabled */ 143 uint64_t msg; 144 uint64_t addr; 145 }; 146 147 struct vm_pptdev_msix { 148 int vcpu; /* unused */ 149 int bus; 150 int slot; 151 int func; 152 int idx; 153 uint64_t msg; 154 uint32_t vector_control; 155 uint64_t addr; 156 }; 157 158 struct vm_nmi { 159 int cpuid; 160 }; 161 162 #define MAX_VM_STATS 64 163 struct vm_stats { 164 int cpuid; /* in */ 165 int index; /* in */ 166 int num_entries; /* out */ 167 struct timeval tv; 168 uint64_t statbuf[MAX_VM_STATS]; 169 }; 170 171 struct vm_stat_desc { 172 int index; /* in */ 173 char desc[128]; /* out */ 174 }; 175 176 struct vm_x2apic { 177 int cpuid; 178 enum x2apic_state state; 179 }; 180 181 struct vm_gpa_pte { 182 uint64_t gpa; /* in */ 183 uint64_t pte[4]; /* out */ 184 int ptenum; 185 }; 186 187 struct vm_hpet_cap { 188 uint32_t capabilities; /* lower 32 bits of HPET capabilities */ 189 }; 190 191 struct vm_suspend { 192 enum vm_suspend_how how; 193 }; 194 195 struct vm_gla2gpa { 196 int vcpuid; /* inputs */ 197 int prot; /* PROT_READ or PROT_WRITE */ 198 uint64_t gla; 199 struct vm_guest_paging paging; 200 int fault; /* outputs */ 201 uint64_t gpa; 202 }; 203 204 struct vm_activate_cpu { 205 int vcpuid; 206 }; 207 208 struct vm_cpuset { 209 int which; 210 int cpusetsize; 211 cpuset_t *cpus; 212 }; 213 #define VM_ACTIVE_CPUS 0 214 #define VM_SUSPENDED_CPUS 1 215 #define VM_DEBUG_CPUS 2 216 217 struct vm_intinfo { 218 int vcpuid; 219 uint64_t info1; 220 uint64_t info2; 221 }; 222 223 struct vm_rtc_time { 224 time_t secs; 225 }; 226 227 struct vm_rtc_data { 228 int offset; 229 uint8_t value; 230 }; 231 232 struct vm_cpu_topology { 233 uint16_t sockets; 234 uint16_t cores; 235 uint16_t threads; 236 uint16_t maxcpus; 237 }; 238 239 struct vm_readwrite_kernemu_device { 240 int vcpuid; 241 unsigned access_width : 3; 242 unsigned _unused : 29; 243 uint64_t gpa; 244 uint64_t value; 245 }; 246 _Static_assert(sizeof(struct vm_readwrite_kernemu_device) == 24, "ABI"); 247 248 enum { 249 /* general routines */ 250 IOCNUM_ABIVERS = 0, 251 IOCNUM_RUN = 1, 252 IOCNUM_SET_CAPABILITY = 2, 253 IOCNUM_GET_CAPABILITY = 3, 254 IOCNUM_SUSPEND = 4, 255 IOCNUM_REINIT = 5, 256 257 /* memory apis */ 258 IOCNUM_MAP_MEMORY = 10, /* deprecated */ 259 IOCNUM_GET_MEMORY_SEG = 11, /* deprecated */ 260 IOCNUM_GET_GPA_PMAP = 12, 261 IOCNUM_GLA2GPA = 13, 262 IOCNUM_ALLOC_MEMSEG = 14, 263 IOCNUM_GET_MEMSEG = 15, 264 IOCNUM_MMAP_MEMSEG = 16, 265 IOCNUM_MMAP_GETNEXT = 17, 266 IOCNUM_GLA2GPA_NOFAULT = 18, 267 IOCNUM_MUNMAP_MEMSEG = 19, 268 269 /* register/state accessors */ 270 IOCNUM_SET_REGISTER = 20, 271 IOCNUM_GET_REGISTER = 21, 272 IOCNUM_SET_SEGMENT_DESCRIPTOR = 22, 273 IOCNUM_GET_SEGMENT_DESCRIPTOR = 23, 274 IOCNUM_SET_REGISTER_SET = 24, 275 IOCNUM_GET_REGISTER_SET = 25, 276 IOCNUM_GET_KERNEMU_DEV = 26, 277 IOCNUM_SET_KERNEMU_DEV = 27, 278 279 /* interrupt injection */ 280 IOCNUM_GET_INTINFO = 28, 281 IOCNUM_SET_INTINFO = 29, 282 IOCNUM_INJECT_EXCEPTION = 30, 283 IOCNUM_LAPIC_IRQ = 31, 284 IOCNUM_INJECT_NMI = 32, 285 IOCNUM_IOAPIC_ASSERT_IRQ = 33, 286 IOCNUM_IOAPIC_DEASSERT_IRQ = 34, 287 IOCNUM_IOAPIC_PULSE_IRQ = 35, 288 IOCNUM_LAPIC_MSI = 36, 289 IOCNUM_LAPIC_LOCAL_IRQ = 37, 290 IOCNUM_IOAPIC_PINCOUNT = 38, 291 IOCNUM_RESTART_INSTRUCTION = 39, 292 293 /* PCI pass-thru */ 294 IOCNUM_BIND_PPTDEV = 40, 295 IOCNUM_UNBIND_PPTDEV = 41, 296 IOCNUM_MAP_PPTDEV_MMIO = 42, 297 IOCNUM_PPTDEV_MSI = 43, 298 IOCNUM_PPTDEV_MSIX = 44, 299 IOCNUM_PPTDEV_DISABLE_MSIX = 45, 300 IOCNUM_UNMAP_PPTDEV_MMIO = 46, 301 302 /* statistics */ 303 IOCNUM_VM_STATS = 50, 304 IOCNUM_VM_STAT_DESC = 51, 305 306 /* kernel device state */ 307 IOCNUM_SET_X2APIC_STATE = 60, 308 IOCNUM_GET_X2APIC_STATE = 61, 309 IOCNUM_GET_HPET_CAPABILITIES = 62, 310 311 /* CPU Topology */ 312 IOCNUM_SET_TOPOLOGY = 63, 313 IOCNUM_GET_TOPOLOGY = 64, 314 315 /* legacy interrupt injection */ 316 IOCNUM_ISA_ASSERT_IRQ = 80, 317 IOCNUM_ISA_DEASSERT_IRQ = 81, 318 IOCNUM_ISA_PULSE_IRQ = 82, 319 IOCNUM_ISA_SET_IRQ_TRIGGER = 83, 320 321 /* vm_cpuset */ 322 IOCNUM_ACTIVATE_CPU = 90, 323 IOCNUM_GET_CPUSET = 91, 324 IOCNUM_SUSPEND_CPU = 92, 325 IOCNUM_RESUME_CPU = 93, 326 327 /* RTC */ 328 IOCNUM_RTC_READ = 100, 329 IOCNUM_RTC_WRITE = 101, 330 IOCNUM_RTC_SETTIME = 102, 331 IOCNUM_RTC_GETTIME = 103, 332 333 /* checkpoint */ 334 IOCNUM_SNAPSHOT_REQ = 113, 335 336 IOCNUM_RESTORE_TIME = 115 337 }; 338 339 #define VM_RUN \ 340 _IOW('v', IOCNUM_RUN, struct vm_run) 341 #define VM_SUSPEND \ 342 _IOW('v', IOCNUM_SUSPEND, struct vm_suspend) 343 #define VM_REINIT \ 344 _IO('v', IOCNUM_REINIT) 345 #define VM_ALLOC_MEMSEG \ 346 _IOW('v', IOCNUM_ALLOC_MEMSEG, struct vm_memseg) 347 #define VM_GET_MEMSEG \ 348 _IOWR('v', IOCNUM_GET_MEMSEG, struct vm_memseg) 349 #define VM_MMAP_MEMSEG \ 350 _IOW('v', IOCNUM_MMAP_MEMSEG, struct vm_memmap) 351 #define VM_MMAP_GETNEXT \ 352 _IOWR('v', IOCNUM_MMAP_GETNEXT, struct vm_memmap) 353 #define VM_MUNMAP_MEMSEG \ 354 _IOW('v', IOCNUM_MUNMAP_MEMSEG, struct vm_munmap) 355 #define VM_SET_REGISTER \ 356 _IOW('v', IOCNUM_SET_REGISTER, struct vm_register) 357 #define VM_GET_REGISTER \ 358 _IOWR('v', IOCNUM_GET_REGISTER, struct vm_register) 359 #define VM_SET_SEGMENT_DESCRIPTOR \ 360 _IOW('v', IOCNUM_SET_SEGMENT_DESCRIPTOR, struct vm_seg_desc) 361 #define VM_GET_SEGMENT_DESCRIPTOR \ 362 _IOWR('v', IOCNUM_GET_SEGMENT_DESCRIPTOR, struct vm_seg_desc) 363 #define VM_SET_REGISTER_SET \ 364 _IOW('v', IOCNUM_SET_REGISTER_SET, struct vm_register_set) 365 #define VM_GET_REGISTER_SET \ 366 _IOWR('v', IOCNUM_GET_REGISTER_SET, struct vm_register_set) 367 #define VM_SET_KERNEMU_DEV \ 368 _IOW('v', IOCNUM_SET_KERNEMU_DEV, \ 369 struct vm_readwrite_kernemu_device) 370 #define VM_GET_KERNEMU_DEV \ 371 _IOWR('v', IOCNUM_GET_KERNEMU_DEV, \ 372 struct vm_readwrite_kernemu_device) 373 #define VM_INJECT_EXCEPTION \ 374 _IOW('v', IOCNUM_INJECT_EXCEPTION, struct vm_exception) 375 #define VM_LAPIC_IRQ \ 376 _IOW('v', IOCNUM_LAPIC_IRQ, struct vm_lapic_irq) 377 #define VM_LAPIC_LOCAL_IRQ \ 378 _IOW('v', IOCNUM_LAPIC_LOCAL_IRQ, struct vm_lapic_irq) 379 #define VM_LAPIC_MSI \ 380 _IOW('v', IOCNUM_LAPIC_MSI, struct vm_lapic_msi) 381 #define VM_IOAPIC_ASSERT_IRQ \ 382 _IOW('v', IOCNUM_IOAPIC_ASSERT_IRQ, struct vm_ioapic_irq) 383 #define VM_IOAPIC_DEASSERT_IRQ \ 384 _IOW('v', IOCNUM_IOAPIC_DEASSERT_IRQ, struct vm_ioapic_irq) 385 #define VM_IOAPIC_PULSE_IRQ \ 386 _IOW('v', IOCNUM_IOAPIC_PULSE_IRQ, struct vm_ioapic_irq) 387 #define VM_IOAPIC_PINCOUNT \ 388 _IOR('v', IOCNUM_IOAPIC_PINCOUNT, int) 389 #define VM_ISA_ASSERT_IRQ \ 390 _IOW('v', IOCNUM_ISA_ASSERT_IRQ, struct vm_isa_irq) 391 #define VM_ISA_DEASSERT_IRQ \ 392 _IOW('v', IOCNUM_ISA_DEASSERT_IRQ, struct vm_isa_irq) 393 #define VM_ISA_PULSE_IRQ \ 394 _IOW('v', IOCNUM_ISA_PULSE_IRQ, struct vm_isa_irq) 395 #define VM_ISA_SET_IRQ_TRIGGER \ 396 _IOW('v', IOCNUM_ISA_SET_IRQ_TRIGGER, struct vm_isa_irq_trigger) 397 #define VM_SET_CAPABILITY \ 398 _IOW('v', IOCNUM_SET_CAPABILITY, struct vm_capability) 399 #define VM_GET_CAPABILITY \ 400 _IOWR('v', IOCNUM_GET_CAPABILITY, struct vm_capability) 401 #define VM_BIND_PPTDEV \ 402 _IOW('v', IOCNUM_BIND_PPTDEV, struct vm_pptdev) 403 #define VM_UNBIND_PPTDEV \ 404 _IOW('v', IOCNUM_UNBIND_PPTDEV, struct vm_pptdev) 405 #define VM_MAP_PPTDEV_MMIO \ 406 _IOW('v', IOCNUM_MAP_PPTDEV_MMIO, struct vm_pptdev_mmio) 407 #define VM_PPTDEV_MSI \ 408 _IOW('v', IOCNUM_PPTDEV_MSI, struct vm_pptdev_msi) 409 #define VM_PPTDEV_MSIX \ 410 _IOW('v', IOCNUM_PPTDEV_MSIX, struct vm_pptdev_msix) 411 #define VM_PPTDEV_DISABLE_MSIX \ 412 _IOW('v', IOCNUM_PPTDEV_DISABLE_MSIX, struct vm_pptdev) 413 #define VM_UNMAP_PPTDEV_MMIO \ 414 _IOW('v', IOCNUM_UNMAP_PPTDEV_MMIO, struct vm_pptdev_mmio) 415 #define VM_INJECT_NMI \ 416 _IOW('v', IOCNUM_INJECT_NMI, struct vm_nmi) 417 #define VM_STATS \ 418 _IOWR('v', IOCNUM_VM_STATS, struct vm_stats) 419 #define VM_STAT_DESC \ 420 _IOWR('v', IOCNUM_VM_STAT_DESC, struct vm_stat_desc) 421 #define VM_SET_X2APIC_STATE \ 422 _IOW('v', IOCNUM_SET_X2APIC_STATE, struct vm_x2apic) 423 #define VM_GET_X2APIC_STATE \ 424 _IOWR('v', IOCNUM_GET_X2APIC_STATE, struct vm_x2apic) 425 #define VM_GET_HPET_CAPABILITIES \ 426 _IOR('v', IOCNUM_GET_HPET_CAPABILITIES, struct vm_hpet_cap) 427 #define VM_SET_TOPOLOGY \ 428 _IOW('v', IOCNUM_SET_TOPOLOGY, struct vm_cpu_topology) 429 #define VM_GET_TOPOLOGY \ 430 _IOR('v', IOCNUM_GET_TOPOLOGY, struct vm_cpu_topology) 431 #define VM_GET_GPA_PMAP \ 432 _IOWR('v', IOCNUM_GET_GPA_PMAP, struct vm_gpa_pte) 433 #define VM_GLA2GPA \ 434 _IOWR('v', IOCNUM_GLA2GPA, struct vm_gla2gpa) 435 #define VM_GLA2GPA_NOFAULT \ 436 _IOWR('v', IOCNUM_GLA2GPA_NOFAULT, struct vm_gla2gpa) 437 #define VM_ACTIVATE_CPU \ 438 _IOW('v', IOCNUM_ACTIVATE_CPU, struct vm_activate_cpu) 439 #define VM_GET_CPUS \ 440 _IOW('v', IOCNUM_GET_CPUSET, struct vm_cpuset) 441 #define VM_SUSPEND_CPU \ 442 _IOW('v', IOCNUM_SUSPEND_CPU, struct vm_activate_cpu) 443 #define VM_RESUME_CPU \ 444 _IOW('v', IOCNUM_RESUME_CPU, struct vm_activate_cpu) 445 #define VM_SET_INTINFO \ 446 _IOW('v', IOCNUM_SET_INTINFO, struct vm_intinfo) 447 #define VM_GET_INTINFO \ 448 _IOWR('v', IOCNUM_GET_INTINFO, struct vm_intinfo) 449 #define VM_RTC_WRITE \ 450 _IOW('v', IOCNUM_RTC_WRITE, struct vm_rtc_data) 451 #define VM_RTC_READ \ 452 _IOWR('v', IOCNUM_RTC_READ, struct vm_rtc_data) 453 #define VM_RTC_SETTIME \ 454 _IOW('v', IOCNUM_RTC_SETTIME, struct vm_rtc_time) 455 #define VM_RTC_GETTIME \ 456 _IOR('v', IOCNUM_RTC_GETTIME, struct vm_rtc_time) 457 #define VM_RESTART_INSTRUCTION \ 458 _IOW('v', IOCNUM_RESTART_INSTRUCTION, int) 459 #define VM_SNAPSHOT_REQ \ 460 _IOWR('v', IOCNUM_SNAPSHOT_REQ, struct vm_snapshot_meta) 461 #define VM_RESTORE_TIME \ 462 _IOWR('v', IOCNUM_RESTORE_TIME, int) 463 #endif 464