1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011 NetApp, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #ifndef _VMM_DEV_H_ 32 #define _VMM_DEV_H_ 33 34 struct vm_snapshot_meta; 35 36 #ifdef _KERNEL 37 void vmmdev_init(void); 38 int vmmdev_cleanup(void); 39 #endif 40 41 struct vm_memmap { 42 vm_paddr_t gpa; 43 int segid; /* memory segment */ 44 vm_ooffset_t segoff; /* offset into memory segment */ 45 size_t len; /* mmap length */ 46 int prot; /* RWX */ 47 int flags; 48 }; 49 #define VM_MEMMAP_F_WIRED 0x01 50 #define VM_MEMMAP_F_IOMMU 0x02 51 52 struct vm_munmap { 53 vm_paddr_t gpa; 54 size_t len; 55 }; 56 57 #define VM_MEMSEG_NAME(m) ((m)->name[0] != '\0' ? (m)->name : NULL) 58 struct vm_memseg { 59 int segid; 60 size_t len; 61 char name[VM_MAX_SUFFIXLEN + 1]; 62 }; 63 64 struct vm_memseg_fbsd12 { 65 int segid; 66 size_t len; 67 char name[64]; 68 }; 69 _Static_assert(sizeof(struct vm_memseg_fbsd12) == 80, "COMPAT_FREEBSD12 ABI"); 70 71 struct vm_register { 72 int cpuid; 73 int regnum; /* enum vm_reg_name */ 74 uint64_t regval; 75 }; 76 77 struct vm_seg_desc { /* data or code segment */ 78 int cpuid; 79 int regnum; /* enum vm_reg_name */ 80 struct seg_desc desc; 81 }; 82 83 struct vm_register_set { 84 int cpuid; 85 unsigned int count; 86 const int *regnums; /* enum vm_reg_name */ 87 uint64_t *regvals; 88 }; 89 90 struct vm_run { 91 int cpuid; 92 cpuset_t *cpuset; /* CPU set storage */ 93 size_t cpusetsize; 94 struct vm_exit *vm_exit; 95 }; 96 97 struct vm_exception { 98 int cpuid; 99 int vector; 100 uint32_t error_code; 101 int error_code_valid; 102 int restart_instruction; 103 }; 104 105 struct vm_lapic_msi { 106 uint64_t msg; 107 uint64_t addr; 108 }; 109 110 struct vm_lapic_irq { 111 int cpuid; 112 int vector; 113 }; 114 115 struct vm_ioapic_irq { 116 int irq; 117 }; 118 119 struct vm_isa_irq { 120 int atpic_irq; 121 int ioapic_irq; 122 }; 123 124 struct vm_isa_irq_trigger { 125 int atpic_irq; 126 enum vm_intr_trigger trigger; 127 }; 128 129 struct vm_capability { 130 int cpuid; 131 enum vm_cap_type captype; 132 int capval; 133 int allcpus; 134 }; 135 136 struct vm_pptdev { 137 int bus; 138 int slot; 139 int func; 140 }; 141 142 struct vm_pptdev_mmio { 143 int bus; 144 int slot; 145 int func; 146 vm_paddr_t gpa; 147 vm_paddr_t hpa; 148 size_t len; 149 }; 150 151 struct vm_pptdev_msi { 152 int vcpu; /* unused */ 153 int bus; 154 int slot; 155 int func; 156 int numvec; /* 0 means disabled */ 157 uint64_t msg; 158 uint64_t addr; 159 }; 160 161 struct vm_pptdev_msix { 162 int vcpu; /* unused */ 163 int bus; 164 int slot; 165 int func; 166 int idx; 167 uint64_t msg; 168 uint32_t vector_control; 169 uint64_t addr; 170 }; 171 172 struct vm_nmi { 173 int cpuid; 174 }; 175 176 #define MAX_VM_STATS 64 177 struct vm_stats { 178 int cpuid; /* in */ 179 int index; /* in */ 180 int num_entries; /* out */ 181 struct timeval tv; 182 uint64_t statbuf[MAX_VM_STATS]; 183 }; 184 185 struct vm_stat_desc { 186 int index; /* in */ 187 char desc[128]; /* out */ 188 }; 189 190 struct vm_x2apic { 191 int cpuid; 192 enum x2apic_state state; 193 }; 194 195 struct vm_gpa_pte { 196 uint64_t gpa; /* in */ 197 uint64_t pte[4]; /* out */ 198 int ptenum; 199 }; 200 201 struct vm_hpet_cap { 202 uint32_t capabilities; /* lower 32 bits of HPET capabilities */ 203 }; 204 205 struct vm_suspend { 206 enum vm_suspend_how how; 207 }; 208 209 struct vm_gla2gpa { 210 int vcpuid; /* inputs */ 211 int prot; /* PROT_READ or PROT_WRITE */ 212 uint64_t gla; 213 struct vm_guest_paging paging; 214 int fault; /* outputs */ 215 uint64_t gpa; 216 }; 217 218 struct vm_activate_cpu { 219 int vcpuid; 220 }; 221 222 struct vm_cpuset { 223 int which; 224 int cpusetsize; 225 cpuset_t *cpus; 226 }; 227 #define VM_ACTIVE_CPUS 0 228 #define VM_SUSPENDED_CPUS 1 229 #define VM_DEBUG_CPUS 2 230 231 struct vm_intinfo { 232 int vcpuid; 233 uint64_t info1; 234 uint64_t info2; 235 }; 236 237 struct vm_rtc_time { 238 time_t secs; 239 }; 240 241 struct vm_rtc_data { 242 int offset; 243 uint8_t value; 244 }; 245 246 struct vm_cpu_topology { 247 uint16_t sockets; 248 uint16_t cores; 249 uint16_t threads; 250 uint16_t maxcpus; 251 }; 252 253 struct vm_readwrite_kernemu_device { 254 int vcpuid; 255 unsigned access_width : 3; 256 unsigned _unused : 29; 257 uint64_t gpa; 258 uint64_t value; 259 }; 260 _Static_assert(sizeof(struct vm_readwrite_kernemu_device) == 24, "ABI"); 261 262 enum { 263 /* general routines */ 264 IOCNUM_ABIVERS = 0, 265 IOCNUM_RUN = 1, 266 IOCNUM_SET_CAPABILITY = 2, 267 IOCNUM_GET_CAPABILITY = 3, 268 IOCNUM_SUSPEND = 4, 269 IOCNUM_REINIT = 5, 270 271 /* memory apis */ 272 IOCNUM_MAP_MEMORY = 10, /* deprecated */ 273 IOCNUM_GET_MEMORY_SEG = 11, /* deprecated */ 274 IOCNUM_GET_GPA_PMAP = 12, 275 IOCNUM_GLA2GPA = 13, 276 IOCNUM_ALLOC_MEMSEG = 14, 277 IOCNUM_GET_MEMSEG = 15, 278 IOCNUM_MMAP_MEMSEG = 16, 279 IOCNUM_MMAP_GETNEXT = 17, 280 IOCNUM_GLA2GPA_NOFAULT = 18, 281 IOCNUM_MUNMAP_MEMSEG = 19, 282 283 /* register/state accessors */ 284 IOCNUM_SET_REGISTER = 20, 285 IOCNUM_GET_REGISTER = 21, 286 IOCNUM_SET_SEGMENT_DESCRIPTOR = 22, 287 IOCNUM_GET_SEGMENT_DESCRIPTOR = 23, 288 IOCNUM_SET_REGISTER_SET = 24, 289 IOCNUM_GET_REGISTER_SET = 25, 290 IOCNUM_GET_KERNEMU_DEV = 26, 291 IOCNUM_SET_KERNEMU_DEV = 27, 292 293 /* interrupt injection */ 294 IOCNUM_GET_INTINFO = 28, 295 IOCNUM_SET_INTINFO = 29, 296 IOCNUM_INJECT_EXCEPTION = 30, 297 IOCNUM_LAPIC_IRQ = 31, 298 IOCNUM_INJECT_NMI = 32, 299 IOCNUM_IOAPIC_ASSERT_IRQ = 33, 300 IOCNUM_IOAPIC_DEASSERT_IRQ = 34, 301 IOCNUM_IOAPIC_PULSE_IRQ = 35, 302 IOCNUM_LAPIC_MSI = 36, 303 IOCNUM_LAPIC_LOCAL_IRQ = 37, 304 IOCNUM_IOAPIC_PINCOUNT = 38, 305 IOCNUM_RESTART_INSTRUCTION = 39, 306 307 /* PCI pass-thru */ 308 IOCNUM_BIND_PPTDEV = 40, 309 IOCNUM_UNBIND_PPTDEV = 41, 310 IOCNUM_MAP_PPTDEV_MMIO = 42, 311 IOCNUM_PPTDEV_MSI = 43, 312 IOCNUM_PPTDEV_MSIX = 44, 313 IOCNUM_PPTDEV_DISABLE_MSIX = 45, 314 IOCNUM_UNMAP_PPTDEV_MMIO = 46, 315 316 /* statistics */ 317 IOCNUM_VM_STATS = 50, 318 IOCNUM_VM_STAT_DESC = 51, 319 320 /* kernel device state */ 321 IOCNUM_SET_X2APIC_STATE = 60, 322 IOCNUM_GET_X2APIC_STATE = 61, 323 IOCNUM_GET_HPET_CAPABILITIES = 62, 324 325 /* CPU Topology */ 326 IOCNUM_SET_TOPOLOGY = 63, 327 IOCNUM_GET_TOPOLOGY = 64, 328 329 /* legacy interrupt injection */ 330 IOCNUM_ISA_ASSERT_IRQ = 80, 331 IOCNUM_ISA_DEASSERT_IRQ = 81, 332 IOCNUM_ISA_PULSE_IRQ = 82, 333 IOCNUM_ISA_SET_IRQ_TRIGGER = 83, 334 335 /* vm_cpuset */ 336 IOCNUM_ACTIVATE_CPU = 90, 337 IOCNUM_GET_CPUSET = 91, 338 IOCNUM_SUSPEND_CPU = 92, 339 IOCNUM_RESUME_CPU = 93, 340 341 /* RTC */ 342 IOCNUM_RTC_READ = 100, 343 IOCNUM_RTC_WRITE = 101, 344 IOCNUM_RTC_SETTIME = 102, 345 IOCNUM_RTC_GETTIME = 103, 346 347 /* checkpoint */ 348 IOCNUM_SNAPSHOT_REQ = 113, 349 350 IOCNUM_RESTORE_TIME = 115 351 }; 352 353 #define VM_RUN \ 354 _IOW('v', IOCNUM_RUN, struct vm_run) 355 #define VM_SUSPEND \ 356 _IOW('v', IOCNUM_SUSPEND, struct vm_suspend) 357 #define VM_REINIT \ 358 _IO('v', IOCNUM_REINIT) 359 #define VM_ALLOC_MEMSEG_FBSD12 \ 360 _IOW('v', IOCNUM_ALLOC_MEMSEG, struct vm_memseg_fbsd12) 361 #define VM_ALLOC_MEMSEG \ 362 _IOW('v', IOCNUM_ALLOC_MEMSEG, struct vm_memseg) 363 #define VM_GET_MEMSEG_FBSD12 \ 364 _IOWR('v', IOCNUM_GET_MEMSEG, struct vm_memseg_fbsd12) 365 #define VM_GET_MEMSEG \ 366 _IOWR('v', IOCNUM_GET_MEMSEG, struct vm_memseg) 367 #define VM_MMAP_MEMSEG \ 368 _IOW('v', IOCNUM_MMAP_MEMSEG, struct vm_memmap) 369 #define VM_MMAP_GETNEXT \ 370 _IOWR('v', IOCNUM_MMAP_GETNEXT, struct vm_memmap) 371 #define VM_MUNMAP_MEMSEG \ 372 _IOW('v', IOCNUM_MUNMAP_MEMSEG, struct vm_munmap) 373 #define VM_SET_REGISTER \ 374 _IOW('v', IOCNUM_SET_REGISTER, struct vm_register) 375 #define VM_GET_REGISTER \ 376 _IOWR('v', IOCNUM_GET_REGISTER, struct vm_register) 377 #define VM_SET_SEGMENT_DESCRIPTOR \ 378 _IOW('v', IOCNUM_SET_SEGMENT_DESCRIPTOR, struct vm_seg_desc) 379 #define VM_GET_SEGMENT_DESCRIPTOR \ 380 _IOWR('v', IOCNUM_GET_SEGMENT_DESCRIPTOR, struct vm_seg_desc) 381 #define VM_SET_REGISTER_SET \ 382 _IOW('v', IOCNUM_SET_REGISTER_SET, struct vm_register_set) 383 #define VM_GET_REGISTER_SET \ 384 _IOWR('v', IOCNUM_GET_REGISTER_SET, struct vm_register_set) 385 #define VM_SET_KERNEMU_DEV \ 386 _IOW('v', IOCNUM_SET_KERNEMU_DEV, \ 387 struct vm_readwrite_kernemu_device) 388 #define VM_GET_KERNEMU_DEV \ 389 _IOWR('v', IOCNUM_GET_KERNEMU_DEV, \ 390 struct vm_readwrite_kernemu_device) 391 #define VM_INJECT_EXCEPTION \ 392 _IOW('v', IOCNUM_INJECT_EXCEPTION, struct vm_exception) 393 #define VM_LAPIC_IRQ \ 394 _IOW('v', IOCNUM_LAPIC_IRQ, struct vm_lapic_irq) 395 #define VM_LAPIC_LOCAL_IRQ \ 396 _IOW('v', IOCNUM_LAPIC_LOCAL_IRQ, struct vm_lapic_irq) 397 #define VM_LAPIC_MSI \ 398 _IOW('v', IOCNUM_LAPIC_MSI, struct vm_lapic_msi) 399 #define VM_IOAPIC_ASSERT_IRQ \ 400 _IOW('v', IOCNUM_IOAPIC_ASSERT_IRQ, struct vm_ioapic_irq) 401 #define VM_IOAPIC_DEASSERT_IRQ \ 402 _IOW('v', IOCNUM_IOAPIC_DEASSERT_IRQ, struct vm_ioapic_irq) 403 #define VM_IOAPIC_PULSE_IRQ \ 404 _IOW('v', IOCNUM_IOAPIC_PULSE_IRQ, struct vm_ioapic_irq) 405 #define VM_IOAPIC_PINCOUNT \ 406 _IOR('v', IOCNUM_IOAPIC_PINCOUNT, int) 407 #define VM_ISA_ASSERT_IRQ \ 408 _IOW('v', IOCNUM_ISA_ASSERT_IRQ, struct vm_isa_irq) 409 #define VM_ISA_DEASSERT_IRQ \ 410 _IOW('v', IOCNUM_ISA_DEASSERT_IRQ, struct vm_isa_irq) 411 #define VM_ISA_PULSE_IRQ \ 412 _IOW('v', IOCNUM_ISA_PULSE_IRQ, struct vm_isa_irq) 413 #define VM_ISA_SET_IRQ_TRIGGER \ 414 _IOW('v', IOCNUM_ISA_SET_IRQ_TRIGGER, struct vm_isa_irq_trigger) 415 #define VM_SET_CAPABILITY \ 416 _IOW('v', IOCNUM_SET_CAPABILITY, struct vm_capability) 417 #define VM_GET_CAPABILITY \ 418 _IOWR('v', IOCNUM_GET_CAPABILITY, struct vm_capability) 419 #define VM_BIND_PPTDEV \ 420 _IOW('v', IOCNUM_BIND_PPTDEV, struct vm_pptdev) 421 #define VM_UNBIND_PPTDEV \ 422 _IOW('v', IOCNUM_UNBIND_PPTDEV, struct vm_pptdev) 423 #define VM_MAP_PPTDEV_MMIO \ 424 _IOW('v', IOCNUM_MAP_PPTDEV_MMIO, struct vm_pptdev_mmio) 425 #define VM_PPTDEV_MSI \ 426 _IOW('v', IOCNUM_PPTDEV_MSI, struct vm_pptdev_msi) 427 #define VM_PPTDEV_MSIX \ 428 _IOW('v', IOCNUM_PPTDEV_MSIX, struct vm_pptdev_msix) 429 #define VM_PPTDEV_DISABLE_MSIX \ 430 _IOW('v', IOCNUM_PPTDEV_DISABLE_MSIX, struct vm_pptdev) 431 #define VM_UNMAP_PPTDEV_MMIO \ 432 _IOW('v', IOCNUM_UNMAP_PPTDEV_MMIO, struct vm_pptdev_mmio) 433 #define VM_INJECT_NMI \ 434 _IOW('v', IOCNUM_INJECT_NMI, struct vm_nmi) 435 #define VM_STATS \ 436 _IOWR('v', IOCNUM_VM_STATS, struct vm_stats) 437 #define VM_STAT_DESC \ 438 _IOWR('v', IOCNUM_VM_STAT_DESC, struct vm_stat_desc) 439 #define VM_SET_X2APIC_STATE \ 440 _IOW('v', IOCNUM_SET_X2APIC_STATE, struct vm_x2apic) 441 #define VM_GET_X2APIC_STATE \ 442 _IOWR('v', IOCNUM_GET_X2APIC_STATE, struct vm_x2apic) 443 #define VM_GET_HPET_CAPABILITIES \ 444 _IOR('v', IOCNUM_GET_HPET_CAPABILITIES, struct vm_hpet_cap) 445 #define VM_SET_TOPOLOGY \ 446 _IOW('v', IOCNUM_SET_TOPOLOGY, struct vm_cpu_topology) 447 #define VM_GET_TOPOLOGY \ 448 _IOR('v', IOCNUM_GET_TOPOLOGY, struct vm_cpu_topology) 449 #define VM_GET_GPA_PMAP \ 450 _IOWR('v', IOCNUM_GET_GPA_PMAP, struct vm_gpa_pte) 451 #define VM_GLA2GPA \ 452 _IOWR('v', IOCNUM_GLA2GPA, struct vm_gla2gpa) 453 #define VM_GLA2GPA_NOFAULT \ 454 _IOWR('v', IOCNUM_GLA2GPA_NOFAULT, struct vm_gla2gpa) 455 #define VM_ACTIVATE_CPU \ 456 _IOW('v', IOCNUM_ACTIVATE_CPU, struct vm_activate_cpu) 457 #define VM_GET_CPUS \ 458 _IOW('v', IOCNUM_GET_CPUSET, struct vm_cpuset) 459 #define VM_SUSPEND_CPU \ 460 _IOW('v', IOCNUM_SUSPEND_CPU, struct vm_activate_cpu) 461 #define VM_RESUME_CPU \ 462 _IOW('v', IOCNUM_RESUME_CPU, struct vm_activate_cpu) 463 #define VM_SET_INTINFO \ 464 _IOW('v', IOCNUM_SET_INTINFO, struct vm_intinfo) 465 #define VM_GET_INTINFO \ 466 _IOWR('v', IOCNUM_GET_INTINFO, struct vm_intinfo) 467 #define VM_RTC_WRITE \ 468 _IOW('v', IOCNUM_RTC_WRITE, struct vm_rtc_data) 469 #define VM_RTC_READ \ 470 _IOWR('v', IOCNUM_RTC_READ, struct vm_rtc_data) 471 #define VM_RTC_SETTIME \ 472 _IOW('v', IOCNUM_RTC_SETTIME, struct vm_rtc_time) 473 #define VM_RTC_GETTIME \ 474 _IOR('v', IOCNUM_RTC_GETTIME, struct vm_rtc_time) 475 #define VM_RESTART_INSTRUCTION \ 476 _IOW('v', IOCNUM_RESTART_INSTRUCTION, int) 477 #define VM_SNAPSHOT_REQ \ 478 _IOWR('v', IOCNUM_SNAPSHOT_REQ, struct vm_snapshot_meta) 479 #define VM_RESTORE_TIME \ 480 _IOWR('v', IOCNUM_RESTORE_TIME, int) 481 #endif 482