1 /*- 2 * Copyright (c) 2011 NetApp, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef _VMM_DEV_H_ 30 #define _VMM_DEV_H_ 31 32 #ifdef _KERNEL 33 void vmmdev_init(void); 34 int vmmdev_cleanup(void); 35 #endif 36 37 struct vm_memory_segment { 38 vm_paddr_t gpa; /* in */ 39 size_t len; 40 int wired; 41 }; 42 43 struct vm_register { 44 int cpuid; 45 int regnum; /* enum vm_reg_name */ 46 uint64_t regval; 47 }; 48 49 struct vm_seg_desc { /* data or code segment */ 50 int cpuid; 51 int regnum; /* enum vm_reg_name */ 52 struct seg_desc desc; 53 }; 54 55 struct vm_run { 56 int cpuid; 57 uint64_t rip; /* start running here */ 58 struct vm_exit vm_exit; 59 }; 60 61 struct vm_exception { 62 int cpuid; 63 int vector; 64 uint32_t error_code; 65 int error_code_valid; 66 }; 67 68 struct vm_lapic_msi { 69 uint64_t msg; 70 uint64_t addr; 71 }; 72 73 struct vm_lapic_irq { 74 int cpuid; 75 int vector; 76 }; 77 78 struct vm_ioapic_irq { 79 int irq; 80 }; 81 82 struct vm_isa_irq { 83 int atpic_irq; 84 int ioapic_irq; 85 }; 86 87 struct vm_capability { 88 int cpuid; 89 enum vm_cap_type captype; 90 int capval; 91 int allcpus; 92 }; 93 94 struct vm_pptdev { 95 int bus; 96 int slot; 97 int func; 98 }; 99 100 struct vm_pptdev_mmio { 101 int bus; 102 int slot; 103 int func; 104 vm_paddr_t gpa; 105 vm_paddr_t hpa; 106 size_t len; 107 }; 108 109 struct vm_pptdev_msi { 110 int vcpu; 111 int bus; 112 int slot; 113 int func; 114 int numvec; /* 0 means disabled */ 115 uint64_t msg; 116 uint64_t addr; 117 }; 118 119 struct vm_pptdev_msix { 120 int vcpu; 121 int bus; 122 int slot; 123 int func; 124 int idx; 125 uint64_t msg; 126 uint32_t vector_control; 127 uint64_t addr; 128 }; 129 130 struct vm_nmi { 131 int cpuid; 132 }; 133 134 #define MAX_VM_STATS 64 135 struct vm_stats { 136 int cpuid; /* in */ 137 int num_entries; /* out */ 138 struct timeval tv; 139 uint64_t statbuf[MAX_VM_STATS]; 140 }; 141 142 struct vm_stat_desc { 143 int index; /* in */ 144 char desc[128]; /* out */ 145 }; 146 147 struct vm_x2apic { 148 int cpuid; 149 enum x2apic_state state; 150 }; 151 152 struct vm_gpa_pte { 153 uint64_t gpa; /* in */ 154 uint64_t pte[4]; /* out */ 155 int ptenum; 156 }; 157 158 struct vm_hpet_cap { 159 uint32_t capabilities; /* lower 32 bits of HPET capabilities */ 160 }; 161 162 enum { 163 /* general routines */ 164 IOCNUM_ABIVERS = 0, 165 IOCNUM_RUN = 1, 166 IOCNUM_SET_CAPABILITY = 2, 167 IOCNUM_GET_CAPABILITY = 3, 168 IOCNUM_SUSPEND = 4, 169 170 /* memory apis */ 171 IOCNUM_MAP_MEMORY = 10, 172 IOCNUM_GET_MEMORY_SEG = 11, 173 IOCNUM_GET_GPA_PMAP = 12, 174 175 /* register/state accessors */ 176 IOCNUM_SET_REGISTER = 20, 177 IOCNUM_GET_REGISTER = 21, 178 IOCNUM_SET_SEGMENT_DESCRIPTOR = 22, 179 IOCNUM_GET_SEGMENT_DESCRIPTOR = 23, 180 181 /* interrupt injection */ 182 IOCNUM_INJECT_EXCEPTION = 30, 183 IOCNUM_LAPIC_IRQ = 31, 184 IOCNUM_INJECT_NMI = 32, 185 IOCNUM_IOAPIC_ASSERT_IRQ = 33, 186 IOCNUM_IOAPIC_DEASSERT_IRQ = 34, 187 IOCNUM_IOAPIC_PULSE_IRQ = 35, 188 IOCNUM_LAPIC_MSI = 36, 189 IOCNUM_LAPIC_LOCAL_IRQ = 37, 190 IOCNUM_IOAPIC_PINCOUNT = 38, 191 192 /* PCI pass-thru */ 193 IOCNUM_BIND_PPTDEV = 40, 194 IOCNUM_UNBIND_PPTDEV = 41, 195 IOCNUM_MAP_PPTDEV_MMIO = 42, 196 IOCNUM_PPTDEV_MSI = 43, 197 IOCNUM_PPTDEV_MSIX = 44, 198 199 /* statistics */ 200 IOCNUM_VM_STATS = 50, 201 IOCNUM_VM_STAT_DESC = 51, 202 203 /* kernel device state */ 204 IOCNUM_SET_X2APIC_STATE = 60, 205 IOCNUM_GET_X2APIC_STATE = 61, 206 IOCNUM_GET_HPET_CAPABILITIES = 62, 207 208 /* legacy interrupt injection */ 209 IOCNUM_ISA_ASSERT_IRQ = 80, 210 IOCNUM_ISA_DEASSERT_IRQ = 81, 211 IOCNUM_ISA_PULSE_IRQ = 82, 212 }; 213 214 #define VM_RUN \ 215 _IOWR('v', IOCNUM_RUN, struct vm_run) 216 #define VM_SUSPEND \ 217 _IO('v', IOCNUM_SUSPEND) 218 #define VM_MAP_MEMORY \ 219 _IOWR('v', IOCNUM_MAP_MEMORY, struct vm_memory_segment) 220 #define VM_GET_MEMORY_SEG \ 221 _IOWR('v', IOCNUM_GET_MEMORY_SEG, struct vm_memory_segment) 222 #define VM_SET_REGISTER \ 223 _IOW('v', IOCNUM_SET_REGISTER, struct vm_register) 224 #define VM_GET_REGISTER \ 225 _IOWR('v', IOCNUM_GET_REGISTER, struct vm_register) 226 #define VM_SET_SEGMENT_DESCRIPTOR \ 227 _IOW('v', IOCNUM_SET_SEGMENT_DESCRIPTOR, struct vm_seg_desc) 228 #define VM_GET_SEGMENT_DESCRIPTOR \ 229 _IOWR('v', IOCNUM_GET_SEGMENT_DESCRIPTOR, struct vm_seg_desc) 230 #define VM_INJECT_EXCEPTION \ 231 _IOW('v', IOCNUM_INJECT_EXCEPTION, struct vm_exception) 232 #define VM_LAPIC_IRQ \ 233 _IOW('v', IOCNUM_LAPIC_IRQ, struct vm_lapic_irq) 234 #define VM_LAPIC_LOCAL_IRQ \ 235 _IOW('v', IOCNUM_LAPIC_LOCAL_IRQ, struct vm_lapic_irq) 236 #define VM_LAPIC_MSI \ 237 _IOW('v', IOCNUM_LAPIC_MSI, struct vm_lapic_msi) 238 #define VM_IOAPIC_ASSERT_IRQ \ 239 _IOW('v', IOCNUM_IOAPIC_ASSERT_IRQ, struct vm_ioapic_irq) 240 #define VM_IOAPIC_DEASSERT_IRQ \ 241 _IOW('v', IOCNUM_IOAPIC_DEASSERT_IRQ, struct vm_ioapic_irq) 242 #define VM_IOAPIC_PULSE_IRQ \ 243 _IOW('v', IOCNUM_IOAPIC_PULSE_IRQ, struct vm_ioapic_irq) 244 #define VM_IOAPIC_PINCOUNT \ 245 _IOR('v', IOCNUM_IOAPIC_PINCOUNT, int) 246 #define VM_ISA_ASSERT_IRQ \ 247 _IOW('v', IOCNUM_ISA_ASSERT_IRQ, struct vm_isa_irq) 248 #define VM_ISA_DEASSERT_IRQ \ 249 _IOW('v', IOCNUM_ISA_DEASSERT_IRQ, struct vm_isa_irq) 250 #define VM_ISA_PULSE_IRQ \ 251 _IOW('v', IOCNUM_ISA_PULSE_IRQ, struct vm_isa_irq) 252 #define VM_SET_CAPABILITY \ 253 _IOW('v', IOCNUM_SET_CAPABILITY, struct vm_capability) 254 #define VM_GET_CAPABILITY \ 255 _IOWR('v', IOCNUM_GET_CAPABILITY, struct vm_capability) 256 #define VM_BIND_PPTDEV \ 257 _IOW('v', IOCNUM_BIND_PPTDEV, struct vm_pptdev) 258 #define VM_UNBIND_PPTDEV \ 259 _IOW('v', IOCNUM_UNBIND_PPTDEV, struct vm_pptdev) 260 #define VM_MAP_PPTDEV_MMIO \ 261 _IOW('v', IOCNUM_MAP_PPTDEV_MMIO, struct vm_pptdev_mmio) 262 #define VM_PPTDEV_MSI \ 263 _IOW('v', IOCNUM_PPTDEV_MSI, struct vm_pptdev_msi) 264 #define VM_PPTDEV_MSIX \ 265 _IOW('v', IOCNUM_PPTDEV_MSIX, struct vm_pptdev_msix) 266 #define VM_INJECT_NMI \ 267 _IOW('v', IOCNUM_INJECT_NMI, struct vm_nmi) 268 #define VM_STATS \ 269 _IOWR('v', IOCNUM_VM_STATS, struct vm_stats) 270 #define VM_STAT_DESC \ 271 _IOWR('v', IOCNUM_VM_STAT_DESC, struct vm_stat_desc) 272 #define VM_SET_X2APIC_STATE \ 273 _IOW('v', IOCNUM_SET_X2APIC_STATE, struct vm_x2apic) 274 #define VM_GET_X2APIC_STATE \ 275 _IOWR('v', IOCNUM_GET_X2APIC_STATE, struct vm_x2apic) 276 #define VM_GET_HPET_CAPABILITIES \ 277 _IOR('v', IOCNUM_GET_HPET_CAPABILITIES, struct vm_hpet_cap) 278 #define VM_GET_GPA_PMAP \ 279 _IOWR('v', IOCNUM_GET_GPA_PMAP, struct vm_gpa_pte) 280 #endif 281