1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011 NetApp, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _VMM_DEV_H_ 30 #define _VMM_DEV_H_ 31 32 struct vm_snapshot_meta; 33 34 #ifdef _KERNEL 35 void vmmdev_init(void); 36 int vmmdev_cleanup(void); 37 #endif 38 39 struct vm_memmap { 40 vm_paddr_t gpa; 41 int segid; /* memory segment */ 42 vm_ooffset_t segoff; /* offset into memory segment */ 43 size_t len; /* mmap length */ 44 int prot; /* RWX */ 45 int flags; 46 }; 47 #define VM_MEMMAP_F_WIRED 0x01 48 #define VM_MEMMAP_F_IOMMU 0x02 49 50 struct vm_munmap { 51 vm_paddr_t gpa; 52 size_t len; 53 }; 54 55 #define VM_MEMSEG_NAME(m) ((m)->name[0] != '\0' ? (m)->name : NULL) 56 struct vm_memseg { 57 int segid; 58 size_t len; 59 char name[VM_MAX_SUFFIXLEN + 1]; 60 }; 61 62 struct vm_memseg_fbsd12 { 63 int segid; 64 size_t len; 65 char name[64]; 66 }; 67 _Static_assert(sizeof(struct vm_memseg_fbsd12) == 80, "COMPAT_FREEBSD12 ABI"); 68 69 struct vm_register { 70 int cpuid; 71 int regnum; /* enum vm_reg_name */ 72 uint64_t regval; 73 }; 74 75 struct vm_seg_desc { /* data or code segment */ 76 int cpuid; 77 int regnum; /* enum vm_reg_name */ 78 struct seg_desc desc; 79 }; 80 81 struct vm_register_set { 82 int cpuid; 83 unsigned int count; 84 const int *regnums; /* enum vm_reg_name */ 85 uint64_t *regvals; 86 }; 87 88 struct vm_run { 89 int cpuid; 90 cpuset_t *cpuset; /* CPU set storage */ 91 size_t cpusetsize; 92 struct vm_exit *vm_exit; 93 }; 94 95 struct vm_exception { 96 int cpuid; 97 int vector; 98 uint32_t error_code; 99 int error_code_valid; 100 int restart_instruction; 101 }; 102 103 struct vm_lapic_msi { 104 uint64_t msg; 105 uint64_t addr; 106 }; 107 108 struct vm_lapic_irq { 109 int cpuid; 110 int vector; 111 }; 112 113 struct vm_ioapic_irq { 114 int irq; 115 }; 116 117 struct vm_isa_irq { 118 int atpic_irq; 119 int ioapic_irq; 120 }; 121 122 struct vm_isa_irq_trigger { 123 int atpic_irq; 124 enum vm_intr_trigger trigger; 125 }; 126 127 struct vm_capability { 128 int cpuid; 129 enum vm_cap_type captype; 130 int capval; 131 int allcpus; 132 }; 133 134 struct vm_pptdev { 135 int bus; 136 int slot; 137 int func; 138 }; 139 140 struct vm_pptdev_mmio { 141 int bus; 142 int slot; 143 int func; 144 vm_paddr_t gpa; 145 vm_paddr_t hpa; 146 size_t len; 147 }; 148 149 struct vm_pptdev_msi { 150 int vcpu; /* unused */ 151 int bus; 152 int slot; 153 int func; 154 int numvec; /* 0 means disabled */ 155 uint64_t msg; 156 uint64_t addr; 157 }; 158 159 struct vm_pptdev_msix { 160 int vcpu; /* unused */ 161 int bus; 162 int slot; 163 int func; 164 int idx; 165 uint64_t msg; 166 uint32_t vector_control; 167 uint64_t addr; 168 }; 169 170 struct vm_nmi { 171 int cpuid; 172 }; 173 174 #define MAX_VM_STATS 64 175 struct vm_stats { 176 int cpuid; /* in */ 177 int index; /* in */ 178 int num_entries; /* out */ 179 struct timeval tv; 180 uint64_t statbuf[MAX_VM_STATS]; 181 }; 182 183 struct vm_stat_desc { 184 int index; /* in */ 185 char desc[128]; /* out */ 186 }; 187 188 struct vm_x2apic { 189 int cpuid; 190 enum x2apic_state state; 191 }; 192 193 struct vm_gpa_pte { 194 uint64_t gpa; /* in */ 195 uint64_t pte[4]; /* out */ 196 int ptenum; 197 }; 198 199 struct vm_hpet_cap { 200 uint32_t capabilities; /* lower 32 bits of HPET capabilities */ 201 }; 202 203 struct vm_suspend { 204 enum vm_suspend_how how; 205 }; 206 207 struct vm_gla2gpa { 208 int vcpuid; /* inputs */ 209 int prot; /* PROT_READ or PROT_WRITE */ 210 uint64_t gla; 211 struct vm_guest_paging paging; 212 int fault; /* outputs */ 213 uint64_t gpa; 214 }; 215 216 struct vm_activate_cpu { 217 int vcpuid; 218 }; 219 220 struct vm_cpuset { 221 int which; 222 int cpusetsize; 223 cpuset_t *cpus; 224 }; 225 #define VM_ACTIVE_CPUS 0 226 #define VM_SUSPENDED_CPUS 1 227 #define VM_DEBUG_CPUS 2 228 229 struct vm_intinfo { 230 int vcpuid; 231 uint64_t info1; 232 uint64_t info2; 233 }; 234 235 struct vm_rtc_time { 236 time_t secs; 237 }; 238 239 struct vm_rtc_data { 240 int offset; 241 uint8_t value; 242 }; 243 244 struct vm_cpu_topology { 245 uint16_t sockets; 246 uint16_t cores; 247 uint16_t threads; 248 uint16_t maxcpus; 249 }; 250 251 struct vm_readwrite_kernemu_device { 252 int vcpuid; 253 unsigned access_width : 3; 254 unsigned _unused : 29; 255 uint64_t gpa; 256 uint64_t value; 257 }; 258 _Static_assert(sizeof(struct vm_readwrite_kernemu_device) == 24, "ABI"); 259 260 enum { 261 /* general routines */ 262 IOCNUM_ABIVERS = 0, 263 IOCNUM_RUN = 1, 264 IOCNUM_SET_CAPABILITY = 2, 265 IOCNUM_GET_CAPABILITY = 3, 266 IOCNUM_SUSPEND = 4, 267 IOCNUM_REINIT = 5, 268 269 /* memory apis */ 270 IOCNUM_MAP_MEMORY = 10, /* deprecated */ 271 IOCNUM_GET_MEMORY_SEG = 11, /* deprecated */ 272 IOCNUM_GET_GPA_PMAP = 12, 273 IOCNUM_GLA2GPA = 13, 274 IOCNUM_ALLOC_MEMSEG = 14, 275 IOCNUM_GET_MEMSEG = 15, 276 IOCNUM_MMAP_MEMSEG = 16, 277 IOCNUM_MMAP_GETNEXT = 17, 278 IOCNUM_GLA2GPA_NOFAULT = 18, 279 IOCNUM_MUNMAP_MEMSEG = 19, 280 281 /* register/state accessors */ 282 IOCNUM_SET_REGISTER = 20, 283 IOCNUM_GET_REGISTER = 21, 284 IOCNUM_SET_SEGMENT_DESCRIPTOR = 22, 285 IOCNUM_GET_SEGMENT_DESCRIPTOR = 23, 286 IOCNUM_SET_REGISTER_SET = 24, 287 IOCNUM_GET_REGISTER_SET = 25, 288 IOCNUM_GET_KERNEMU_DEV = 26, 289 IOCNUM_SET_KERNEMU_DEV = 27, 290 291 /* interrupt injection */ 292 IOCNUM_GET_INTINFO = 28, 293 IOCNUM_SET_INTINFO = 29, 294 IOCNUM_INJECT_EXCEPTION = 30, 295 IOCNUM_LAPIC_IRQ = 31, 296 IOCNUM_INJECT_NMI = 32, 297 IOCNUM_IOAPIC_ASSERT_IRQ = 33, 298 IOCNUM_IOAPIC_DEASSERT_IRQ = 34, 299 IOCNUM_IOAPIC_PULSE_IRQ = 35, 300 IOCNUM_LAPIC_MSI = 36, 301 IOCNUM_LAPIC_LOCAL_IRQ = 37, 302 IOCNUM_IOAPIC_PINCOUNT = 38, 303 IOCNUM_RESTART_INSTRUCTION = 39, 304 305 /* PCI pass-thru */ 306 IOCNUM_BIND_PPTDEV = 40, 307 IOCNUM_UNBIND_PPTDEV = 41, 308 IOCNUM_MAP_PPTDEV_MMIO = 42, 309 IOCNUM_PPTDEV_MSI = 43, 310 IOCNUM_PPTDEV_MSIX = 44, 311 IOCNUM_PPTDEV_DISABLE_MSIX = 45, 312 IOCNUM_UNMAP_PPTDEV_MMIO = 46, 313 314 /* statistics */ 315 IOCNUM_VM_STATS = 50, 316 IOCNUM_VM_STAT_DESC = 51, 317 318 /* kernel device state */ 319 IOCNUM_SET_X2APIC_STATE = 60, 320 IOCNUM_GET_X2APIC_STATE = 61, 321 IOCNUM_GET_HPET_CAPABILITIES = 62, 322 323 /* CPU Topology */ 324 IOCNUM_SET_TOPOLOGY = 63, 325 IOCNUM_GET_TOPOLOGY = 64, 326 327 /* legacy interrupt injection */ 328 IOCNUM_ISA_ASSERT_IRQ = 80, 329 IOCNUM_ISA_DEASSERT_IRQ = 81, 330 IOCNUM_ISA_PULSE_IRQ = 82, 331 IOCNUM_ISA_SET_IRQ_TRIGGER = 83, 332 333 /* vm_cpuset */ 334 IOCNUM_ACTIVATE_CPU = 90, 335 IOCNUM_GET_CPUSET = 91, 336 IOCNUM_SUSPEND_CPU = 92, 337 IOCNUM_RESUME_CPU = 93, 338 339 /* RTC */ 340 IOCNUM_RTC_READ = 100, 341 IOCNUM_RTC_WRITE = 101, 342 IOCNUM_RTC_SETTIME = 102, 343 IOCNUM_RTC_GETTIME = 103, 344 345 /* checkpoint */ 346 IOCNUM_SNAPSHOT_REQ = 113, 347 348 IOCNUM_RESTORE_TIME = 115 349 }; 350 351 #define VM_RUN \ 352 _IOW('v', IOCNUM_RUN, struct vm_run) 353 #define VM_SUSPEND \ 354 _IOW('v', IOCNUM_SUSPEND, struct vm_suspend) 355 #define VM_REINIT \ 356 _IO('v', IOCNUM_REINIT) 357 #define VM_ALLOC_MEMSEG_FBSD12 \ 358 _IOW('v', IOCNUM_ALLOC_MEMSEG, struct vm_memseg_fbsd12) 359 #define VM_ALLOC_MEMSEG \ 360 _IOW('v', IOCNUM_ALLOC_MEMSEG, struct vm_memseg) 361 #define VM_GET_MEMSEG_FBSD12 \ 362 _IOWR('v', IOCNUM_GET_MEMSEG, struct vm_memseg_fbsd12) 363 #define VM_GET_MEMSEG \ 364 _IOWR('v', IOCNUM_GET_MEMSEG, struct vm_memseg) 365 #define VM_MMAP_MEMSEG \ 366 _IOW('v', IOCNUM_MMAP_MEMSEG, struct vm_memmap) 367 #define VM_MMAP_GETNEXT \ 368 _IOWR('v', IOCNUM_MMAP_GETNEXT, struct vm_memmap) 369 #define VM_MUNMAP_MEMSEG \ 370 _IOW('v', IOCNUM_MUNMAP_MEMSEG, struct vm_munmap) 371 #define VM_SET_REGISTER \ 372 _IOW('v', IOCNUM_SET_REGISTER, struct vm_register) 373 #define VM_GET_REGISTER \ 374 _IOWR('v', IOCNUM_GET_REGISTER, struct vm_register) 375 #define VM_SET_SEGMENT_DESCRIPTOR \ 376 _IOW('v', IOCNUM_SET_SEGMENT_DESCRIPTOR, struct vm_seg_desc) 377 #define VM_GET_SEGMENT_DESCRIPTOR \ 378 _IOWR('v', IOCNUM_GET_SEGMENT_DESCRIPTOR, struct vm_seg_desc) 379 #define VM_SET_REGISTER_SET \ 380 _IOW('v', IOCNUM_SET_REGISTER_SET, struct vm_register_set) 381 #define VM_GET_REGISTER_SET \ 382 _IOWR('v', IOCNUM_GET_REGISTER_SET, struct vm_register_set) 383 #define VM_SET_KERNEMU_DEV \ 384 _IOW('v', IOCNUM_SET_KERNEMU_DEV, \ 385 struct vm_readwrite_kernemu_device) 386 #define VM_GET_KERNEMU_DEV \ 387 _IOWR('v', IOCNUM_GET_KERNEMU_DEV, \ 388 struct vm_readwrite_kernemu_device) 389 #define VM_INJECT_EXCEPTION \ 390 _IOW('v', IOCNUM_INJECT_EXCEPTION, struct vm_exception) 391 #define VM_LAPIC_IRQ \ 392 _IOW('v', IOCNUM_LAPIC_IRQ, struct vm_lapic_irq) 393 #define VM_LAPIC_LOCAL_IRQ \ 394 _IOW('v', IOCNUM_LAPIC_LOCAL_IRQ, struct vm_lapic_irq) 395 #define VM_LAPIC_MSI \ 396 _IOW('v', IOCNUM_LAPIC_MSI, struct vm_lapic_msi) 397 #define VM_IOAPIC_ASSERT_IRQ \ 398 _IOW('v', IOCNUM_IOAPIC_ASSERT_IRQ, struct vm_ioapic_irq) 399 #define VM_IOAPIC_DEASSERT_IRQ \ 400 _IOW('v', IOCNUM_IOAPIC_DEASSERT_IRQ, struct vm_ioapic_irq) 401 #define VM_IOAPIC_PULSE_IRQ \ 402 _IOW('v', IOCNUM_IOAPIC_PULSE_IRQ, struct vm_ioapic_irq) 403 #define VM_IOAPIC_PINCOUNT \ 404 _IOR('v', IOCNUM_IOAPIC_PINCOUNT, int) 405 #define VM_ISA_ASSERT_IRQ \ 406 _IOW('v', IOCNUM_ISA_ASSERT_IRQ, struct vm_isa_irq) 407 #define VM_ISA_DEASSERT_IRQ \ 408 _IOW('v', IOCNUM_ISA_DEASSERT_IRQ, struct vm_isa_irq) 409 #define VM_ISA_PULSE_IRQ \ 410 _IOW('v', IOCNUM_ISA_PULSE_IRQ, struct vm_isa_irq) 411 #define VM_ISA_SET_IRQ_TRIGGER \ 412 _IOW('v', IOCNUM_ISA_SET_IRQ_TRIGGER, struct vm_isa_irq_trigger) 413 #define VM_SET_CAPABILITY \ 414 _IOW('v', IOCNUM_SET_CAPABILITY, struct vm_capability) 415 #define VM_GET_CAPABILITY \ 416 _IOWR('v', IOCNUM_GET_CAPABILITY, struct vm_capability) 417 #define VM_BIND_PPTDEV \ 418 _IOW('v', IOCNUM_BIND_PPTDEV, struct vm_pptdev) 419 #define VM_UNBIND_PPTDEV \ 420 _IOW('v', IOCNUM_UNBIND_PPTDEV, struct vm_pptdev) 421 #define VM_MAP_PPTDEV_MMIO \ 422 _IOW('v', IOCNUM_MAP_PPTDEV_MMIO, struct vm_pptdev_mmio) 423 #define VM_PPTDEV_MSI \ 424 _IOW('v', IOCNUM_PPTDEV_MSI, struct vm_pptdev_msi) 425 #define VM_PPTDEV_MSIX \ 426 _IOW('v', IOCNUM_PPTDEV_MSIX, struct vm_pptdev_msix) 427 #define VM_PPTDEV_DISABLE_MSIX \ 428 _IOW('v', IOCNUM_PPTDEV_DISABLE_MSIX, struct vm_pptdev) 429 #define VM_UNMAP_PPTDEV_MMIO \ 430 _IOW('v', IOCNUM_UNMAP_PPTDEV_MMIO, struct vm_pptdev_mmio) 431 #define VM_INJECT_NMI \ 432 _IOW('v', IOCNUM_INJECT_NMI, struct vm_nmi) 433 #define VM_STATS \ 434 _IOWR('v', IOCNUM_VM_STATS, struct vm_stats) 435 #define VM_STAT_DESC \ 436 _IOWR('v', IOCNUM_VM_STAT_DESC, struct vm_stat_desc) 437 #define VM_SET_X2APIC_STATE \ 438 _IOW('v', IOCNUM_SET_X2APIC_STATE, struct vm_x2apic) 439 #define VM_GET_X2APIC_STATE \ 440 _IOWR('v', IOCNUM_GET_X2APIC_STATE, struct vm_x2apic) 441 #define VM_GET_HPET_CAPABILITIES \ 442 _IOR('v', IOCNUM_GET_HPET_CAPABILITIES, struct vm_hpet_cap) 443 #define VM_SET_TOPOLOGY \ 444 _IOW('v', IOCNUM_SET_TOPOLOGY, struct vm_cpu_topology) 445 #define VM_GET_TOPOLOGY \ 446 _IOR('v', IOCNUM_GET_TOPOLOGY, struct vm_cpu_topology) 447 #define VM_GET_GPA_PMAP \ 448 _IOWR('v', IOCNUM_GET_GPA_PMAP, struct vm_gpa_pte) 449 #define VM_GLA2GPA \ 450 _IOWR('v', IOCNUM_GLA2GPA, struct vm_gla2gpa) 451 #define VM_GLA2GPA_NOFAULT \ 452 _IOWR('v', IOCNUM_GLA2GPA_NOFAULT, struct vm_gla2gpa) 453 #define VM_ACTIVATE_CPU \ 454 _IOW('v', IOCNUM_ACTIVATE_CPU, struct vm_activate_cpu) 455 #define VM_GET_CPUS \ 456 _IOW('v', IOCNUM_GET_CPUSET, struct vm_cpuset) 457 #define VM_SUSPEND_CPU \ 458 _IOW('v', IOCNUM_SUSPEND_CPU, struct vm_activate_cpu) 459 #define VM_RESUME_CPU \ 460 _IOW('v', IOCNUM_RESUME_CPU, struct vm_activate_cpu) 461 #define VM_SET_INTINFO \ 462 _IOW('v', IOCNUM_SET_INTINFO, struct vm_intinfo) 463 #define VM_GET_INTINFO \ 464 _IOWR('v', IOCNUM_GET_INTINFO, struct vm_intinfo) 465 #define VM_RTC_WRITE \ 466 _IOW('v', IOCNUM_RTC_WRITE, struct vm_rtc_data) 467 #define VM_RTC_READ \ 468 _IOWR('v', IOCNUM_RTC_READ, struct vm_rtc_data) 469 #define VM_RTC_SETTIME \ 470 _IOW('v', IOCNUM_RTC_SETTIME, struct vm_rtc_time) 471 #define VM_RTC_GETTIME \ 472 _IOR('v', IOCNUM_RTC_GETTIME, struct vm_rtc_time) 473 #define VM_RESTART_INSTRUCTION \ 474 _IOW('v', IOCNUM_RESTART_INSTRUCTION, int) 475 #define VM_SNAPSHOT_REQ \ 476 _IOWR('v', IOCNUM_SNAPSHOT_REQ, struct vm_snapshot_meta) 477 #define VM_RESTORE_TIME \ 478 _IOWR('v', IOCNUM_RESTORE_TIME, int) 479 #endif 480