1 /*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 4. Neither the name of the University nor the names of its contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 30 * $FreeBSD$ 31 */ 32 33 #ifndef _MACHINE_SPECIALREG_H_ 34 #define _MACHINE_SPECIALREG_H_ 35 36 /* 37 * Bits in 386 special registers: 38 */ 39 #define CR0_PE 0x00000001 /* Protected mode Enable */ 40 #define CR0_MP 0x00000002 /* "Math" (fpu) Present */ 41 #define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */ 42 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 43 #define CR0_PG 0x80000000 /* PaGing enable */ 44 45 /* 46 * Bits in 486 special registers: 47 */ 48 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 49 #define CR0_WP 0x00010000 /* Write Protect (honor page protect in 50 all modes) */ 51 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 52 #define CR0_NW 0x20000000 /* Not Write-through */ 53 #define CR0_CD 0x40000000 /* Cache Disable */ 54 55 /* 56 * Bits in PPro special registers 57 */ 58 #define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */ 59 #define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */ 60 #define CR4_TSD 0x00000004 /* Time stamp disable */ 61 #define CR4_DE 0x00000008 /* Debugging extensions */ 62 #define CR4_PSE 0x00000010 /* Page size extensions */ 63 #define CR4_PAE 0x00000020 /* Physical address extension */ 64 #define CR4_MCE 0x00000040 /* Machine check enable */ 65 #define CR4_PGE 0x00000080 /* Page global enable */ 66 #define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ 67 #define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */ 68 #define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */ 69 70 /* 71 * Bits in AMD64 special registers. EFER is 64 bits wide. 72 */ 73 #define EFER_SCE 0x000000001 /* System Call Extensions (R/W) */ 74 #define EFER_LME 0x000000100 /* Long mode enable (R/W) */ 75 #define EFER_LMA 0x000000400 /* Long mode active (R) */ 76 #define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */ 77 78 /* 79 * CPUID instruction features register 80 */ 81 #define CPUID_FPU 0x00000001 82 #define CPUID_VME 0x00000002 83 #define CPUID_DE 0x00000004 84 #define CPUID_PSE 0x00000008 85 #define CPUID_TSC 0x00000010 86 #define CPUID_MSR 0x00000020 87 #define CPUID_PAE 0x00000040 88 #define CPUID_MCE 0x00000080 89 #define CPUID_CX8 0x00000100 90 #define CPUID_APIC 0x00000200 91 #define CPUID_B10 0x00000400 92 #define CPUID_SEP 0x00000800 93 #define CPUID_MTRR 0x00001000 94 #define CPUID_PGE 0x00002000 95 #define CPUID_MCA 0x00004000 96 #define CPUID_CMOV 0x00008000 97 #define CPUID_PAT 0x00010000 98 #define CPUID_PSE36 0x00020000 99 #define CPUID_PSN 0x00040000 100 #define CPUID_CLFSH 0x00080000 101 #define CPUID_B20 0x00100000 102 #define CPUID_DS 0x00200000 103 #define CPUID_ACPI 0x00400000 104 #define CPUID_MMX 0x00800000 105 #define CPUID_FXSR 0x01000000 106 #define CPUID_SSE 0x02000000 107 #define CPUID_XMM 0x02000000 108 #define CPUID_SSE2 0x04000000 109 #define CPUID_SS 0x08000000 110 #define CPUID_HTT 0x10000000 111 #define CPUID_TM 0x20000000 112 #define CPUID_B30 0x40000000 113 #define CPUID_PBE 0x80000000 114 115 #define CPUID2_SSE3 0x00000001 116 #define CPUID2_MON 0x00000008 117 #define CPUID2_DS_CPL 0x00000010 118 #define CPUID2_EST 0x00000080 119 #define CPUID2_TM2 0x00000100 120 #define CPUID2_CNTXID 0x00000400 121 #define CPUID2_CX16 0x00002000 122 123 /* 124 * Important bits in the AMD extended cpuid flags 125 */ 126 #define AMDID_SYSCALL 0x00000800 127 #define AMDID_MP 0x00080000 128 #define AMDID_NX 0x00100000 129 #define AMDID_LM 0x20000000 130 131 /* 132 * CPUID instruction 1 ebx info 133 */ 134 #define CPUID_BRAND_INDEX 0x000000ff 135 #define CPUID_CLFUSH_SIZE 0x0000ff00 136 #define CPUID_HTT_CORES 0x00ff0000 137 #define CPUID_LOCAL_APIC_ID 0xff000000 138 139 /* 140 * Model-specific registers for the i386 family 141 */ 142 #define MSR_P5_MC_ADDR 0x000 143 #define MSR_P5_MC_TYPE 0x001 144 #define MSR_TSC 0x010 145 #define MSR_P5_CESR 0x011 146 #define MSR_P5_CTR0 0x012 147 #define MSR_P5_CTR1 0x013 148 #define MSR_IA32_PLATFORM_ID 0x017 149 #define MSR_APICBASE 0x01b 150 #define MSR_EBL_CR_POWERON 0x02a 151 #define MSR_TEST_CTL 0x033 152 #define MSR_BIOS_UPDT_TRIG 0x079 153 #define MSR_BBL_CR_D0 0x088 154 #define MSR_BBL_CR_D1 0x089 155 #define MSR_BBL_CR_D2 0x08a 156 #define MSR_BIOS_SIGN 0x08b 157 #define MSR_PERFCTR0 0x0c1 158 #define MSR_PERFCTR1 0x0c2 159 #define MSR_MTRRcap 0x0fe 160 #define MSR_BBL_CR_ADDR 0x116 161 #define MSR_BBL_CR_DECC 0x118 162 #define MSR_BBL_CR_CTL 0x119 163 #define MSR_BBL_CR_TRIG 0x11a 164 #define MSR_BBL_CR_BUSY 0x11b 165 #define MSR_BBL_CR_CTL3 0x11e 166 #define MSR_SYSENTER_CS_MSR 0x174 167 #define MSR_SYSENTER_ESP_MSR 0x175 168 #define MSR_SYSENTER_EIP_MSR 0x176 169 #define MSR_MCG_CAP 0x179 170 #define MSR_MCG_STATUS 0x17a 171 #define MSR_MCG_CTL 0x17b 172 #define MSR_EVNTSEL0 0x186 173 #define MSR_EVNTSEL1 0x187 174 #define MSR_THERM_CONTROL 0x19a 175 #define MSR_THERM_INTERRUPT 0x19b 176 #define MSR_THERM_STATUS 0x19c 177 #define MSR_DEBUGCTLMSR 0x1d9 178 #define MSR_LASTBRANCHFROMIP 0x1db 179 #define MSR_LASTBRANCHTOIP 0x1dc 180 #define MSR_LASTINTFROMIP 0x1dd 181 #define MSR_LASTINTTOIP 0x1de 182 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0 183 #define MSR_MTRRVarBase 0x200 184 #define MSR_MTRR64kBase 0x250 185 #define MSR_MTRR16kBase 0x258 186 #define MSR_MTRR4kBase 0x268 187 #define MSR_PAT 0x277 188 #define MSR_MTRRdefType 0x2ff 189 #define MSR_MC0_CTL 0x400 190 #define MSR_MC0_STATUS 0x401 191 #define MSR_MC0_ADDR 0x402 192 #define MSR_MC0_MISC 0x403 193 #define MSR_MC1_CTL 0x404 194 #define MSR_MC1_STATUS 0x405 195 #define MSR_MC1_ADDR 0x406 196 #define MSR_MC1_MISC 0x407 197 #define MSR_MC2_CTL 0x408 198 #define MSR_MC2_STATUS 0x409 199 #define MSR_MC2_ADDR 0x40a 200 #define MSR_MC2_MISC 0x40b 201 #define MSR_MC4_CTL 0x40c 202 #define MSR_MC4_STATUS 0x40d 203 #define MSR_MC4_ADDR 0x40e 204 #define MSR_MC4_MISC 0x40f 205 #define MSR_MC3_CTL 0x410 206 #define MSR_MC3_STATUS 0x411 207 #define MSR_MC3_ADDR 0x412 208 #define MSR_MC3_MISC 0x413 209 210 /* 211 * Constants related to MSR's. 212 */ 213 #define APICBASE_RESERVED 0x000006ff 214 #define APICBASE_BSP 0x00000100 215 #define APICBASE_ENABLED 0x00000800 216 #define APICBASE_ADDRESS 0xfffff000 217 218 /* 219 * Constants related to MTRRs 220 */ 221 #define MTRR_N64K 8 /* numbers of fixed-size entries */ 222 #define MTRR_N16K 16 223 #define MTRR_N4K 64 224 225 /* Performance Control Register (5x86 only). */ 226 #define PCR0 0x20 227 #define PCR0_RSTK 0x01 /* Enables return stack */ 228 #define PCR0_BTB 0x02 /* Enables branch target buffer */ 229 #define PCR0_LOOP 0x04 /* Enables loop */ 230 #define PCR0_AIS 0x08 /* Enables all instrcutions stalled to 231 serialize pipe. */ 232 #define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */ 233 #define PCR0_BTBRT 0x40 /* Enables BTB test register. */ 234 #define PCR0_LSSER 0x80 /* Disable reorder */ 235 236 /* Device Identification Registers */ 237 #define DIR0 0xfe 238 #define DIR1 0xff 239 240 /* 241 * The following four 3-byte registers control the non-cacheable regions. 242 * These registers must be written as three separate bytes. 243 * 244 * NCRx+0: A31-A24 of starting address 245 * NCRx+1: A23-A16 of starting address 246 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 247 * 248 * The non-cacheable region's starting address must be aligned to the 249 * size indicated by the NCR_SIZE_xx field. 250 */ 251 #define NCR1 0xc4 252 #define NCR2 0xc7 253 #define NCR3 0xca 254 #define NCR4 0xcd 255 256 #define NCR_SIZE_0K 0 257 #define NCR_SIZE_4K 1 258 #define NCR_SIZE_8K 2 259 #define NCR_SIZE_16K 3 260 #define NCR_SIZE_32K 4 261 #define NCR_SIZE_64K 5 262 #define NCR_SIZE_128K 6 263 #define NCR_SIZE_256K 7 264 #define NCR_SIZE_512K 8 265 #define NCR_SIZE_1M 9 266 #define NCR_SIZE_2M 10 267 #define NCR_SIZE_4M 11 268 #define NCR_SIZE_8M 12 269 #define NCR_SIZE_16M 13 270 #define NCR_SIZE_32M 14 271 #define NCR_SIZE_4G 15 272 273 /* 274 * The address region registers are used to specify the location and 275 * size for the eight address regions. 276 * 277 * ARRx + 0: A31-A24 of start address 278 * ARRx + 1: A23-A16 of start address 279 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx 280 */ 281 #define ARR0 0xc4 282 #define ARR1 0xc7 283 #define ARR2 0xca 284 #define ARR3 0xcd 285 #define ARR4 0xd0 286 #define ARR5 0xd3 287 #define ARR6 0xd6 288 #define ARR7 0xd9 289 290 #define ARR_SIZE_0K 0 291 #define ARR_SIZE_4K 1 292 #define ARR_SIZE_8K 2 293 #define ARR_SIZE_16K 3 294 #define ARR_SIZE_32K 4 295 #define ARR_SIZE_64K 5 296 #define ARR_SIZE_128K 6 297 #define ARR_SIZE_256K 7 298 #define ARR_SIZE_512K 8 299 #define ARR_SIZE_1M 9 300 #define ARR_SIZE_2M 10 301 #define ARR_SIZE_4M 11 302 #define ARR_SIZE_8M 12 303 #define ARR_SIZE_16M 13 304 #define ARR_SIZE_32M 14 305 #define ARR_SIZE_4G 15 306 307 /* 308 * The region control registers specify the attributes associated with 309 * the ARRx addres regions. 310 */ 311 #define RCR0 0xdc 312 #define RCR1 0xdd 313 #define RCR2 0xde 314 #define RCR3 0xdf 315 #define RCR4 0xe0 316 #define RCR5 0xe1 317 #define RCR6 0xe2 318 #define RCR7 0xe3 319 320 #define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */ 321 #define RCR_RCE 0x01 /* Enables caching for ARR7. */ 322 #define RCR_WWO 0x02 /* Weak write ordering. */ 323 #define RCR_WL 0x04 /* Weak locking. */ 324 #define RCR_WG 0x08 /* Write gathering. */ 325 #define RCR_WT 0x10 /* Write-through. */ 326 #define RCR_NLB 0x20 /* LBA# pin is not asserted. */ 327 328 /* AMD Write Allocate Top-Of-Memory and Control Register */ 329 #define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */ 330 #define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */ 331 #define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */ 332 333 /* X86-64 MSR's */ 334 #define MSR_EFER 0xc0000080 /* extended features */ 335 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target/cs/ss */ 336 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target rip */ 337 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target rip */ 338 #define MSR_SF_MASK 0xc0000084 /* syscall flags mask */ 339 #define MSR_FSBASE 0xc0000100 /* base address of the %fs "segment" */ 340 #define MSR_GSBASE 0xc0000101 /* base address of the %gs "segment" */ 341 #define MSR_KGSBASE 0xc0000102 /* base address of the kernel %gs */ 342 #define MSR_PERFEVSEL0 0xc0010000 343 #define MSR_PERFEVSEL1 0xc0010001 344 #define MSR_PERFEVSEL2 0xc0010002 345 #define MSR_PERFEVSEL3 0xc0010003 346 #undef MSR_PERFCTR0 347 #undef MSR_PERFCTR1 348 #define MSR_PERFCTR0 0xc0010004 349 #define MSR_PERFCTR1 0xc0010005 350 #define MSR_PERFCTR2 0xc0010006 351 #define MSR_PERFCTR3 0xc0010007 352 #define MSR_SYSCFG 0xc0010010 353 #define MSR_IORRBASE0 0xc0010016 354 #define MSR_IORRMASK0 0xc0010017 355 #define MSR_IORRBASE1 0xc0010018 356 #define MSR_IORRMASK1 0xc0010019 357 #define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */ 358 #define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */ 359 360 #endif /* !_MACHINE_SPECIALREG_H_ */ 361