xref: /freebsd/sys/amd64/include/specialreg.h (revision acd3428b7d3e94cef0e1881c868cb4b131d4ff41)
1 /*-
2  * Copyright (c) 1991 The Regents of the University of California.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  * 4. Neither the name of the University nor the names of its contributors
14  *    may be used to endorse or promote products derived from this software
15  *    without specific prior written permission.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27  * SUCH DAMAGE.
28  *
29  *	from: @(#)specialreg.h	7.1 (Berkeley) 5/9/91
30  * $FreeBSD$
31  */
32 
33 #ifndef _MACHINE_SPECIALREG_H_
34 #define	_MACHINE_SPECIALREG_H_
35 
36 /*
37  * Bits in 386 special registers:
38  */
39 #define	CR0_PE	0x00000001	/* Protected mode Enable */
40 #define	CR0_MP	0x00000002	/* "Math" (fpu) Present */
41 #define	CR0_EM	0x00000004	/* EMulate FPU instructions. (trap ESC only) */
42 #define	CR0_TS	0x00000008	/* Task Switched (if MP, trap ESC and WAIT) */
43 #define	CR0_PG	0x80000000	/* PaGing enable */
44 
45 /*
46  * Bits in 486 special registers:
47  */
48 #define	CR0_NE	0x00000020	/* Numeric Error enable (EX16 vs IRQ13) */
49 #define	CR0_WP	0x00010000	/* Write Protect (honor page protect in
50 							   all modes) */
51 #define	CR0_AM	0x00040000	/* Alignment Mask (set to enable AC flag) */
52 #define	CR0_NW  0x20000000	/* Not Write-through */
53 #define	CR0_CD  0x40000000	/* Cache Disable */
54 
55 /*
56  * Bits in PPro special registers
57  */
58 #define	CR4_VME	0x00000001	/* Virtual 8086 mode extensions */
59 #define	CR4_PVI	0x00000002	/* Protected-mode virtual interrupts */
60 #define	CR4_TSD	0x00000004	/* Time stamp disable */
61 #define	CR4_DE	0x00000008	/* Debugging extensions */
62 #define	CR4_PSE	0x00000010	/* Page size extensions */
63 #define	CR4_PAE	0x00000020	/* Physical address extension */
64 #define	CR4_MCE	0x00000040	/* Machine check enable */
65 #define	CR4_PGE	0x00000080	/* Page global enable */
66 #define	CR4_PCE	0x00000100	/* Performance monitoring counter enable */
67 #define	CR4_FXSR 0x00000200	/* Fast FPU save/restore used by OS */
68 #define	CR4_XMM	0x00000400	/* enable SIMD/MMX2 to use except 16 */
69 
70 /*
71  * Bits in AMD64 special registers.  EFER is 64 bits wide.
72  */
73 #define	EFER_SCE 0x000000001	/* System Call Extensions (R/W) */
74 #define	EFER_LME 0x000000100	/* Long mode enable (R/W) */
75 #define	EFER_LMA 0x000000400	/* Long mode active (R) */
76 #define	EFER_NXE 0x000000800	/* PTE No-Execute bit enable (R/W) */
77 
78 /*
79  * CPUID instruction features register
80  */
81 #define	CPUID_FPU	0x00000001
82 #define	CPUID_VME	0x00000002
83 #define	CPUID_DE	0x00000004
84 #define	CPUID_PSE	0x00000008
85 #define	CPUID_TSC	0x00000010
86 #define	CPUID_MSR	0x00000020
87 #define	CPUID_PAE	0x00000040
88 #define	CPUID_MCE	0x00000080
89 #define	CPUID_CX8	0x00000100
90 #define	CPUID_APIC	0x00000200
91 #define	CPUID_B10	0x00000400
92 #define	CPUID_SEP	0x00000800
93 #define	CPUID_MTRR	0x00001000
94 #define	CPUID_PGE	0x00002000
95 #define	CPUID_MCA	0x00004000
96 #define	CPUID_CMOV	0x00008000
97 #define	CPUID_PAT	0x00010000
98 #define	CPUID_PSE36	0x00020000
99 #define	CPUID_PSN	0x00040000
100 #define	CPUID_CLFSH	0x00080000
101 #define	CPUID_B20	0x00100000
102 #define	CPUID_DS	0x00200000
103 #define	CPUID_ACPI	0x00400000
104 #define	CPUID_MMX	0x00800000
105 #define	CPUID_FXSR	0x01000000
106 #define	CPUID_SSE	0x02000000
107 #define	CPUID_XMM	0x02000000
108 #define	CPUID_SSE2	0x04000000
109 #define	CPUID_SS	0x08000000
110 #define	CPUID_HTT	0x10000000
111 #define	CPUID_TM	0x20000000
112 #define	CPUID_IA64	0x40000000
113 #define	CPUID_PBE	0x80000000
114 
115 #define CPUID2_SSE3	0x00000001
116 #define CPUID2_MON	0x00000008
117 #define CPUID2_DS_CPL	0x00000010
118 #define CPUID2_VMX	0x00000020
119 #define CPUID2_EST	0x00000080
120 #define CPUID2_TM2	0x00000100
121 #define CPUID2_CNTXID	0x00000400
122 #define CPUID2_CX16	0x00002000
123 #define CPUID2_XTPR	0x00004000
124 
125 /*
126  * Important bits in the AMD extended cpuid flags
127  */
128 #define AMDID_SYSCALL	0x00000800
129 #define AMDID_MP	0x00080000
130 #define AMDID_NX	0x00100000
131 #define AMDID_EXT_MMX	0x00400000
132 #define AMDID_FFXSR	0x01000000
133 #define AMDID_RDTSCP	0x08000000
134 #define AMDID_LM	0x20000000
135 #define AMDID_EXT_3DNOW	0x40000000
136 #define AMDID_3DNOW	0x80000000
137 
138 #define AMDID2_LAHF	0x00000001
139 #define AMDID2_CMP	0x00000002
140 #define AMDID2_SVM	0x00000004
141 #define AMDID2_EXT_APIC	0x00000008
142 #define AMDID2_CR8	0x00000010
143 
144 /*
145  * CPUID instruction 1 ebx info
146  */
147 #define	CPUID_BRAND_INDEX	0x000000ff
148 #define	CPUID_CLFUSH_SIZE	0x0000ff00
149 #define	CPUID_HTT_CORES		0x00ff0000
150 #define	CPUID_LOCAL_APIC_ID	0xff000000
151 
152 /*
153  * AMD extended function 8000_0008h ecx info
154  */
155 #define AMDID_CMP_CORES		0x000000ff
156 
157 /*
158  * Model-specific registers for the i386 family
159  */
160 #define MSR_P5_MC_ADDR		0x000
161 #define MSR_P5_MC_TYPE		0x001
162 #define MSR_TSC			0x010
163 #define	MSR_P5_CESR		0x011
164 #define	MSR_P5_CTR0		0x012
165 #define	MSR_P5_CTR1		0x013
166 #define	MSR_IA32_PLATFORM_ID	0x017
167 #define MSR_APICBASE		0x01b
168 #define MSR_EBL_CR_POWERON	0x02a
169 #define	MSR_TEST_CTL		0x033
170 #define MSR_BIOS_UPDT_TRIG	0x079
171 #define	MSR_BBL_CR_D0		0x088
172 #define	MSR_BBL_CR_D1		0x089
173 #define	MSR_BBL_CR_D2		0x08a
174 #define MSR_BIOS_SIGN		0x08b
175 #define MSR_PERFCTR0		0x0c1
176 #define MSR_PERFCTR1		0x0c2
177 #define MSR_MTRRcap		0x0fe
178 #define	MSR_BBL_CR_ADDR		0x116
179 #define	MSR_BBL_CR_DECC		0x118
180 #define	MSR_BBL_CR_CTL		0x119
181 #define	MSR_BBL_CR_TRIG		0x11a
182 #define	MSR_BBL_CR_BUSY		0x11b
183 #define	MSR_BBL_CR_CTL3		0x11e
184 #define	MSR_SYSENTER_CS_MSR	0x174
185 #define	MSR_SYSENTER_ESP_MSR	0x175
186 #define	MSR_SYSENTER_EIP_MSR	0x176
187 #define MSR_MCG_CAP		0x179
188 #define MSR_MCG_STATUS		0x17a
189 #define MSR_MCG_CTL		0x17b
190 #define MSR_EVNTSEL0		0x186
191 #define MSR_EVNTSEL1		0x187
192 #define MSR_THERM_CONTROL	0x19a
193 #define MSR_THERM_INTERRUPT	0x19b
194 #define MSR_THERM_STATUS	0x19c
195 #define	MSR_IA32_MISC_ENABLE	0x1a0
196 #define MSR_DEBUGCTLMSR		0x1d9
197 #define MSR_LASTBRANCHFROMIP	0x1db
198 #define MSR_LASTBRANCHTOIP	0x1dc
199 #define MSR_LASTINTFROMIP	0x1dd
200 #define MSR_LASTINTTOIP		0x1de
201 #define MSR_ROB_CR_BKUPTMPDR6	0x1e0
202 #define MSR_MTRRVarBase		0x200
203 #define MSR_MTRR64kBase		0x250
204 #define MSR_MTRR16kBase		0x258
205 #define MSR_MTRR4kBase		0x268
206 #define MSR_PAT			0x277
207 #define MSR_MTRRdefType		0x2ff
208 #define MSR_MC0_CTL		0x400
209 #define MSR_MC0_STATUS		0x401
210 #define MSR_MC0_ADDR		0x402
211 #define MSR_MC0_MISC		0x403
212 #define MSR_MC1_CTL		0x404
213 #define MSR_MC1_STATUS		0x405
214 #define MSR_MC1_ADDR		0x406
215 #define MSR_MC1_MISC		0x407
216 #define MSR_MC2_CTL		0x408
217 #define MSR_MC2_STATUS		0x409
218 #define MSR_MC2_ADDR		0x40a
219 #define MSR_MC2_MISC		0x40b
220 #define MSR_MC3_CTL		0x40c
221 #define MSR_MC3_STATUS		0x40d
222 #define MSR_MC3_ADDR		0x40e
223 #define MSR_MC3_MISC		0x40f
224 #define MSR_MC4_CTL		0x410
225 #define MSR_MC4_STATUS		0x411
226 #define MSR_MC4_ADDR		0x412
227 #define MSR_MC4_MISC		0x413
228 
229 /*
230  * Constants related to MSR's.
231  */
232 #define	APICBASE_RESERVED	0x000006ff
233 #define	APICBASE_BSP		0x00000100
234 #define	APICBASE_ENABLED	0x00000800
235 #define	APICBASE_ADDRESS	0xfffff000
236 
237 /*
238  * PAT modes.
239  */
240 #define	PAT_UNCACHEABLE		0x00
241 #define	PAT_WRITE_COMBINING	0x01
242 #define	PAT_WRITE_THROUGH	0x04
243 #define	PAT_WRITE_PROTECTED	0x05
244 #define	PAT_WRITE_BACK		0x06
245 #define	PAT_UNCACHED		0x07
246 #define	PAT_VALUE(i, m)		((long)(m) << (8 * (i)))
247 #define	PAT_MASK(i)		PAT_VALUE(i, 0xff)
248 
249 /*
250  * Constants related to MTRRs
251  */
252 #define MTRR_N64K		8	/* numbers of fixed-size entries */
253 #define MTRR_N16K		16
254 #define MTRR_N4K		64
255 
256 /* Performance Control Register (5x86 only). */
257 #define	PCR0			0x20
258 #define	PCR0_RSTK		0x01	/* Enables return stack */
259 #define	PCR0_BTB		0x02	/* Enables branch target buffer */
260 #define	PCR0_LOOP		0x04	/* Enables loop */
261 #define	PCR0_AIS		0x08	/* Enables all instrcutions stalled to
262 								   serialize pipe. */
263 #define	PCR0_MLR		0x10	/* Enables reordering of misaligned loads */
264 #define	PCR0_BTBRT		0x40	/* Enables BTB test register. */
265 #define	PCR0_LSSER		0x80	/* Disable reorder */
266 
267 /* Device Identification Registers */
268 #define	DIR0			0xfe
269 #define	DIR1			0xff
270 
271 /*
272  * The following four 3-byte registers control the non-cacheable regions.
273  * These registers must be written as three separate bytes.
274  *
275  * NCRx+0: A31-A24 of starting address
276  * NCRx+1: A23-A16 of starting address
277  * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
278  *
279  * The non-cacheable region's starting address must be aligned to the
280  * size indicated by the NCR_SIZE_xx field.
281  */
282 #define	NCR1	0xc4
283 #define	NCR2	0xc7
284 #define	NCR3	0xca
285 #define	NCR4	0xcd
286 
287 #define	NCR_SIZE_0K	0
288 #define	NCR_SIZE_4K	1
289 #define	NCR_SIZE_8K	2
290 #define	NCR_SIZE_16K	3
291 #define	NCR_SIZE_32K	4
292 #define	NCR_SIZE_64K	5
293 #define	NCR_SIZE_128K	6
294 #define	NCR_SIZE_256K	7
295 #define	NCR_SIZE_512K	8
296 #define	NCR_SIZE_1M	9
297 #define	NCR_SIZE_2M	10
298 #define	NCR_SIZE_4M	11
299 #define	NCR_SIZE_8M	12
300 #define	NCR_SIZE_16M	13
301 #define	NCR_SIZE_32M	14
302 #define	NCR_SIZE_4G	15
303 
304 /*
305  * The address region registers are used to specify the location and
306  * size for the eight address regions.
307  *
308  * ARRx + 0: A31-A24 of start address
309  * ARRx + 1: A23-A16 of start address
310  * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx
311  */
312 #define	ARR0	0xc4
313 #define	ARR1	0xc7
314 #define	ARR2	0xca
315 #define	ARR3	0xcd
316 #define	ARR4	0xd0
317 #define	ARR5	0xd3
318 #define	ARR6	0xd6
319 #define	ARR7	0xd9
320 
321 #define	ARR_SIZE_0K		0
322 #define	ARR_SIZE_4K		1
323 #define	ARR_SIZE_8K		2
324 #define	ARR_SIZE_16K	3
325 #define	ARR_SIZE_32K	4
326 #define	ARR_SIZE_64K	5
327 #define	ARR_SIZE_128K	6
328 #define	ARR_SIZE_256K	7
329 #define	ARR_SIZE_512K	8
330 #define	ARR_SIZE_1M		9
331 #define	ARR_SIZE_2M		10
332 #define	ARR_SIZE_4M		11
333 #define	ARR_SIZE_8M		12
334 #define	ARR_SIZE_16M	13
335 #define	ARR_SIZE_32M	14
336 #define	ARR_SIZE_4G		15
337 
338 /*
339  * The region control registers specify the attributes associated with
340  * the ARRx addres regions.
341  */
342 #define	RCR0	0xdc
343 #define	RCR1	0xdd
344 #define	RCR2	0xde
345 #define	RCR3	0xdf
346 #define	RCR4	0xe0
347 #define	RCR5	0xe1
348 #define	RCR6	0xe2
349 #define	RCR7	0xe3
350 
351 #define RCR_RCD	0x01	/* Disables caching for ARRx (x = 0-6). */
352 #define RCR_RCE	0x01	/* Enables caching for ARR7. */
353 #define RCR_WWO	0x02	/* Weak write ordering. */
354 #define	RCR_WL	0x04	/* Weak locking. */
355 #define RCR_WG	0x08	/* Write gathering. */
356 #define	RCR_WT	0x10	/* Write-through. */
357 #define	RCR_NLB	0x20	/* LBA# pin is not asserted. */
358 
359 /* AMD Write Allocate Top-Of-Memory and Control Register */
360 #define	AMD_WT_ALLOC_TME	0x40000	/* top-of-memory enable */
361 #define	AMD_WT_ALLOC_PRE	0x20000	/* programmable range enable */
362 #define	AMD_WT_ALLOC_FRE	0x10000	/* fixed (A0000-FFFFF) range enable */
363 
364 /* AMD64 MSR's */
365 #define	MSR_EFER	0xc0000080	/* extended features */
366 #define	MSR_STAR	0xc0000081	/* legacy mode SYSCALL target/cs/ss */
367 #define	MSR_LSTAR	0xc0000082	/* long mode SYSCALL target rip */
368 #define	MSR_CSTAR	0xc0000083	/* compat mode SYSCALL target rip */
369 #define	MSR_SF_MASK	0xc0000084	/* syscall flags mask */
370 #define	MSR_FSBASE	0xc0000100	/* base address of the %fs "segment" */
371 #define	MSR_GSBASE	0xc0000101	/* base address of the %gs "segment" */
372 #define	MSR_KGSBASE	0xc0000102	/* base address of the kernel %gs */
373 #define	MSR_PERFEVSEL0	0xc0010000
374 #define	MSR_PERFEVSEL1	0xc0010001
375 #define	MSR_PERFEVSEL2	0xc0010002
376 #define	MSR_PERFEVSEL3	0xc0010003
377 #undef MSR_PERFCTR0
378 #undef MSR_PERFCTR1
379 #define	MSR_PERFCTR0	0xc0010004
380 #define	MSR_PERFCTR1	0xc0010005
381 #define	MSR_PERFCTR2	0xc0010006
382 #define	MSR_PERFCTR3	0xc0010007
383 #define	MSR_SYSCFG	0xc0010010
384 #define	MSR_IORRBASE0	0xc0010016
385 #define	MSR_IORRMASK0	0xc0010017
386 #define	MSR_IORRBASE1	0xc0010018
387 #define	MSR_IORRMASK1	0xc0010019
388 #define	MSR_TOP_MEM	0xc001001a	/* boundary for ram below 4G */
389 #define	MSR_TOP_MEM2	0xc001001d	/* boundary for ram above 4G */
390 
391 #endif /* !_MACHINE_SPECIALREG_H_ */
392