1 /*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 4. Neither the name of the University nor the names of its contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 30 * $FreeBSD$ 31 */ 32 33 #ifndef _MACHINE_SPECIALREG_H_ 34 #define _MACHINE_SPECIALREG_H_ 35 36 /* 37 * Bits in 386 special registers: 38 */ 39 #define CR0_PE 0x00000001 /* Protected mode Enable */ 40 #define CR0_MP 0x00000002 /* "Math" (fpu) Present */ 41 #define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */ 42 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 43 #define CR0_PG 0x80000000 /* PaGing enable */ 44 45 /* 46 * Bits in 486 special registers: 47 */ 48 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 49 #define CR0_WP 0x00010000 /* Write Protect (honor page protect in 50 all modes) */ 51 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 52 #define CR0_NW 0x20000000 /* Not Write-through */ 53 #define CR0_CD 0x40000000 /* Cache Disable */ 54 55 /* 56 * Bits in PPro special registers 57 */ 58 #define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */ 59 #define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */ 60 #define CR4_TSD 0x00000004 /* Time stamp disable */ 61 #define CR4_DE 0x00000008 /* Debugging extensions */ 62 #define CR4_PSE 0x00000010 /* Page size extensions */ 63 #define CR4_PAE 0x00000020 /* Physical address extension */ 64 #define CR4_MCE 0x00000040 /* Machine check enable */ 65 #define CR4_PGE 0x00000080 /* Page global enable */ 66 #define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ 67 #define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */ 68 #define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */ 69 70 /* 71 * Bits in AMD64 special registers. EFER is 64 bits wide. 72 */ 73 #define EFER_SCE 0x000000001 /* System Call Extensions (R/W) */ 74 #define EFER_LME 0x000000100 /* Long mode enable (R/W) */ 75 #define EFER_LMA 0x000000400 /* Long mode active (R) */ 76 #define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */ 77 78 /* 79 * CPUID instruction features register 80 */ 81 #define CPUID_FPU 0x00000001 82 #define CPUID_VME 0x00000002 83 #define CPUID_DE 0x00000004 84 #define CPUID_PSE 0x00000008 85 #define CPUID_TSC 0x00000010 86 #define CPUID_MSR 0x00000020 87 #define CPUID_PAE 0x00000040 88 #define CPUID_MCE 0x00000080 89 #define CPUID_CX8 0x00000100 90 #define CPUID_APIC 0x00000200 91 #define CPUID_B10 0x00000400 92 #define CPUID_SEP 0x00000800 93 #define CPUID_MTRR 0x00001000 94 #define CPUID_PGE 0x00002000 95 #define CPUID_MCA 0x00004000 96 #define CPUID_CMOV 0x00008000 97 #define CPUID_PAT 0x00010000 98 #define CPUID_PSE36 0x00020000 99 #define CPUID_PSN 0x00040000 100 #define CPUID_CLFSH 0x00080000 101 #define CPUID_B20 0x00100000 102 #define CPUID_DS 0x00200000 103 #define CPUID_ACPI 0x00400000 104 #define CPUID_MMX 0x00800000 105 #define CPUID_FXSR 0x01000000 106 #define CPUID_SSE 0x02000000 107 #define CPUID_XMM 0x02000000 108 #define CPUID_SSE2 0x04000000 109 #define CPUID_SS 0x08000000 110 #define CPUID_HTT 0x10000000 111 #define CPUID_TM 0x20000000 112 #define CPUID_IA64 0x40000000 113 #define CPUID_PBE 0x80000000 114 115 #define CPUID2_SSE3 0x00000001 116 #define CPUID2_PCLMULQDQ 0x00000002 117 #define CPUID2_DTES64 0x00000004 118 #define CPUID2_MON 0x00000008 119 #define CPUID2_DS_CPL 0x00000010 120 #define CPUID2_VMX 0x00000020 121 #define CPUID2_SMX 0x00000040 122 #define CPUID2_EST 0x00000080 123 #define CPUID2_TM2 0x00000100 124 #define CPUID2_SSSE3 0x00000200 125 #define CPUID2_CNXTID 0x00000400 126 #define CPUID2_CX16 0x00002000 127 #define CPUID2_XTPR 0x00004000 128 #define CPUID2_PDCM 0x00008000 129 #define CPUID2_PCID 0x00020000 130 #define CPUID2_DCA 0x00040000 131 #define CPUID2_SSE41 0x00080000 132 #define CPUID2_SSE42 0x00100000 133 #define CPUID2_X2APIC 0x00200000 134 #define CPUID2_MOVBE 0x00400000 135 #define CPUID2_POPCNT 0x00800000 136 #define CPUID2_AESNI 0x02000000 137 138 /* 139 * Important bits in the AMD extended cpuid flags 140 */ 141 #define AMDID_SYSCALL 0x00000800 142 #define AMDID_MP 0x00080000 143 #define AMDID_NX 0x00100000 144 #define AMDID_EXT_MMX 0x00400000 145 #define AMDID_FFXSR 0x01000000 146 #define AMDID_PAGE1GB 0x04000000 147 #define AMDID_RDTSCP 0x08000000 148 #define AMDID_LM 0x20000000 149 #define AMDID_EXT_3DNOW 0x40000000 150 #define AMDID_3DNOW 0x80000000 151 152 #define AMDID2_LAHF 0x00000001 153 #define AMDID2_CMP 0x00000002 154 #define AMDID2_SVM 0x00000004 155 #define AMDID2_EXT_APIC 0x00000008 156 #define AMDID2_CR8 0x00000010 157 #define AMDID2_ABM 0x00000020 158 #define AMDID2_SSE4A 0x00000040 159 #define AMDID2_MAS 0x00000080 160 #define AMDID2_PREFETCH 0x00000100 161 #define AMDID2_OSVW 0x00000200 162 #define AMDID2_IBS 0x00000400 163 #define AMDID2_SSE5 0x00000800 164 #define AMDID2_SKINIT 0x00001000 165 #define AMDID2_WDT 0x00002000 166 167 /* 168 * CPUID instruction 1 eax info 169 */ 170 #define CPUID_STEPPING 0x0000000f 171 #define CPUID_MODEL 0x000000f0 172 #define CPUID_FAMILY 0x00000f00 173 #define CPUID_EXT_MODEL 0x000f0000 174 #define CPUID_EXT_FAMILY 0x0ff00000 175 #define CPUID_TO_MODEL(id) \ 176 ((((id) & CPUID_MODEL) >> 4) | \ 177 (((id) & CPUID_EXT_MODEL) >> 12)) 178 #define CPUID_TO_FAMILY(id) \ 179 ((((id) & CPUID_FAMILY) >> 8) + \ 180 (((id) & CPUID_EXT_FAMILY) >> 20)) 181 182 /* 183 * CPUID instruction 1 ebx info 184 */ 185 #define CPUID_BRAND_INDEX 0x000000ff 186 #define CPUID_CLFUSH_SIZE 0x0000ff00 187 #define CPUID_HTT_CORES 0x00ff0000 188 #define CPUID_LOCAL_APIC_ID 0xff000000 189 190 /* 191 * CPUID instruction 0xb ebx info. 192 */ 193 #define CPUID_TYPE_INVAL 0 194 #define CPUID_TYPE_SMT 1 195 #define CPUID_TYPE_CORE 2 196 197 /* 198 * AMD extended function 8000_0007h edx info 199 */ 200 #define AMDPM_TS 0x00000001 201 #define AMDPM_FID 0x00000002 202 #define AMDPM_VID 0x00000004 203 #define AMDPM_TTP 0x00000008 204 #define AMDPM_TM 0x00000010 205 #define AMDPM_STC 0x00000020 206 #define AMDPM_100MHZ_STEPS 0x00000040 207 #define AMDPM_HW_PSTATE 0x00000080 208 #define AMDPM_TSC_INVARIANT 0x00000100 209 #define AMDPM_CPB 0x00000200 210 211 /* 212 * AMD extended function 8000_0008h ecx info 213 */ 214 #define AMDID_CMP_CORES 0x000000ff 215 216 /* 217 * CPUID manufacturers identifiers 218 */ 219 #define AMD_VENDOR_ID "AuthenticAMD" 220 #define CENTAUR_VENDOR_ID "CentaurHauls" 221 #define INTEL_VENDOR_ID "GenuineIntel" 222 223 /* 224 * Model-specific registers for the i386 family 225 */ 226 #define MSR_P5_MC_ADDR 0x000 227 #define MSR_P5_MC_TYPE 0x001 228 #define MSR_TSC 0x010 229 #define MSR_P5_CESR 0x011 230 #define MSR_P5_CTR0 0x012 231 #define MSR_P5_CTR1 0x013 232 #define MSR_IA32_PLATFORM_ID 0x017 233 #define MSR_APICBASE 0x01b 234 #define MSR_EBL_CR_POWERON 0x02a 235 #define MSR_TEST_CTL 0x033 236 #define MSR_BIOS_UPDT_TRIG 0x079 237 #define MSR_BBL_CR_D0 0x088 238 #define MSR_BBL_CR_D1 0x089 239 #define MSR_BBL_CR_D2 0x08a 240 #define MSR_BIOS_SIGN 0x08b 241 #define MSR_PERFCTR0 0x0c1 242 #define MSR_PERFCTR1 0x0c2 243 #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */ 244 #define MSR_MTRRcap 0x0fe 245 #define MSR_BBL_CR_ADDR 0x116 246 #define MSR_BBL_CR_DECC 0x118 247 #define MSR_BBL_CR_CTL 0x119 248 #define MSR_BBL_CR_TRIG 0x11a 249 #define MSR_BBL_CR_BUSY 0x11b 250 #define MSR_BBL_CR_CTL3 0x11e 251 #define MSR_SYSENTER_CS_MSR 0x174 252 #define MSR_SYSENTER_ESP_MSR 0x175 253 #define MSR_SYSENTER_EIP_MSR 0x176 254 #define MSR_MCG_CAP 0x179 255 #define MSR_MCG_STATUS 0x17a 256 #define MSR_MCG_CTL 0x17b 257 #define MSR_EVNTSEL0 0x186 258 #define MSR_EVNTSEL1 0x187 259 #define MSR_THERM_CONTROL 0x19a 260 #define MSR_THERM_INTERRUPT 0x19b 261 #define MSR_THERM_STATUS 0x19c 262 #define MSR_IA32_MISC_ENABLE 0x1a0 263 #define MSR_IA32_TEMPERATURE_TARGET 0x1a2 264 #define MSR_DEBUGCTLMSR 0x1d9 265 #define MSR_LASTBRANCHFROMIP 0x1db 266 #define MSR_LASTBRANCHTOIP 0x1dc 267 #define MSR_LASTINTFROMIP 0x1dd 268 #define MSR_LASTINTTOIP 0x1de 269 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0 270 #define MSR_MTRRVarBase 0x200 271 #define MSR_MTRR64kBase 0x250 272 #define MSR_MTRR16kBase 0x258 273 #define MSR_MTRR4kBase 0x268 274 #define MSR_PAT 0x277 275 #define MSR_MC0_CTL2 0x280 276 #define MSR_MTRRdefType 0x2ff 277 #define MSR_MC0_CTL 0x400 278 #define MSR_MC0_STATUS 0x401 279 #define MSR_MC0_ADDR 0x402 280 #define MSR_MC0_MISC 0x403 281 #define MSR_MC1_CTL 0x404 282 #define MSR_MC1_STATUS 0x405 283 #define MSR_MC1_ADDR 0x406 284 #define MSR_MC1_MISC 0x407 285 #define MSR_MC2_CTL 0x408 286 #define MSR_MC2_STATUS 0x409 287 #define MSR_MC2_ADDR 0x40a 288 #define MSR_MC2_MISC 0x40b 289 #define MSR_MC3_CTL 0x40c 290 #define MSR_MC3_STATUS 0x40d 291 #define MSR_MC3_ADDR 0x40e 292 #define MSR_MC3_MISC 0x40f 293 #define MSR_MC4_CTL 0x410 294 #define MSR_MC4_STATUS 0x411 295 #define MSR_MC4_ADDR 0x412 296 #define MSR_MC4_MISC 0x413 297 298 /* 299 * Constants related to MSR's. 300 */ 301 #define APICBASE_RESERVED 0x000006ff 302 #define APICBASE_BSP 0x00000100 303 #define APICBASE_ENABLED 0x00000800 304 #define APICBASE_ADDRESS 0xfffff000 305 306 /* 307 * PAT modes. 308 */ 309 #define PAT_UNCACHEABLE 0x00 310 #define PAT_WRITE_COMBINING 0x01 311 #define PAT_WRITE_THROUGH 0x04 312 #define PAT_WRITE_PROTECTED 0x05 313 #define PAT_WRITE_BACK 0x06 314 #define PAT_UNCACHED 0x07 315 #define PAT_VALUE(i, m) ((long)(m) << (8 * (i))) 316 #define PAT_MASK(i) PAT_VALUE(i, 0xff) 317 318 /* 319 * Constants related to MTRRs 320 */ 321 #define MTRR_UNCACHEABLE 0x00 322 #define MTRR_WRITE_COMBINING 0x01 323 #define MTRR_WRITE_THROUGH 0x04 324 #define MTRR_WRITE_PROTECTED 0x05 325 #define MTRR_WRITE_BACK 0x06 326 #define MTRR_N64K 8 /* numbers of fixed-size entries */ 327 #define MTRR_N16K 16 328 #define MTRR_N4K 64 329 #define MTRR_CAP_WC 0x0000000000000400 330 #define MTRR_CAP_FIXED 0x0000000000000100 331 #define MTRR_CAP_VCNT 0x00000000000000ff 332 #define MTRR_DEF_ENABLE 0x0000000000000800 333 #define MTRR_DEF_FIXED_ENABLE 0x0000000000000400 334 #define MTRR_DEF_TYPE 0x00000000000000ff 335 #define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000 336 #define MTRR_PHYSBASE_TYPE 0x00000000000000ff 337 #define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000 338 #define MTRR_PHYSMASK_VALID 0x0000000000000800 339 340 /* Performance Control Register (5x86 only). */ 341 #define PCR0 0x20 342 #define PCR0_RSTK 0x01 /* Enables return stack */ 343 #define PCR0_BTB 0x02 /* Enables branch target buffer */ 344 #define PCR0_LOOP 0x04 /* Enables loop */ 345 #define PCR0_AIS 0x08 /* Enables all instrcutions stalled to 346 serialize pipe. */ 347 #define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */ 348 #define PCR0_BTBRT 0x40 /* Enables BTB test register. */ 349 #define PCR0_LSSER 0x80 /* Disable reorder */ 350 351 /* Device Identification Registers */ 352 #define DIR0 0xfe 353 #define DIR1 0xff 354 355 /* 356 * Machine Check register constants. 357 */ 358 #define MCG_CAP_COUNT 0x000000ff 359 #define MCG_CAP_CTL_P 0x00000100 360 #define MCG_CAP_EXT_P 0x00000200 361 #define MCG_CAP_CMCI_P 0x00000400 362 #define MCG_CAP_TES_P 0x00000800 363 #define MCG_CAP_EXT_CNT 0x00ff0000 364 #define MCG_CAP_SER_P 0x01000000 365 #define MCG_STATUS_RIPV 0x00000001 366 #define MCG_STATUS_EIPV 0x00000002 367 #define MCG_STATUS_MCIP 0x00000004 368 #define MCG_CTL_ENABLE 0xffffffffffffffff 369 #define MCG_CTL_DISABLE 0x0000000000000000 370 #define MSR_MC_CTL(x) (MSR_MC0_CTL + (x) * 4) 371 #define MSR_MC_STATUS(x) (MSR_MC0_STATUS + (x) * 4) 372 #define MSR_MC_ADDR(x) (MSR_MC0_ADDR + (x) * 4) 373 #define MSR_MC_MISC(x) (MSR_MC0_MISC + (x) * 4) 374 #define MSR_MC_CTL2(x) (MSR_MC0_CTL2 + (x)) /* If MCG_CAP_CMCI_P */ 375 #define MC_STATUS_MCA_ERROR 0x000000000000ffff 376 #define MC_STATUS_MODEL_ERROR 0x00000000ffff0000 377 #define MC_STATUS_OTHER_INFO 0x01ffffff00000000 378 #define MC_STATUS_COR_COUNT 0x001fffc000000000 /* If MCG_CAP_CMCI_P */ 379 #define MC_STATUS_TES_STATUS 0x0060000000000000 /* If MCG_CAP_TES_P */ 380 #define MC_STATUS_AR 0x0080000000000000 /* If MCG_CAP_TES_P */ 381 #define MC_STATUS_S 0x0100000000000000 /* If MCG_CAP_TES_P */ 382 #define MC_STATUS_PCC 0x0200000000000000 383 #define MC_STATUS_ADDRV 0x0400000000000000 384 #define MC_STATUS_MISCV 0x0800000000000000 385 #define MC_STATUS_EN 0x1000000000000000 386 #define MC_STATUS_UC 0x2000000000000000 387 #define MC_STATUS_OVER 0x4000000000000000 388 #define MC_STATUS_VAL 0x8000000000000000 389 #define MC_MISC_RA_LSB 0x000000000000003f /* If MCG_CAP_SER_P */ 390 #define MC_MISC_ADDRESS_MODE 0x00000000000001c0 /* If MCG_CAP_SER_P */ 391 #define MC_CTL2_THRESHOLD 0x0000000000007fff 392 #define MC_CTL2_CMCI_EN 0x0000000040000000 393 394 /* 395 * The following four 3-byte registers control the non-cacheable regions. 396 * These registers must be written as three separate bytes. 397 * 398 * NCRx+0: A31-A24 of starting address 399 * NCRx+1: A23-A16 of starting address 400 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 401 * 402 * The non-cacheable region's starting address must be aligned to the 403 * size indicated by the NCR_SIZE_xx field. 404 */ 405 #define NCR1 0xc4 406 #define NCR2 0xc7 407 #define NCR3 0xca 408 #define NCR4 0xcd 409 410 #define NCR_SIZE_0K 0 411 #define NCR_SIZE_4K 1 412 #define NCR_SIZE_8K 2 413 #define NCR_SIZE_16K 3 414 #define NCR_SIZE_32K 4 415 #define NCR_SIZE_64K 5 416 #define NCR_SIZE_128K 6 417 #define NCR_SIZE_256K 7 418 #define NCR_SIZE_512K 8 419 #define NCR_SIZE_1M 9 420 #define NCR_SIZE_2M 10 421 #define NCR_SIZE_4M 11 422 #define NCR_SIZE_8M 12 423 #define NCR_SIZE_16M 13 424 #define NCR_SIZE_32M 14 425 #define NCR_SIZE_4G 15 426 427 /* 428 * The address region registers are used to specify the location and 429 * size for the eight address regions. 430 * 431 * ARRx + 0: A31-A24 of start address 432 * ARRx + 1: A23-A16 of start address 433 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx 434 */ 435 #define ARR0 0xc4 436 #define ARR1 0xc7 437 #define ARR2 0xca 438 #define ARR3 0xcd 439 #define ARR4 0xd0 440 #define ARR5 0xd3 441 #define ARR6 0xd6 442 #define ARR7 0xd9 443 444 #define ARR_SIZE_0K 0 445 #define ARR_SIZE_4K 1 446 #define ARR_SIZE_8K 2 447 #define ARR_SIZE_16K 3 448 #define ARR_SIZE_32K 4 449 #define ARR_SIZE_64K 5 450 #define ARR_SIZE_128K 6 451 #define ARR_SIZE_256K 7 452 #define ARR_SIZE_512K 8 453 #define ARR_SIZE_1M 9 454 #define ARR_SIZE_2M 10 455 #define ARR_SIZE_4M 11 456 #define ARR_SIZE_8M 12 457 #define ARR_SIZE_16M 13 458 #define ARR_SIZE_32M 14 459 #define ARR_SIZE_4G 15 460 461 /* 462 * The region control registers specify the attributes associated with 463 * the ARRx addres regions. 464 */ 465 #define RCR0 0xdc 466 #define RCR1 0xdd 467 #define RCR2 0xde 468 #define RCR3 0xdf 469 #define RCR4 0xe0 470 #define RCR5 0xe1 471 #define RCR6 0xe2 472 #define RCR7 0xe3 473 474 #define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */ 475 #define RCR_RCE 0x01 /* Enables caching for ARR7. */ 476 #define RCR_WWO 0x02 /* Weak write ordering. */ 477 #define RCR_WL 0x04 /* Weak locking. */ 478 #define RCR_WG 0x08 /* Write gathering. */ 479 #define RCR_WT 0x10 /* Write-through. */ 480 #define RCR_NLB 0x20 /* LBA# pin is not asserted. */ 481 482 /* AMD Write Allocate Top-Of-Memory and Control Register */ 483 #define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */ 484 #define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */ 485 #define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */ 486 487 /* AMD64 MSR's */ 488 #define MSR_EFER 0xc0000080 /* extended features */ 489 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target/cs/ss */ 490 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target rip */ 491 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target rip */ 492 #define MSR_SF_MASK 0xc0000084 /* syscall flags mask */ 493 #define MSR_FSBASE 0xc0000100 /* base address of the %fs "segment" */ 494 #define MSR_GSBASE 0xc0000101 /* base address of the %gs "segment" */ 495 #define MSR_KGSBASE 0xc0000102 /* base address of the kernel %gs */ 496 #define MSR_PERFEVSEL0 0xc0010000 497 #define MSR_PERFEVSEL1 0xc0010001 498 #define MSR_PERFEVSEL2 0xc0010002 499 #define MSR_PERFEVSEL3 0xc0010003 500 #undef MSR_PERFCTR0 501 #undef MSR_PERFCTR1 502 #define MSR_PERFCTR0 0xc0010004 503 #define MSR_PERFCTR1 0xc0010005 504 #define MSR_PERFCTR2 0xc0010006 505 #define MSR_PERFCTR3 0xc0010007 506 #define MSR_SYSCFG 0xc0010010 507 #define MSR_HWCR 0xc0010015 508 #define MSR_IORRBASE0 0xc0010016 509 #define MSR_IORRMASK0 0xc0010017 510 #define MSR_IORRBASE1 0xc0010018 511 #define MSR_IORRMASK1 0xc0010019 512 #define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */ 513 #define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */ 514 #define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */ 515 #define MSR_MC0_CTL_MASK 0xc0010044 516 517 /* VIA ACE crypto featureset: for via_feature_rng */ 518 #define VIA_HAS_RNG 1 /* cpu has RNG */ 519 520 /* VIA ACE crypto featureset: for via_feature_xcrypt */ 521 #define VIA_HAS_AES 1 /* cpu has AES */ 522 #define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */ 523 #define VIA_HAS_MM 4 /* cpu has RSA instructions */ 524 #define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */ 525 526 /* Centaur Extended Feature flags */ 527 #define VIA_CPUID_HAS_RNG 0x000004 528 #define VIA_CPUID_DO_RNG 0x000008 529 #define VIA_CPUID_HAS_ACE 0x000040 530 #define VIA_CPUID_DO_ACE 0x000080 531 #define VIA_CPUID_HAS_ACE2 0x000100 532 #define VIA_CPUID_DO_ACE2 0x000200 533 #define VIA_CPUID_HAS_PHE 0x000400 534 #define VIA_CPUID_DO_PHE 0x000800 535 #define VIA_CPUID_HAS_PMM 0x001000 536 #define VIA_CPUID_DO_PMM 0x002000 537 538 /* VIA ACE xcrypt-* instruction context control options */ 539 #define VIA_CRYPT_CWLO_ROUND_M 0x0000000f 540 #define VIA_CRYPT_CWLO_ALG_M 0x00000070 541 #define VIA_CRYPT_CWLO_ALG_AES 0x00000000 542 #define VIA_CRYPT_CWLO_KEYGEN_M 0x00000080 543 #define VIA_CRYPT_CWLO_KEYGEN_HW 0x00000000 544 #define VIA_CRYPT_CWLO_KEYGEN_SW 0x00000080 545 #define VIA_CRYPT_CWLO_NORMAL 0x00000000 546 #define VIA_CRYPT_CWLO_INTERMEDIATE 0x00000100 547 #define VIA_CRYPT_CWLO_ENCRYPT 0x00000000 548 #define VIA_CRYPT_CWLO_DECRYPT 0x00000200 549 #define VIA_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */ 550 #define VIA_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */ 551 #define VIA_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */ 552 553 #endif /* !_MACHINE_SPECIALREG_H_ */ 554