1 /*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by the University of 16 * California, Berkeley and its contributors. 17 * 4. Neither the name of the University nor the names of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 34 * $FreeBSD$ 35 */ 36 37 #ifndef _MACHINE_SPECIALREG_H_ 38 #define _MACHINE_SPECIALREG_H_ 39 40 /* 41 * Bits in 386 special registers: 42 */ 43 #define CR0_PE 0x00000001 /* Protected mode Enable */ 44 #define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */ 45 #define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */ 46 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 47 #ifdef notused 48 #define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */ 49 #endif 50 #define CR0_PG 0x80000000 /* PaGing enable */ 51 52 /* 53 * Bits in 486 special registers: 54 */ 55 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 56 #define CR0_WP 0x00010000 /* Write Protect (honor page protect in 57 all modes) */ 58 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 59 #define CR0_NW 0x20000000 /* Not Write-through */ 60 #define CR0_CD 0x40000000 /* Cache Disable */ 61 62 /* 63 * Bits in PPro special registers 64 */ 65 #define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */ 66 #define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */ 67 #define CR4_TSD 0x00000004 /* Time stamp disable */ 68 #define CR4_DE 0x00000008 /* Debugging extensions */ 69 #define CR4_PSE 0x00000010 /* Page size extensions */ 70 #define CR4_PAE 0x00000020 /* Physical address extension */ 71 #define CR4_MCE 0x00000040 /* Machine check enable */ 72 #define CR4_PGE 0x00000080 /* Page global enable */ 73 #define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ 74 #define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */ 75 #define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */ 76 77 /* 78 * Bits in AMD64 special registers. EFER is 64 bits wide. 79 */ 80 #define EFER_SCE 0x000000001 /* System Call Extensions (R/W) */ 81 #define EFER_LME 0x000000100 /* Long mode enable (R/W) */ 82 #define EFER_LMA 0x000000400 /* Long mode active (R) */ 83 #define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */ 84 85 /* 86 * CPUID instruction features register 87 */ 88 #define CPUID_FPU 0x00000001 89 #define CPUID_VME 0x00000002 90 #define CPUID_DE 0x00000004 91 #define CPUID_PSE 0x00000008 92 #define CPUID_TSC 0x00000010 93 #define CPUID_MSR 0x00000020 94 #define CPUID_PAE 0x00000040 95 #define CPUID_MCE 0x00000080 96 #define CPUID_CX8 0x00000100 97 #define CPUID_APIC 0x00000200 98 #define CPUID_B10 0x00000400 99 #define CPUID_SEP 0x00000800 100 #define CPUID_MTRR 0x00001000 101 #define CPUID_PGE 0x00002000 102 #define CPUID_MCA 0x00004000 103 #define CPUID_CMOV 0x00008000 104 #define CPUID_PAT 0x00010000 105 #define CPUID_PSE36 0x00020000 106 #define CPUID_PSN 0x00040000 107 #define CPUID_CLFSH 0x00080000 108 #define CPUID_B20 0x00100000 109 #define CPUID_DS 0x00200000 110 #define CPUID_ACPI 0x00400000 111 #define CPUID_MMX 0x00800000 112 #define CPUID_FXSR 0x01000000 113 #define CPUID_SSE 0x02000000 114 #define CPUID_XMM 0x02000000 115 #define CPUID_SSE2 0x04000000 116 #define CPUID_SS 0x08000000 117 #define CPUID_HTT 0x10000000 118 #define CPUID_TM 0x20000000 119 #define CPUID_B30 0x40000000 120 #define CPUID_PBE 0x80000000 121 122 /* 123 * CPUID instruction 1 ebx info 124 */ 125 #define CPUID_BRAND_INDEX 0x000000ff 126 #define CPUID_CLFUSH_SIZE 0x0000ff00 127 #define CPUID_HTT_CORES 0x00ff0000 128 #define CPUID_LOCAL_APIC_ID 0xff000000 129 130 /* 131 * Model-specific registers for the i386 family 132 */ 133 #define MSR_P5_MC_ADDR 0x000 134 #define MSR_P5_MC_TYPE 0x001 135 #define MSR_TSC 0x010 136 #define MSR_APICBASE 0x01b 137 #define MSR_EBL_CR_POWERON 0x02a 138 #define MSR_BIOS_UPDT_TRIG 0x079 139 #define MSR_BIOS_SIGN 0x08b 140 #define MSR_PERFCTR0 0x0c1 141 #define MSR_PERFCTR1 0x0c2 142 #define MSR_MTRRcap 0x0fe 143 #define MSR_SYSENTER_CS 0x174 144 #define MSR_SYSENTER_ESP 0x175 145 #define MSR_SYSENTER_EIP 0x176 146 #define MSR_MCG_CAP 0x179 147 #define MSR_MCG_STATUS 0x17a 148 #define MSR_MCG_CTL 0x17b 149 #define MSR_EVNTSEL0 0x186 150 #define MSR_EVNTSEL1 0x187 151 #define MSR_DEBUGCTLMSR 0x1d9 152 #define MSR_LASTBRANCHFROMIP 0x1db 153 #define MSR_LASTBRANCHTOIP 0x1dc 154 #define MSR_LASTINTFROMIP 0x1dd 155 #define MSR_LASTINTTOIP 0x1de 156 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0 157 #define MSR_MTRRVarBase 0x200 158 #define MSR_MTRR64kBase 0x250 159 #define MSR_MTRR16kBase 0x258 160 #define MSR_MTRR4kBase 0x268 161 #define MSR_PAT 0x277 162 #define MSR_MTRRdefType 0x2ff 163 #define MSR_MC0_CTL 0x400 164 #define MSR_MC0_STATUS 0x401 165 #define MSR_MC0_ADDR 0x402 166 #define MSR_MC0_MISC 0x403 167 #define MSR_MC1_CTL 0x404 168 #define MSR_MC1_STATUS 0x405 169 #define MSR_MC1_ADDR 0x406 170 #define MSR_MC1_MISC 0x407 171 #define MSR_MC2_CTL 0x408 172 #define MSR_MC2_STATUS 0x409 173 #define MSR_MC2_ADDR 0x40a 174 #define MSR_MC2_MISC 0x40b 175 #define MSR_MC4_CTL 0x40c 176 #define MSR_MC4_STATUS 0x40d 177 #define MSR_MC4_ADDR 0x40e 178 #define MSR_MC4_MISC 0x40f 179 #define MSR_MC3_CTL 0x410 180 #define MSR_MC3_STATUS 0x411 181 #define MSR_MC3_ADDR 0x412 182 #define MSR_MC3_MISC 0x413 183 184 /* 185 * Constants related to MTRRs 186 */ 187 #define MTRR_N64K 8 /* numbers of fixed-size entries */ 188 #define MTRR_N16K 16 189 #define MTRR_N4K 64 190 191 /* Performance Control Register (5x86 only). */ 192 #define PCR0 0x20 193 #define PCR0_RSTK 0x01 /* Enables return stack */ 194 #define PCR0_BTB 0x02 /* Enables branch target buffer */ 195 #define PCR0_LOOP 0x04 /* Enables loop */ 196 #define PCR0_AIS 0x08 /* Enables all instrcutions stalled to 197 serialize pipe. */ 198 #define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */ 199 #define PCR0_BTBRT 0x40 /* Enables BTB test register. */ 200 #define PCR0_LSSER 0x80 /* Disable reorder */ 201 202 /* Device Identification Registers */ 203 #define DIR0 0xfe 204 #define DIR1 0xff 205 206 /* 207 * The following four 3-byte registers control the non-cacheable regions. 208 * These registers must be written as three separate bytes. 209 * 210 * NCRx+0: A31-A24 of starting address 211 * NCRx+1: A23-A16 of starting address 212 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 213 * 214 * The non-cacheable region's starting address must be aligned to the 215 * size indicated by the NCR_SIZE_xx field. 216 */ 217 #define NCR1 0xc4 218 #define NCR2 0xc7 219 #define NCR3 0xca 220 #define NCR4 0xcd 221 222 #define NCR_SIZE_0K 0 223 #define NCR_SIZE_4K 1 224 #define NCR_SIZE_8K 2 225 #define NCR_SIZE_16K 3 226 #define NCR_SIZE_32K 4 227 #define NCR_SIZE_64K 5 228 #define NCR_SIZE_128K 6 229 #define NCR_SIZE_256K 7 230 #define NCR_SIZE_512K 8 231 #define NCR_SIZE_1M 9 232 #define NCR_SIZE_2M 10 233 #define NCR_SIZE_4M 11 234 #define NCR_SIZE_8M 12 235 #define NCR_SIZE_16M 13 236 #define NCR_SIZE_32M 14 237 #define NCR_SIZE_4G 15 238 239 /* 240 * The address region registers are used to specify the location and 241 * size for the eight address regions. 242 * 243 * ARRx + 0: A31-A24 of start address 244 * ARRx + 1: A23-A16 of start address 245 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx 246 */ 247 #define ARR0 0xc4 248 #define ARR1 0xc7 249 #define ARR2 0xca 250 #define ARR3 0xcd 251 #define ARR4 0xd0 252 #define ARR5 0xd3 253 #define ARR6 0xd6 254 #define ARR7 0xd9 255 256 #define ARR_SIZE_0K 0 257 #define ARR_SIZE_4K 1 258 #define ARR_SIZE_8K 2 259 #define ARR_SIZE_16K 3 260 #define ARR_SIZE_32K 4 261 #define ARR_SIZE_64K 5 262 #define ARR_SIZE_128K 6 263 #define ARR_SIZE_256K 7 264 #define ARR_SIZE_512K 8 265 #define ARR_SIZE_1M 9 266 #define ARR_SIZE_2M 10 267 #define ARR_SIZE_4M 11 268 #define ARR_SIZE_8M 12 269 #define ARR_SIZE_16M 13 270 #define ARR_SIZE_32M 14 271 #define ARR_SIZE_4G 15 272 273 /* 274 * The region control registers specify the attributes associated with 275 * the ARRx addres regions. 276 */ 277 #define RCR0 0xdc 278 #define RCR1 0xdd 279 #define RCR2 0xde 280 #define RCR3 0xdf 281 #define RCR4 0xe0 282 #define RCR5 0xe1 283 #define RCR6 0xe2 284 #define RCR7 0xe3 285 286 #define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */ 287 #define RCR_RCE 0x01 /* Enables caching for ARR7. */ 288 #define RCR_WWO 0x02 /* Weak write ordering. */ 289 #define RCR_WL 0x04 /* Weak locking. */ 290 #define RCR_WG 0x08 /* Write gathering. */ 291 #define RCR_WT 0x10 /* Write-through. */ 292 #define RCR_NLB 0x20 /* LBA# pin is not asserted. */ 293 294 /* AMD Write Allocate Top-Of-Memory and Control Register */ 295 #define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */ 296 #define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */ 297 #define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */ 298 299 /* X86-64 MSR's */ 300 #define MSR_EFER 0xc0000080 /* extended features */ 301 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target/cs/ss */ 302 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target rip */ 303 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target rip */ 304 #define MSR_SF_MASK 0xc0000084 /* syscall flags mask */ 305 #define MSR_FSBASE 0xc0000100 /* base address of the %fs "segment" */ 306 #define MSR_GSBASE 0xc0000101 /* base address of the %gs "segment" */ 307 #define MSR_KGSBASE 0xc0000102 /* base address of the kernel %gs */ 308 #define MSR_PERFEVSEL0 0xc0010000 309 #define MSR_PERFEVSEL1 0xc0010001 310 #define MSR_PERFEVSEL2 0xc0010002 311 #define MSR_PERFEVSEL3 0xc0010003 312 #undef MSR_PERFCTR0 313 #undef MSR_PERFCTR1 314 #define MSR_PERFCTR0 0xc0010004 315 #define MSR_PERFCTR1 0xc0010005 316 #define MSR_PERFCTR2 0xc0010006 317 #define MSR_PERFCTR3 0xc0010007 318 #define MSR_SYSCFG 0xc0010010 319 #define MSR_IORRBASE0 0xc0010016 320 #define MSR_IORRMASK0 0xc0010017 321 #define MSR_IORRBASE1 0xc0010018 322 #define MSR_IORRMASK1 0xc0010019 323 #define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */ 324 #define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */ 325 326 #endif /* !_MACHINE_SPECIALREG_H_ */ 327