1 /*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 4. Neither the name of the University nor the names of its contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 30 * $FreeBSD$ 31 */ 32 33 #ifndef _MACHINE_SPECIALREG_H_ 34 #define _MACHINE_SPECIALREG_H_ 35 36 /* 37 * Bits in 386 special registers: 38 */ 39 #define CR0_PE 0x00000001 /* Protected mode Enable */ 40 #define CR0_MP 0x00000002 /* "Math" (fpu) Present */ 41 #define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */ 42 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 43 #define CR0_PG 0x80000000 /* PaGing enable */ 44 45 /* 46 * Bits in 486 special registers: 47 */ 48 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 49 #define CR0_WP 0x00010000 /* Write Protect (honor page protect in 50 all modes) */ 51 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 52 #define CR0_NW 0x20000000 /* Not Write-through */ 53 #define CR0_CD 0x40000000 /* Cache Disable */ 54 55 /* 56 * Bits in PPro special registers 57 */ 58 #define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */ 59 #define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */ 60 #define CR4_TSD 0x00000004 /* Time stamp disable */ 61 #define CR4_DE 0x00000008 /* Debugging extensions */ 62 #define CR4_PSE 0x00000010 /* Page size extensions */ 63 #define CR4_PAE 0x00000020 /* Physical address extension */ 64 #define CR4_MCE 0x00000040 /* Machine check enable */ 65 #define CR4_PGE 0x00000080 /* Page global enable */ 66 #define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ 67 #define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */ 68 #define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */ 69 70 /* 71 * Bits in AMD64 special registers. EFER is 64 bits wide. 72 */ 73 #define EFER_SCE 0x000000001 /* System Call Extensions (R/W) */ 74 #define EFER_LME 0x000000100 /* Long mode enable (R/W) */ 75 #define EFER_LMA 0x000000400 /* Long mode active (R) */ 76 #define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */ 77 78 /* 79 * CPUID instruction features register 80 */ 81 #define CPUID_FPU 0x00000001 82 #define CPUID_VME 0x00000002 83 #define CPUID_DE 0x00000004 84 #define CPUID_PSE 0x00000008 85 #define CPUID_TSC 0x00000010 86 #define CPUID_MSR 0x00000020 87 #define CPUID_PAE 0x00000040 88 #define CPUID_MCE 0x00000080 89 #define CPUID_CX8 0x00000100 90 #define CPUID_APIC 0x00000200 91 #define CPUID_B10 0x00000400 92 #define CPUID_SEP 0x00000800 93 #define CPUID_MTRR 0x00001000 94 #define CPUID_PGE 0x00002000 95 #define CPUID_MCA 0x00004000 96 #define CPUID_CMOV 0x00008000 97 #define CPUID_PAT 0x00010000 98 #define CPUID_PSE36 0x00020000 99 #define CPUID_PSN 0x00040000 100 #define CPUID_CLFSH 0x00080000 101 #define CPUID_B20 0x00100000 102 #define CPUID_DS 0x00200000 103 #define CPUID_ACPI 0x00400000 104 #define CPUID_MMX 0x00800000 105 #define CPUID_FXSR 0x01000000 106 #define CPUID_SSE 0x02000000 107 #define CPUID_XMM 0x02000000 108 #define CPUID_SSE2 0x04000000 109 #define CPUID_SS 0x08000000 110 #define CPUID_HTT 0x10000000 111 #define CPUID_TM 0x20000000 112 #define CPUID_IA64 0x40000000 113 #define CPUID_PBE 0x80000000 114 115 #define CPUID2_SSE3 0x00000001 116 #define CPUID2_PCLMULQDQ 0x00000002 117 #define CPUID2_DTES64 0x00000004 118 #define CPUID2_MON 0x00000008 119 #define CPUID2_DS_CPL 0x00000010 120 #define CPUID2_VMX 0x00000020 121 #define CPUID2_SMX 0x00000040 122 #define CPUID2_EST 0x00000080 123 #define CPUID2_TM2 0x00000100 124 #define CPUID2_SSSE3 0x00000200 125 #define CPUID2_CNXTID 0x00000400 126 #define CPUID2_CX16 0x00002000 127 #define CPUID2_XTPR 0x00004000 128 #define CPUID2_PDCM 0x00008000 129 #define CPUID2_PCID 0x00020000 130 #define CPUID2_DCA 0x00040000 131 #define CPUID2_SSE41 0x00080000 132 #define CPUID2_SSE42 0x00100000 133 #define CPUID2_X2APIC 0x00200000 134 #define CPUID2_MOVBE 0x00400000 135 #define CPUID2_POPCNT 0x00800000 136 #define CPUID2_AESNI 0x02000000 137 138 /* 139 * Important bits in the Thermal and Power Management flags 140 * CPUID.6 EAX and ECX. 141 */ 142 #define CPUTPM1_SENSOR 0x00000001 143 #define CPUTPM1_TURBO 0x00000002 144 #define CPUTPM1_ARAT 0x00000004 145 #define CPUTPM2_EFFREQ 0x00000001 146 147 /* 148 * Important bits in the AMD extended cpuid flags 149 */ 150 #define AMDID_SYSCALL 0x00000800 151 #define AMDID_MP 0x00080000 152 #define AMDID_NX 0x00100000 153 #define AMDID_EXT_MMX 0x00400000 154 #define AMDID_FFXSR 0x01000000 155 #define AMDID_PAGE1GB 0x04000000 156 #define AMDID_RDTSCP 0x08000000 157 #define AMDID_LM 0x20000000 158 #define AMDID_EXT_3DNOW 0x40000000 159 #define AMDID_3DNOW 0x80000000 160 161 #define AMDID2_LAHF 0x00000001 162 #define AMDID2_CMP 0x00000002 163 #define AMDID2_SVM 0x00000004 164 #define AMDID2_EXT_APIC 0x00000008 165 #define AMDID2_CR8 0x00000010 166 #define AMDID2_ABM 0x00000020 167 #define AMDID2_SSE4A 0x00000040 168 #define AMDID2_MAS 0x00000080 169 #define AMDID2_PREFETCH 0x00000100 170 #define AMDID2_OSVW 0x00000200 171 #define AMDID2_IBS 0x00000400 172 #define AMDID2_SSE5 0x00000800 173 #define AMDID2_SKINIT 0x00001000 174 #define AMDID2_WDT 0x00002000 175 176 /* 177 * CPUID instruction 1 eax info 178 */ 179 #define CPUID_STEPPING 0x0000000f 180 #define CPUID_MODEL 0x000000f0 181 #define CPUID_FAMILY 0x00000f00 182 #define CPUID_EXT_MODEL 0x000f0000 183 #define CPUID_EXT_FAMILY 0x0ff00000 184 #define CPUID_TO_MODEL(id) \ 185 ((((id) & CPUID_MODEL) >> 4) | \ 186 (((id) & CPUID_EXT_MODEL) >> 12)) 187 #define CPUID_TO_FAMILY(id) \ 188 ((((id) & CPUID_FAMILY) >> 8) + \ 189 (((id) & CPUID_EXT_FAMILY) >> 20)) 190 191 /* 192 * CPUID instruction 1 ebx info 193 */ 194 #define CPUID_BRAND_INDEX 0x000000ff 195 #define CPUID_CLFUSH_SIZE 0x0000ff00 196 #define CPUID_HTT_CORES 0x00ff0000 197 #define CPUID_LOCAL_APIC_ID 0xff000000 198 199 /* 200 * CPUID instruction 6 ecx info 201 */ 202 #define CPUID_PERF_STAT 0x00000001 203 #define CPUID_PERF_BIAS 0x00000008 204 205 /* 206 * CPUID instruction 0xb ebx info. 207 */ 208 #define CPUID_TYPE_INVAL 0 209 #define CPUID_TYPE_SMT 1 210 #define CPUID_TYPE_CORE 2 211 212 /* 213 * AMD extended function 8000_0007h edx info 214 */ 215 #define AMDPM_TS 0x00000001 216 #define AMDPM_FID 0x00000002 217 #define AMDPM_VID 0x00000004 218 #define AMDPM_TTP 0x00000008 219 #define AMDPM_TM 0x00000010 220 #define AMDPM_STC 0x00000020 221 #define AMDPM_100MHZ_STEPS 0x00000040 222 #define AMDPM_HW_PSTATE 0x00000080 223 #define AMDPM_TSC_INVARIANT 0x00000100 224 #define AMDPM_CPB 0x00000200 225 226 /* 227 * AMD extended function 8000_0008h ecx info 228 */ 229 #define AMDID_CMP_CORES 0x000000ff 230 231 /* 232 * CPUID manufacturers identifiers 233 */ 234 #define AMD_VENDOR_ID "AuthenticAMD" 235 #define CENTAUR_VENDOR_ID "CentaurHauls" 236 #define INTEL_VENDOR_ID "GenuineIntel" 237 238 /* 239 * Model-specific registers for the i386 family 240 */ 241 #define MSR_P5_MC_ADDR 0x000 242 #define MSR_P5_MC_TYPE 0x001 243 #define MSR_TSC 0x010 244 #define MSR_P5_CESR 0x011 245 #define MSR_P5_CTR0 0x012 246 #define MSR_P5_CTR1 0x013 247 #define MSR_IA32_PLATFORM_ID 0x017 248 #define MSR_APICBASE 0x01b 249 #define MSR_EBL_CR_POWERON 0x02a 250 #define MSR_TEST_CTL 0x033 251 #define MSR_BIOS_UPDT_TRIG 0x079 252 #define MSR_BBL_CR_D0 0x088 253 #define MSR_BBL_CR_D1 0x089 254 #define MSR_BBL_CR_D2 0x08a 255 #define MSR_BIOS_SIGN 0x08b 256 #define MSR_PERFCTR0 0x0c1 257 #define MSR_PERFCTR1 0x0c2 258 #define MSR_MPERF 0x0e7 259 #define MSR_APERF 0x0e8 260 #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */ 261 #define MSR_MTRRcap 0x0fe 262 #define MSR_BBL_CR_ADDR 0x116 263 #define MSR_BBL_CR_DECC 0x118 264 #define MSR_BBL_CR_CTL 0x119 265 #define MSR_BBL_CR_TRIG 0x11a 266 #define MSR_BBL_CR_BUSY 0x11b 267 #define MSR_BBL_CR_CTL3 0x11e 268 #define MSR_SYSENTER_CS_MSR 0x174 269 #define MSR_SYSENTER_ESP_MSR 0x175 270 #define MSR_SYSENTER_EIP_MSR 0x176 271 #define MSR_MCG_CAP 0x179 272 #define MSR_MCG_STATUS 0x17a 273 #define MSR_MCG_CTL 0x17b 274 #define MSR_EVNTSEL0 0x186 275 #define MSR_EVNTSEL1 0x187 276 #define MSR_THERM_CONTROL 0x19a 277 #define MSR_THERM_INTERRUPT 0x19b 278 #define MSR_THERM_STATUS 0x19c 279 #define MSR_IA32_MISC_ENABLE 0x1a0 280 #define MSR_IA32_TEMPERATURE_TARGET 0x1a2 281 #define MSR_DEBUGCTLMSR 0x1d9 282 #define MSR_LASTBRANCHFROMIP 0x1db 283 #define MSR_LASTBRANCHTOIP 0x1dc 284 #define MSR_LASTINTFROMIP 0x1dd 285 #define MSR_LASTINTTOIP 0x1de 286 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0 287 #define MSR_MTRRVarBase 0x200 288 #define MSR_MTRR64kBase 0x250 289 #define MSR_MTRR16kBase 0x258 290 #define MSR_MTRR4kBase 0x268 291 #define MSR_PAT 0x277 292 #define MSR_MC0_CTL2 0x280 293 #define MSR_MTRRdefType 0x2ff 294 #define MSR_MC0_CTL 0x400 295 #define MSR_MC0_STATUS 0x401 296 #define MSR_MC0_ADDR 0x402 297 #define MSR_MC0_MISC 0x403 298 #define MSR_MC1_CTL 0x404 299 #define MSR_MC1_STATUS 0x405 300 #define MSR_MC1_ADDR 0x406 301 #define MSR_MC1_MISC 0x407 302 #define MSR_MC2_CTL 0x408 303 #define MSR_MC2_STATUS 0x409 304 #define MSR_MC2_ADDR 0x40a 305 #define MSR_MC2_MISC 0x40b 306 #define MSR_MC3_CTL 0x40c 307 #define MSR_MC3_STATUS 0x40d 308 #define MSR_MC3_ADDR 0x40e 309 #define MSR_MC3_MISC 0x40f 310 #define MSR_MC4_CTL 0x410 311 #define MSR_MC4_STATUS 0x411 312 #define MSR_MC4_ADDR 0x412 313 #define MSR_MC4_MISC 0x413 314 315 /* 316 * Constants related to MSR's. 317 */ 318 #define APICBASE_RESERVED 0x000006ff 319 #define APICBASE_BSP 0x00000100 320 #define APICBASE_ENABLED 0x00000800 321 #define APICBASE_ADDRESS 0xfffff000 322 323 /* 324 * PAT modes. 325 */ 326 #define PAT_UNCACHEABLE 0x00 327 #define PAT_WRITE_COMBINING 0x01 328 #define PAT_WRITE_THROUGH 0x04 329 #define PAT_WRITE_PROTECTED 0x05 330 #define PAT_WRITE_BACK 0x06 331 #define PAT_UNCACHED 0x07 332 #define PAT_VALUE(i, m) ((long)(m) << (8 * (i))) 333 #define PAT_MASK(i) PAT_VALUE(i, 0xff) 334 335 /* 336 * Constants related to MTRRs 337 */ 338 #define MTRR_UNCACHEABLE 0x00 339 #define MTRR_WRITE_COMBINING 0x01 340 #define MTRR_WRITE_THROUGH 0x04 341 #define MTRR_WRITE_PROTECTED 0x05 342 #define MTRR_WRITE_BACK 0x06 343 #define MTRR_N64K 8 /* numbers of fixed-size entries */ 344 #define MTRR_N16K 16 345 #define MTRR_N4K 64 346 #define MTRR_CAP_WC 0x0000000000000400 347 #define MTRR_CAP_FIXED 0x0000000000000100 348 #define MTRR_CAP_VCNT 0x00000000000000ff 349 #define MTRR_DEF_ENABLE 0x0000000000000800 350 #define MTRR_DEF_FIXED_ENABLE 0x0000000000000400 351 #define MTRR_DEF_TYPE 0x00000000000000ff 352 #define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000 353 #define MTRR_PHYSBASE_TYPE 0x00000000000000ff 354 #define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000 355 #define MTRR_PHYSMASK_VALID 0x0000000000000800 356 357 /* Performance Control Register (5x86 only). */ 358 #define PCR0 0x20 359 #define PCR0_RSTK 0x01 /* Enables return stack */ 360 #define PCR0_BTB 0x02 /* Enables branch target buffer */ 361 #define PCR0_LOOP 0x04 /* Enables loop */ 362 #define PCR0_AIS 0x08 /* Enables all instrcutions stalled to 363 serialize pipe. */ 364 #define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */ 365 #define PCR0_BTBRT 0x40 /* Enables BTB test register. */ 366 #define PCR0_LSSER 0x80 /* Disable reorder */ 367 368 /* Device Identification Registers */ 369 #define DIR0 0xfe 370 #define DIR1 0xff 371 372 /* 373 * Machine Check register constants. 374 */ 375 #define MCG_CAP_COUNT 0x000000ff 376 #define MCG_CAP_CTL_P 0x00000100 377 #define MCG_CAP_EXT_P 0x00000200 378 #define MCG_CAP_CMCI_P 0x00000400 379 #define MCG_CAP_TES_P 0x00000800 380 #define MCG_CAP_EXT_CNT 0x00ff0000 381 #define MCG_CAP_SER_P 0x01000000 382 #define MCG_STATUS_RIPV 0x00000001 383 #define MCG_STATUS_EIPV 0x00000002 384 #define MCG_STATUS_MCIP 0x00000004 385 #define MCG_CTL_ENABLE 0xffffffffffffffff 386 #define MCG_CTL_DISABLE 0x0000000000000000 387 #define MSR_MC_CTL(x) (MSR_MC0_CTL + (x) * 4) 388 #define MSR_MC_STATUS(x) (MSR_MC0_STATUS + (x) * 4) 389 #define MSR_MC_ADDR(x) (MSR_MC0_ADDR + (x) * 4) 390 #define MSR_MC_MISC(x) (MSR_MC0_MISC + (x) * 4) 391 #define MSR_MC_CTL2(x) (MSR_MC0_CTL2 + (x)) /* If MCG_CAP_CMCI_P */ 392 #define MC_STATUS_MCA_ERROR 0x000000000000ffff 393 #define MC_STATUS_MODEL_ERROR 0x00000000ffff0000 394 #define MC_STATUS_OTHER_INFO 0x01ffffff00000000 395 #define MC_STATUS_COR_COUNT 0x001fffc000000000 /* If MCG_CAP_CMCI_P */ 396 #define MC_STATUS_TES_STATUS 0x0060000000000000 /* If MCG_CAP_TES_P */ 397 #define MC_STATUS_AR 0x0080000000000000 /* If MCG_CAP_TES_P */ 398 #define MC_STATUS_S 0x0100000000000000 /* If MCG_CAP_TES_P */ 399 #define MC_STATUS_PCC 0x0200000000000000 400 #define MC_STATUS_ADDRV 0x0400000000000000 401 #define MC_STATUS_MISCV 0x0800000000000000 402 #define MC_STATUS_EN 0x1000000000000000 403 #define MC_STATUS_UC 0x2000000000000000 404 #define MC_STATUS_OVER 0x4000000000000000 405 #define MC_STATUS_VAL 0x8000000000000000 406 #define MC_MISC_RA_LSB 0x000000000000003f /* If MCG_CAP_SER_P */ 407 #define MC_MISC_ADDRESS_MODE 0x00000000000001c0 /* If MCG_CAP_SER_P */ 408 #define MC_CTL2_THRESHOLD 0x0000000000007fff 409 #define MC_CTL2_CMCI_EN 0x0000000040000000 410 411 /* 412 * The following four 3-byte registers control the non-cacheable regions. 413 * These registers must be written as three separate bytes. 414 * 415 * NCRx+0: A31-A24 of starting address 416 * NCRx+1: A23-A16 of starting address 417 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 418 * 419 * The non-cacheable region's starting address must be aligned to the 420 * size indicated by the NCR_SIZE_xx field. 421 */ 422 #define NCR1 0xc4 423 #define NCR2 0xc7 424 #define NCR3 0xca 425 #define NCR4 0xcd 426 427 #define NCR_SIZE_0K 0 428 #define NCR_SIZE_4K 1 429 #define NCR_SIZE_8K 2 430 #define NCR_SIZE_16K 3 431 #define NCR_SIZE_32K 4 432 #define NCR_SIZE_64K 5 433 #define NCR_SIZE_128K 6 434 #define NCR_SIZE_256K 7 435 #define NCR_SIZE_512K 8 436 #define NCR_SIZE_1M 9 437 #define NCR_SIZE_2M 10 438 #define NCR_SIZE_4M 11 439 #define NCR_SIZE_8M 12 440 #define NCR_SIZE_16M 13 441 #define NCR_SIZE_32M 14 442 #define NCR_SIZE_4G 15 443 444 /* 445 * The address region registers are used to specify the location and 446 * size for the eight address regions. 447 * 448 * ARRx + 0: A31-A24 of start address 449 * ARRx + 1: A23-A16 of start address 450 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx 451 */ 452 #define ARR0 0xc4 453 #define ARR1 0xc7 454 #define ARR2 0xca 455 #define ARR3 0xcd 456 #define ARR4 0xd0 457 #define ARR5 0xd3 458 #define ARR6 0xd6 459 #define ARR7 0xd9 460 461 #define ARR_SIZE_0K 0 462 #define ARR_SIZE_4K 1 463 #define ARR_SIZE_8K 2 464 #define ARR_SIZE_16K 3 465 #define ARR_SIZE_32K 4 466 #define ARR_SIZE_64K 5 467 #define ARR_SIZE_128K 6 468 #define ARR_SIZE_256K 7 469 #define ARR_SIZE_512K 8 470 #define ARR_SIZE_1M 9 471 #define ARR_SIZE_2M 10 472 #define ARR_SIZE_4M 11 473 #define ARR_SIZE_8M 12 474 #define ARR_SIZE_16M 13 475 #define ARR_SIZE_32M 14 476 #define ARR_SIZE_4G 15 477 478 /* 479 * The region control registers specify the attributes associated with 480 * the ARRx addres regions. 481 */ 482 #define RCR0 0xdc 483 #define RCR1 0xdd 484 #define RCR2 0xde 485 #define RCR3 0xdf 486 #define RCR4 0xe0 487 #define RCR5 0xe1 488 #define RCR6 0xe2 489 #define RCR7 0xe3 490 491 #define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */ 492 #define RCR_RCE 0x01 /* Enables caching for ARR7. */ 493 #define RCR_WWO 0x02 /* Weak write ordering. */ 494 #define RCR_WL 0x04 /* Weak locking. */ 495 #define RCR_WG 0x08 /* Write gathering. */ 496 #define RCR_WT 0x10 /* Write-through. */ 497 #define RCR_NLB 0x20 /* LBA# pin is not asserted. */ 498 499 /* AMD Write Allocate Top-Of-Memory and Control Register */ 500 #define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */ 501 #define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */ 502 #define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */ 503 504 /* AMD64 MSR's */ 505 #define MSR_EFER 0xc0000080 /* extended features */ 506 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target/cs/ss */ 507 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target rip */ 508 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target rip */ 509 #define MSR_SF_MASK 0xc0000084 /* syscall flags mask */ 510 #define MSR_FSBASE 0xc0000100 /* base address of the %fs "segment" */ 511 #define MSR_GSBASE 0xc0000101 /* base address of the %gs "segment" */ 512 #define MSR_KGSBASE 0xc0000102 /* base address of the kernel %gs */ 513 #define MSR_PERFEVSEL0 0xc0010000 514 #define MSR_PERFEVSEL1 0xc0010001 515 #define MSR_PERFEVSEL2 0xc0010002 516 #define MSR_PERFEVSEL3 0xc0010003 517 #undef MSR_PERFCTR0 518 #undef MSR_PERFCTR1 519 #define MSR_PERFCTR0 0xc0010004 520 #define MSR_PERFCTR1 0xc0010005 521 #define MSR_PERFCTR2 0xc0010006 522 #define MSR_PERFCTR3 0xc0010007 523 #define MSR_SYSCFG 0xc0010010 524 #define MSR_HWCR 0xc0010015 525 #define MSR_IORRBASE0 0xc0010016 526 #define MSR_IORRMASK0 0xc0010017 527 #define MSR_IORRBASE1 0xc0010018 528 #define MSR_IORRMASK1 0xc0010019 529 #define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */ 530 #define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */ 531 #define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */ 532 #define MSR_MC0_CTL_MASK 0xc0010044 533 534 /* VIA ACE crypto featureset: for via_feature_rng */ 535 #define VIA_HAS_RNG 1 /* cpu has RNG */ 536 537 /* VIA ACE crypto featureset: for via_feature_xcrypt */ 538 #define VIA_HAS_AES 1 /* cpu has AES */ 539 #define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */ 540 #define VIA_HAS_MM 4 /* cpu has RSA instructions */ 541 #define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */ 542 543 /* Centaur Extended Feature flags */ 544 #define VIA_CPUID_HAS_RNG 0x000004 545 #define VIA_CPUID_DO_RNG 0x000008 546 #define VIA_CPUID_HAS_ACE 0x000040 547 #define VIA_CPUID_DO_ACE 0x000080 548 #define VIA_CPUID_HAS_ACE2 0x000100 549 #define VIA_CPUID_DO_ACE2 0x000200 550 #define VIA_CPUID_HAS_PHE 0x000400 551 #define VIA_CPUID_DO_PHE 0x000800 552 #define VIA_CPUID_HAS_PMM 0x001000 553 #define VIA_CPUID_DO_PMM 0x002000 554 555 /* VIA ACE xcrypt-* instruction context control options */ 556 #define VIA_CRYPT_CWLO_ROUND_M 0x0000000f 557 #define VIA_CRYPT_CWLO_ALG_M 0x00000070 558 #define VIA_CRYPT_CWLO_ALG_AES 0x00000000 559 #define VIA_CRYPT_CWLO_KEYGEN_M 0x00000080 560 #define VIA_CRYPT_CWLO_KEYGEN_HW 0x00000000 561 #define VIA_CRYPT_CWLO_KEYGEN_SW 0x00000080 562 #define VIA_CRYPT_CWLO_NORMAL 0x00000000 563 #define VIA_CRYPT_CWLO_INTERMEDIATE 0x00000100 564 #define VIA_CRYPT_CWLO_ENCRYPT 0x00000000 565 #define VIA_CRYPT_CWLO_DECRYPT 0x00000200 566 #define VIA_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */ 567 #define VIA_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */ 568 #define VIA_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */ 569 570 #endif /* !_MACHINE_SPECIALREG_H_ */ 571