1 /*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 4. Neither the name of the University nor the names of its contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 30 * $FreeBSD$ 31 */ 32 33 #ifndef _MACHINE_SPECIALREG_H_ 34 #define _MACHINE_SPECIALREG_H_ 35 36 /* 37 * Bits in 386 special registers: 38 */ 39 #define CR0_PE 0x00000001 /* Protected mode Enable */ 40 #define CR0_MP 0x00000002 /* "Math" (fpu) Present */ 41 #define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */ 42 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 43 #define CR0_PG 0x80000000 /* PaGing enable */ 44 45 /* 46 * Bits in 486 special registers: 47 */ 48 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 49 #define CR0_WP 0x00010000 /* Write Protect (honor page protect in 50 all modes) */ 51 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 52 #define CR0_NW 0x20000000 /* Not Write-through */ 53 #define CR0_CD 0x40000000 /* Cache Disable */ 54 55 /* 56 * Bits in PPro special registers 57 */ 58 #define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */ 59 #define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */ 60 #define CR4_TSD 0x00000004 /* Time stamp disable */ 61 #define CR4_DE 0x00000008 /* Debugging extensions */ 62 #define CR4_PSE 0x00000010 /* Page size extensions */ 63 #define CR4_PAE 0x00000020 /* Physical address extension */ 64 #define CR4_MCE 0x00000040 /* Machine check enable */ 65 #define CR4_PGE 0x00000080 /* Page global enable */ 66 #define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ 67 #define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */ 68 #define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */ 69 70 /* 71 * Bits in AMD64 special registers. EFER is 64 bits wide. 72 */ 73 #define EFER_SCE 0x000000001 /* System Call Extensions (R/W) */ 74 #define EFER_LME 0x000000100 /* Long mode enable (R/W) */ 75 #define EFER_LMA 0x000000400 /* Long mode active (R) */ 76 #define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */ 77 78 /* 79 * CPUID instruction features register 80 */ 81 #define CPUID_FPU 0x00000001 82 #define CPUID_VME 0x00000002 83 #define CPUID_DE 0x00000004 84 #define CPUID_PSE 0x00000008 85 #define CPUID_TSC 0x00000010 86 #define CPUID_MSR 0x00000020 87 #define CPUID_PAE 0x00000040 88 #define CPUID_MCE 0x00000080 89 #define CPUID_CX8 0x00000100 90 #define CPUID_APIC 0x00000200 91 #define CPUID_B10 0x00000400 92 #define CPUID_SEP 0x00000800 93 #define CPUID_MTRR 0x00001000 94 #define CPUID_PGE 0x00002000 95 #define CPUID_MCA 0x00004000 96 #define CPUID_CMOV 0x00008000 97 #define CPUID_PAT 0x00010000 98 #define CPUID_PSE36 0x00020000 99 #define CPUID_PSN 0x00040000 100 #define CPUID_CLFSH 0x00080000 101 #define CPUID_B20 0x00100000 102 #define CPUID_DS 0x00200000 103 #define CPUID_ACPI 0x00400000 104 #define CPUID_MMX 0x00800000 105 #define CPUID_FXSR 0x01000000 106 #define CPUID_SSE 0x02000000 107 #define CPUID_XMM 0x02000000 108 #define CPUID_SSE2 0x04000000 109 #define CPUID_SS 0x08000000 110 #define CPUID_HTT 0x10000000 111 #define CPUID_TM 0x20000000 112 #define CPUID_IA64 0x40000000 113 #define CPUID_PBE 0x80000000 114 115 #define CPUID2_SSE3 0x00000001 116 #define CPUID2_PCLMULQDQ 0x00000002 117 #define CPUID2_DTES64 0x00000004 118 #define CPUID2_MON 0x00000008 119 #define CPUID2_DS_CPL 0x00000010 120 #define CPUID2_VMX 0x00000020 121 #define CPUID2_SMX 0x00000040 122 #define CPUID2_EST 0x00000080 123 #define CPUID2_TM2 0x00000100 124 #define CPUID2_SSSE3 0x00000200 125 #define CPUID2_CNXTID 0x00000400 126 #define CPUID2_CX16 0x00002000 127 #define CPUID2_XTPR 0x00004000 128 #define CPUID2_PDCM 0x00008000 129 #define CPUID2_DCA 0x00040000 130 #define CPUID2_SSE41 0x00080000 131 #define CPUID2_SSE42 0x00100000 132 #define CPUID2_X2APIC 0x00200000 133 #define CPUID2_MOVBE 0x00400000 134 #define CPUID2_POPCNT 0x00800000 135 #define CPUID2_AESNI 0x02000000 136 137 /* 138 * Important bits in the AMD extended cpuid flags 139 */ 140 #define AMDID_SYSCALL 0x00000800 141 #define AMDID_MP 0x00080000 142 #define AMDID_NX 0x00100000 143 #define AMDID_EXT_MMX 0x00400000 144 #define AMDID_FFXSR 0x01000000 145 #define AMDID_PAGE1GB 0x04000000 146 #define AMDID_RDTSCP 0x08000000 147 #define AMDID_LM 0x20000000 148 #define AMDID_EXT_3DNOW 0x40000000 149 #define AMDID_3DNOW 0x80000000 150 151 #define AMDID2_LAHF 0x00000001 152 #define AMDID2_CMP 0x00000002 153 #define AMDID2_SVM 0x00000004 154 #define AMDID2_EXT_APIC 0x00000008 155 #define AMDID2_CR8 0x00000010 156 #define AMDID2_ABM 0x00000020 157 #define AMDID2_SSE4A 0x00000040 158 #define AMDID2_MAS 0x00000080 159 #define AMDID2_PREFETCH 0x00000100 160 #define AMDID2_OSVW 0x00000200 161 #define AMDID2_IBS 0x00000400 162 #define AMDID2_SSE5 0x00000800 163 #define AMDID2_SKINIT 0x00001000 164 #define AMDID2_WDT 0x00002000 165 166 /* 167 * CPUID instruction 1 eax info 168 */ 169 #define CPUID_STEPPING 0x0000000f 170 #define CPUID_MODEL 0x000000f0 171 #define CPUID_FAMILY 0x00000f00 172 #define CPUID_EXT_MODEL 0x000f0000 173 #define CPUID_EXT_FAMILY 0x0ff00000 174 #define CPUID_TO_MODEL(id) \ 175 ((((id) & CPUID_MODEL) >> 4) | \ 176 (((id) & CPUID_EXT_MODEL) >> 12)) 177 #define CPUID_TO_FAMILY(id) \ 178 ((((id) & CPUID_FAMILY) >> 8) + \ 179 (((id) & CPUID_EXT_FAMILY) >> 20)) 180 181 /* 182 * CPUID instruction 1 ebx info 183 */ 184 #define CPUID_BRAND_INDEX 0x000000ff 185 #define CPUID_CLFUSH_SIZE 0x0000ff00 186 #define CPUID_HTT_CORES 0x00ff0000 187 #define CPUID_LOCAL_APIC_ID 0xff000000 188 189 /* 190 * CPUID instruction 0xb ebx info. 191 */ 192 #define CPUID_TYPE_INVAL 0 193 #define CPUID_TYPE_SMT 1 194 #define CPUID_TYPE_CORE 2 195 196 /* 197 * AMD extended function 8000_0007h edx info 198 */ 199 #define AMDPM_TS 0x00000001 200 #define AMDPM_FID 0x00000002 201 #define AMDPM_VID 0x00000004 202 #define AMDPM_TTP 0x00000008 203 #define AMDPM_TM 0x00000010 204 #define AMDPM_STC 0x00000020 205 #define AMDPM_100MHZ_STEPS 0x00000040 206 #define AMDPM_HW_PSTATE 0x00000080 207 #define AMDPM_TSC_INVARIANT 0x00000100 208 209 /* 210 * AMD extended function 8000_0008h ecx info 211 */ 212 #define AMDID_CMP_CORES 0x000000ff 213 214 /* 215 * CPUID manufacturers identifiers 216 */ 217 #define AMD_VENDOR_ID "AuthenticAMD" 218 #define CENTAUR_VENDOR_ID "CentaurHauls" 219 #define INTEL_VENDOR_ID "GenuineIntel" 220 221 /* 222 * Model-specific registers for the i386 family 223 */ 224 #define MSR_P5_MC_ADDR 0x000 225 #define MSR_P5_MC_TYPE 0x001 226 #define MSR_TSC 0x010 227 #define MSR_P5_CESR 0x011 228 #define MSR_P5_CTR0 0x012 229 #define MSR_P5_CTR1 0x013 230 #define MSR_IA32_PLATFORM_ID 0x017 231 #define MSR_APICBASE 0x01b 232 #define MSR_EBL_CR_POWERON 0x02a 233 #define MSR_TEST_CTL 0x033 234 #define MSR_BIOS_UPDT_TRIG 0x079 235 #define MSR_BBL_CR_D0 0x088 236 #define MSR_BBL_CR_D1 0x089 237 #define MSR_BBL_CR_D2 0x08a 238 #define MSR_BIOS_SIGN 0x08b 239 #define MSR_PERFCTR0 0x0c1 240 #define MSR_PERFCTR1 0x0c2 241 #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */ 242 #define MSR_MTRRcap 0x0fe 243 #define MSR_BBL_CR_ADDR 0x116 244 #define MSR_BBL_CR_DECC 0x118 245 #define MSR_BBL_CR_CTL 0x119 246 #define MSR_BBL_CR_TRIG 0x11a 247 #define MSR_BBL_CR_BUSY 0x11b 248 #define MSR_BBL_CR_CTL3 0x11e 249 #define MSR_SYSENTER_CS_MSR 0x174 250 #define MSR_SYSENTER_ESP_MSR 0x175 251 #define MSR_SYSENTER_EIP_MSR 0x176 252 #define MSR_MCG_CAP 0x179 253 #define MSR_MCG_STATUS 0x17a 254 #define MSR_MCG_CTL 0x17b 255 #define MSR_EVNTSEL0 0x186 256 #define MSR_EVNTSEL1 0x187 257 #define MSR_THERM_CONTROL 0x19a 258 #define MSR_THERM_INTERRUPT 0x19b 259 #define MSR_THERM_STATUS 0x19c 260 #define MSR_IA32_MISC_ENABLE 0x1a0 261 #define MSR_IA32_TEMPERATURE_TARGET 0x1a2 262 #define MSR_DEBUGCTLMSR 0x1d9 263 #define MSR_LASTBRANCHFROMIP 0x1db 264 #define MSR_LASTBRANCHTOIP 0x1dc 265 #define MSR_LASTINTFROMIP 0x1dd 266 #define MSR_LASTINTTOIP 0x1de 267 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0 268 #define MSR_MTRRVarBase 0x200 269 #define MSR_MTRR64kBase 0x250 270 #define MSR_MTRR16kBase 0x258 271 #define MSR_MTRR4kBase 0x268 272 #define MSR_PAT 0x277 273 #define MSR_MC0_CTL2 0x280 274 #define MSR_MTRRdefType 0x2ff 275 #define MSR_MC0_CTL 0x400 276 #define MSR_MC0_STATUS 0x401 277 #define MSR_MC0_ADDR 0x402 278 #define MSR_MC0_MISC 0x403 279 #define MSR_MC1_CTL 0x404 280 #define MSR_MC1_STATUS 0x405 281 #define MSR_MC1_ADDR 0x406 282 #define MSR_MC1_MISC 0x407 283 #define MSR_MC2_CTL 0x408 284 #define MSR_MC2_STATUS 0x409 285 #define MSR_MC2_ADDR 0x40a 286 #define MSR_MC2_MISC 0x40b 287 #define MSR_MC3_CTL 0x40c 288 #define MSR_MC3_STATUS 0x40d 289 #define MSR_MC3_ADDR 0x40e 290 #define MSR_MC3_MISC 0x40f 291 #define MSR_MC4_CTL 0x410 292 #define MSR_MC4_STATUS 0x411 293 #define MSR_MC4_ADDR 0x412 294 #define MSR_MC4_MISC 0x413 295 296 /* 297 * Constants related to MSR's. 298 */ 299 #define APICBASE_RESERVED 0x000006ff 300 #define APICBASE_BSP 0x00000100 301 #define APICBASE_ENABLED 0x00000800 302 #define APICBASE_ADDRESS 0xfffff000 303 304 /* 305 * PAT modes. 306 */ 307 #define PAT_UNCACHEABLE 0x00 308 #define PAT_WRITE_COMBINING 0x01 309 #define PAT_WRITE_THROUGH 0x04 310 #define PAT_WRITE_PROTECTED 0x05 311 #define PAT_WRITE_BACK 0x06 312 #define PAT_UNCACHED 0x07 313 #define PAT_VALUE(i, m) ((long)(m) << (8 * (i))) 314 #define PAT_MASK(i) PAT_VALUE(i, 0xff) 315 316 /* 317 * Constants related to MTRRs 318 */ 319 #define MTRR_UNCACHEABLE 0x00 320 #define MTRR_WRITE_COMBINING 0x01 321 #define MTRR_WRITE_THROUGH 0x04 322 #define MTRR_WRITE_PROTECTED 0x05 323 #define MTRR_WRITE_BACK 0x06 324 #define MTRR_N64K 8 /* numbers of fixed-size entries */ 325 #define MTRR_N16K 16 326 #define MTRR_N4K 64 327 #define MTRR_CAP_WC 0x0000000000000400 328 #define MTRR_CAP_FIXED 0x0000000000000100 329 #define MTRR_CAP_VCNT 0x00000000000000ff 330 #define MTRR_DEF_ENABLE 0x0000000000000800 331 #define MTRR_DEF_FIXED_ENABLE 0x0000000000000400 332 #define MTRR_DEF_TYPE 0x00000000000000ff 333 #define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000 334 #define MTRR_PHYSBASE_TYPE 0x00000000000000ff 335 #define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000 336 #define MTRR_PHYSMASK_VALID 0x0000000000000800 337 338 /* Performance Control Register (5x86 only). */ 339 #define PCR0 0x20 340 #define PCR0_RSTK 0x01 /* Enables return stack */ 341 #define PCR0_BTB 0x02 /* Enables branch target buffer */ 342 #define PCR0_LOOP 0x04 /* Enables loop */ 343 #define PCR0_AIS 0x08 /* Enables all instrcutions stalled to 344 serialize pipe. */ 345 #define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */ 346 #define PCR0_BTBRT 0x40 /* Enables BTB test register. */ 347 #define PCR0_LSSER 0x80 /* Disable reorder */ 348 349 /* Device Identification Registers */ 350 #define DIR0 0xfe 351 #define DIR1 0xff 352 353 /* 354 * Machine Check register constants. 355 */ 356 #define MCG_CAP_COUNT 0x000000ff 357 #define MCG_CAP_CTL_P 0x00000100 358 #define MCG_CAP_EXT_P 0x00000200 359 #define MCG_CAP_CMCI_P 0x00000400 360 #define MCG_CAP_TES_P 0x00000800 361 #define MCG_CAP_EXT_CNT 0x00ff0000 362 #define MCG_CAP_SER_P 0x01000000 363 #define MCG_STATUS_RIPV 0x00000001 364 #define MCG_STATUS_EIPV 0x00000002 365 #define MCG_STATUS_MCIP 0x00000004 366 #define MCG_CTL_ENABLE 0xffffffffffffffff 367 #define MCG_CTL_DISABLE 0x0000000000000000 368 #define MSR_MC_CTL(x) (MSR_MC0_CTL + (x) * 4) 369 #define MSR_MC_STATUS(x) (MSR_MC0_STATUS + (x) * 4) 370 #define MSR_MC_ADDR(x) (MSR_MC0_ADDR + (x) * 4) 371 #define MSR_MC_MISC(x) (MSR_MC0_MISC + (x) * 4) 372 #define MSR_MC_CTL2(x) (MSR_MC0_CTL2 + (x)) /* If MCG_CAP_CMCI_P */ 373 #define MC_STATUS_MCA_ERROR 0x000000000000ffff 374 #define MC_STATUS_MODEL_ERROR 0x00000000ffff0000 375 #define MC_STATUS_OTHER_INFO 0x01ffffff00000000 376 #define MC_STATUS_COR_COUNT 0x001fffc000000000 /* If MCG_CAP_CMCI_P */ 377 #define MC_STATUS_TES_STATUS 0x0060000000000000 /* If MCG_CAP_TES_P */ 378 #define MC_STATUS_AR 0x0080000000000000 /* If MCG_CAP_TES_P */ 379 #define MC_STATUS_S 0x0100000000000000 /* If MCG_CAP_TES_P */ 380 #define MC_STATUS_PCC 0x0200000000000000 381 #define MC_STATUS_ADDRV 0x0400000000000000 382 #define MC_STATUS_MISCV 0x0800000000000000 383 #define MC_STATUS_EN 0x1000000000000000 384 #define MC_STATUS_UC 0x2000000000000000 385 #define MC_STATUS_OVER 0x4000000000000000 386 #define MC_STATUS_VAL 0x8000000000000000 387 #define MC_MISC_RA_LSB 0x000000000000003f /* If MCG_CAP_SER_P */ 388 #define MC_MISC_ADDRESS_MODE 0x00000000000001c0 /* If MCG_CAP_SER_P */ 389 #define MC_CTL2_THRESHOLD 0x0000000000007fff 390 #define MC_CTL2_CMCI_EN 0x0000000040000000 391 392 /* 393 * The following four 3-byte registers control the non-cacheable regions. 394 * These registers must be written as three separate bytes. 395 * 396 * NCRx+0: A31-A24 of starting address 397 * NCRx+1: A23-A16 of starting address 398 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 399 * 400 * The non-cacheable region's starting address must be aligned to the 401 * size indicated by the NCR_SIZE_xx field. 402 */ 403 #define NCR1 0xc4 404 #define NCR2 0xc7 405 #define NCR3 0xca 406 #define NCR4 0xcd 407 408 #define NCR_SIZE_0K 0 409 #define NCR_SIZE_4K 1 410 #define NCR_SIZE_8K 2 411 #define NCR_SIZE_16K 3 412 #define NCR_SIZE_32K 4 413 #define NCR_SIZE_64K 5 414 #define NCR_SIZE_128K 6 415 #define NCR_SIZE_256K 7 416 #define NCR_SIZE_512K 8 417 #define NCR_SIZE_1M 9 418 #define NCR_SIZE_2M 10 419 #define NCR_SIZE_4M 11 420 #define NCR_SIZE_8M 12 421 #define NCR_SIZE_16M 13 422 #define NCR_SIZE_32M 14 423 #define NCR_SIZE_4G 15 424 425 /* 426 * The address region registers are used to specify the location and 427 * size for the eight address regions. 428 * 429 * ARRx + 0: A31-A24 of start address 430 * ARRx + 1: A23-A16 of start address 431 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx 432 */ 433 #define ARR0 0xc4 434 #define ARR1 0xc7 435 #define ARR2 0xca 436 #define ARR3 0xcd 437 #define ARR4 0xd0 438 #define ARR5 0xd3 439 #define ARR6 0xd6 440 #define ARR7 0xd9 441 442 #define ARR_SIZE_0K 0 443 #define ARR_SIZE_4K 1 444 #define ARR_SIZE_8K 2 445 #define ARR_SIZE_16K 3 446 #define ARR_SIZE_32K 4 447 #define ARR_SIZE_64K 5 448 #define ARR_SIZE_128K 6 449 #define ARR_SIZE_256K 7 450 #define ARR_SIZE_512K 8 451 #define ARR_SIZE_1M 9 452 #define ARR_SIZE_2M 10 453 #define ARR_SIZE_4M 11 454 #define ARR_SIZE_8M 12 455 #define ARR_SIZE_16M 13 456 #define ARR_SIZE_32M 14 457 #define ARR_SIZE_4G 15 458 459 /* 460 * The region control registers specify the attributes associated with 461 * the ARRx addres regions. 462 */ 463 #define RCR0 0xdc 464 #define RCR1 0xdd 465 #define RCR2 0xde 466 #define RCR3 0xdf 467 #define RCR4 0xe0 468 #define RCR5 0xe1 469 #define RCR6 0xe2 470 #define RCR7 0xe3 471 472 #define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */ 473 #define RCR_RCE 0x01 /* Enables caching for ARR7. */ 474 #define RCR_WWO 0x02 /* Weak write ordering. */ 475 #define RCR_WL 0x04 /* Weak locking. */ 476 #define RCR_WG 0x08 /* Write gathering. */ 477 #define RCR_WT 0x10 /* Write-through. */ 478 #define RCR_NLB 0x20 /* LBA# pin is not asserted. */ 479 480 /* AMD Write Allocate Top-Of-Memory and Control Register */ 481 #define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */ 482 #define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */ 483 #define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */ 484 485 /* AMD64 MSR's */ 486 #define MSR_EFER 0xc0000080 /* extended features */ 487 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target/cs/ss */ 488 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target rip */ 489 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target rip */ 490 #define MSR_SF_MASK 0xc0000084 /* syscall flags mask */ 491 #define MSR_FSBASE 0xc0000100 /* base address of the %fs "segment" */ 492 #define MSR_GSBASE 0xc0000101 /* base address of the %gs "segment" */ 493 #define MSR_KGSBASE 0xc0000102 /* base address of the kernel %gs */ 494 #define MSR_PERFEVSEL0 0xc0010000 495 #define MSR_PERFEVSEL1 0xc0010001 496 #define MSR_PERFEVSEL2 0xc0010002 497 #define MSR_PERFEVSEL3 0xc0010003 498 #undef MSR_PERFCTR0 499 #undef MSR_PERFCTR1 500 #define MSR_PERFCTR0 0xc0010004 501 #define MSR_PERFCTR1 0xc0010005 502 #define MSR_PERFCTR2 0xc0010006 503 #define MSR_PERFCTR3 0xc0010007 504 #define MSR_SYSCFG 0xc0010010 505 #define MSR_IORRBASE0 0xc0010016 506 #define MSR_IORRMASK0 0xc0010017 507 #define MSR_IORRBASE1 0xc0010018 508 #define MSR_IORRMASK1 0xc0010019 509 #define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */ 510 #define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */ 511 #define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */ 512 #define MSR_MC0_CTL_MASK 0xc0010044 513 514 /* VIA ACE crypto featureset: for via_feature_rng */ 515 #define VIA_HAS_RNG 1 /* cpu has RNG */ 516 517 /* VIA ACE crypto featureset: for via_feature_xcrypt */ 518 #define VIA_HAS_AES 1 /* cpu has AES */ 519 #define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */ 520 #define VIA_HAS_MM 4 /* cpu has RSA instructions */ 521 #define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */ 522 523 /* Centaur Extended Feature flags */ 524 #define VIA_CPUID_HAS_RNG 0x000004 525 #define VIA_CPUID_DO_RNG 0x000008 526 #define VIA_CPUID_HAS_ACE 0x000040 527 #define VIA_CPUID_DO_ACE 0x000080 528 #define VIA_CPUID_HAS_ACE2 0x000100 529 #define VIA_CPUID_DO_ACE2 0x000200 530 #define VIA_CPUID_HAS_PHE 0x000400 531 #define VIA_CPUID_DO_PHE 0x000800 532 #define VIA_CPUID_HAS_PMM 0x001000 533 #define VIA_CPUID_DO_PMM 0x002000 534 535 /* VIA ACE xcrypt-* instruction context control options */ 536 #define VIA_CRYPT_CWLO_ROUND_M 0x0000000f 537 #define VIA_CRYPT_CWLO_ALG_M 0x00000070 538 #define VIA_CRYPT_CWLO_ALG_AES 0x00000000 539 #define VIA_CRYPT_CWLO_KEYGEN_M 0x00000080 540 #define VIA_CRYPT_CWLO_KEYGEN_HW 0x00000000 541 #define VIA_CRYPT_CWLO_KEYGEN_SW 0x00000080 542 #define VIA_CRYPT_CWLO_NORMAL 0x00000000 543 #define VIA_CRYPT_CWLO_INTERMEDIATE 0x00000100 544 #define VIA_CRYPT_CWLO_ENCRYPT 0x00000000 545 #define VIA_CRYPT_CWLO_DECRYPT 0x00000200 546 #define VIA_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */ 547 #define VIA_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */ 548 #define VIA_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */ 549 550 #endif /* !_MACHINE_SPECIALREG_H_ */ 551