1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 2003 Peter Wemm. 5 * Copyright (c) 1991 Regents of the University of California. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * the Systems Programming Group of the University of Utah Computer 10 * Science Department and William Jolitz of UUNET Technologies Inc. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * Derived from hp300 version by Mike Hibler, this version by William 37 * Jolitz uses a recursive map [a pde points to the page directory] to 38 * map the page tables using the pagetables themselves. This is done to 39 * reduce the impact on kernel virtual memory for lots of sparse address 40 * space, and to reduce the cost of memory to each process. 41 * 42 * from: hp300: @(#)pmap.h 7.2 (Berkeley) 12/16/90 43 * from: @(#)pmap.h 7.4 (Berkeley) 5/12/91 44 * $FreeBSD$ 45 */ 46 47 #ifndef _MACHINE_PMAP_H_ 48 #define _MACHINE_PMAP_H_ 49 50 /* 51 * Page-directory and page-table entries follow this format, with a few 52 * of the fields not present here and there, depending on a lot of things. 53 */ 54 /* ---- Intel Nomenclature ---- */ 55 #define X86_PG_V 0x001 /* P Valid */ 56 #define X86_PG_RW 0x002 /* R/W Read/Write */ 57 #define X86_PG_U 0x004 /* U/S User/Supervisor */ 58 #define X86_PG_NC_PWT 0x008 /* PWT Write through */ 59 #define X86_PG_NC_PCD 0x010 /* PCD Cache disable */ 60 #define X86_PG_A 0x020 /* A Accessed */ 61 #define X86_PG_M 0x040 /* D Dirty */ 62 #define X86_PG_PS 0x080 /* PS Page size (0=4k,1=2M) */ 63 #define X86_PG_PTE_PAT 0x080 /* PAT PAT index */ 64 #define X86_PG_G 0x100 /* G Global */ 65 #define X86_PG_AVAIL1 0x200 /* / Available for system */ 66 #define X86_PG_AVAIL2 0x400 /* < programmers use */ 67 #define X86_PG_AVAIL3 0x800 /* \ */ 68 #define X86_PG_PDE_PAT 0x1000 /* PAT PAT index */ 69 #define X86_PG_PKU(idx) ((pt_entry_t)idx << 59) 70 #define X86_PG_NX (1ul<<63) /* No-execute */ 71 #define X86_PG_AVAIL(x) (1ul << (x)) 72 73 /* Page level cache control fields used to determine the PAT type */ 74 #define X86_PG_PDE_CACHE (X86_PG_PDE_PAT | X86_PG_NC_PWT | X86_PG_NC_PCD) 75 #define X86_PG_PTE_CACHE (X86_PG_PTE_PAT | X86_PG_NC_PWT | X86_PG_NC_PCD) 76 77 /* Protection keys indexes */ 78 #define PMAP_MAX_PKRU_IDX 0xf 79 #define X86_PG_PKU_MASK X86_PG_PKU(PMAP_MAX_PKRU_IDX) 80 81 /* 82 * Intel extended page table (EPT) bit definitions. 83 */ 84 #define EPT_PG_READ 0x001 /* R Read */ 85 #define EPT_PG_WRITE 0x002 /* W Write */ 86 #define EPT_PG_EXECUTE 0x004 /* X Execute */ 87 #define EPT_PG_IGNORE_PAT 0x040 /* IPAT Ignore PAT */ 88 #define EPT_PG_PS 0x080 /* PS Page size */ 89 #define EPT_PG_A 0x100 /* A Accessed */ 90 #define EPT_PG_M 0x200 /* D Dirty */ 91 #define EPT_PG_MEMORY_TYPE(x) ((x) << 3) /* MT Memory Type */ 92 93 /* 94 * Define the PG_xx macros in terms of the bits on x86 PTEs. 95 */ 96 #define PG_V X86_PG_V 97 #define PG_RW X86_PG_RW 98 #define PG_U X86_PG_U 99 #define PG_NC_PWT X86_PG_NC_PWT 100 #define PG_NC_PCD X86_PG_NC_PCD 101 #define PG_A X86_PG_A 102 #define PG_M X86_PG_M 103 #define PG_PS X86_PG_PS 104 #define PG_PTE_PAT X86_PG_PTE_PAT 105 #define PG_G X86_PG_G 106 #define PG_AVAIL1 X86_PG_AVAIL1 107 #define PG_AVAIL2 X86_PG_AVAIL2 108 #define PG_AVAIL3 X86_PG_AVAIL3 109 #define PG_PDE_PAT X86_PG_PDE_PAT 110 #define PG_NX X86_PG_NX 111 #define PG_PDE_CACHE X86_PG_PDE_CACHE 112 #define PG_PTE_CACHE X86_PG_PTE_CACHE 113 114 /* Our various interpretations of the above */ 115 #define PG_W X86_PG_AVAIL3 /* "Wired" pseudoflag */ 116 #define PG_MANAGED X86_PG_AVAIL2 117 #define EPT_PG_EMUL_V X86_PG_AVAIL(52) 118 #define EPT_PG_EMUL_RW X86_PG_AVAIL(53) 119 #define PG_PROMOTED X86_PG_AVAIL(54) /* PDE only */ 120 #define PG_FRAME (0x000ffffffffff000ul) 121 #define PG_PS_FRAME (0x000fffffffe00000ul) 122 123 /* 124 * Promotion to a 2MB (PDE) page mapping requires that the corresponding 4KB 125 * (PTE) page mappings have identical settings for the following fields: 126 */ 127 #define PG_PTE_PROMOTE (PG_NX | PG_MANAGED | PG_W | PG_G | PG_PTE_CACHE | \ 128 PG_M | PG_A | PG_U | PG_RW | PG_V | PG_PKU_MASK) 129 130 /* 131 * Page Protection Exception bits 132 */ 133 134 #define PGEX_P 0x01 /* Protection violation vs. not present */ 135 #define PGEX_W 0x02 /* during a Write cycle */ 136 #define PGEX_U 0x04 /* access from User mode (UPL) */ 137 #define PGEX_RSV 0x08 /* reserved PTE field is non-zero */ 138 #define PGEX_I 0x10 /* during an instruction fetch */ 139 #define PGEX_PK 0x20 /* protection key violation */ 140 #define PGEX_SGX 0x40 /* SGX-related */ 141 142 /* 143 * undef the PG_xx macros that define bits in the regular x86 PTEs that 144 * have a different position in nested PTEs. This is done when compiling 145 * code that needs to be aware of the differences between regular x86 and 146 * nested PTEs. 147 * 148 * The appropriate bitmask will be calculated at runtime based on the pmap 149 * type. 150 */ 151 #ifdef AMD64_NPT_AWARE 152 #undef PG_AVAIL1 /* X86_PG_AVAIL1 aliases with EPT_PG_M */ 153 #undef PG_G 154 #undef PG_A 155 #undef PG_M 156 #undef PG_PDE_PAT 157 #undef PG_PDE_CACHE 158 #undef PG_PTE_PAT 159 #undef PG_PTE_CACHE 160 #undef PG_RW 161 #undef PG_V 162 #endif 163 164 /* 165 * Pte related macros. This is complicated by having to deal with 166 * the sign extension of the 48th bit. 167 */ 168 #define KVADDR(l4, l3, l2, l1) ( \ 169 ((unsigned long)-1 << 47) | \ 170 ((unsigned long)(l4) << PML4SHIFT) | \ 171 ((unsigned long)(l3) << PDPSHIFT) | \ 172 ((unsigned long)(l2) << PDRSHIFT) | \ 173 ((unsigned long)(l1) << PAGE_SHIFT)) 174 175 #define UVADDR(l4, l3, l2, l1) ( \ 176 ((unsigned long)(l4) << PML4SHIFT) | \ 177 ((unsigned long)(l3) << PDPSHIFT) | \ 178 ((unsigned long)(l2) << PDRSHIFT) | \ 179 ((unsigned long)(l1) << PAGE_SHIFT)) 180 181 /* 182 * Number of kernel PML4 slots. Can be anywhere from 1 to 64 or so, 183 * but setting it larger than NDMPML4E makes no sense. 184 * 185 * Each slot provides .5 TB of kernel virtual space. 186 */ 187 #define NKPML4E 4 188 189 #define NUPML4E (NPML4EPG/2) /* number of userland PML4 pages */ 190 #define NUPDPE (NUPML4E*NPDPEPG)/* number of userland PDP pages */ 191 #define NUPDE (NUPDPE*NPDEPG) /* number of userland PD entries */ 192 193 /* 194 * NDMPML4E is the maximum number of PML4 entries that will be 195 * used to implement the direct map. It must be a power of two, 196 * and should generally exceed NKPML4E. The maximum possible 197 * value is 64; using 128 will make the direct map intrude into 198 * the recursive page table map. 199 */ 200 #define NDMPML4E 8 201 202 /* 203 * These values control the layout of virtual memory. The starting address 204 * of the direct map, which is controlled by DMPML4I, must be a multiple of 205 * its size. (See the PHYS_TO_DMAP() and DMAP_TO_PHYS() macros.) 206 * 207 * Note: KPML4I is the index of the (single) level 4 page that maps 208 * the KVA that holds KERNBASE, while KPML4BASE is the index of the 209 * first level 4 page that maps VM_MIN_KERNEL_ADDRESS. If NKPML4E 210 * is 1, these are the same, otherwise KPML4BASE < KPML4I and extra 211 * level 4 PDEs are needed to map from VM_MIN_KERNEL_ADDRESS up to 212 * KERNBASE. 213 * 214 * (KPML4I combines with KPDPI to choose where KERNBASE starts. 215 * Or, in other words, KPML4I provides bits 39..47 of KERNBASE, 216 * and KPDPI provides bits 30..38.) 217 */ 218 #define PML4PML4I (NPML4EPG/2) /* Index of recursive pml4 mapping */ 219 220 #define KPML4BASE (NPML4EPG-NKPML4E) /* KVM at highest addresses */ 221 #define DMPML4I rounddown(KPML4BASE-NDMPML4E, NDMPML4E) /* Below KVM */ 222 223 #define KPML4I (NPML4EPG-1) 224 #define KPDPI (NPDPEPG-2) /* kernbase at -2GB */ 225 226 /* Large map: index of the first and max last pml4 entry */ 227 #define LMSPML4I (PML4PML4I + 1) 228 #define LMEPML4I (DMPML4I - 1) 229 230 /* 231 * XXX doesn't really belong here I guess... 232 */ 233 #define ISA_HOLE_START 0xa0000 234 #define ISA_HOLE_LENGTH (0x100000-ISA_HOLE_START) 235 236 #define PMAP_PCID_NONE 0xffffffff 237 #define PMAP_PCID_KERN 0 238 #define PMAP_PCID_OVERMAX 0x1000 239 #define PMAP_PCID_OVERMAX_KERN 0x800 240 #define PMAP_PCID_USER_PT 0x800 241 242 #define PMAP_NO_CR3 (~0UL) 243 244 #ifndef LOCORE 245 246 #include <sys/queue.h> 247 #include <sys/_cpuset.h> 248 #include <sys/_lock.h> 249 #include <sys/_mutex.h> 250 #include <sys/_pctrie.h> 251 #include <sys/_rangeset.h> 252 253 #include <vm/_vm_radix.h> 254 255 typedef u_int64_t pd_entry_t; 256 typedef u_int64_t pt_entry_t; 257 typedef u_int64_t pdp_entry_t; 258 typedef u_int64_t pml4_entry_t; 259 260 /* 261 * Address of current address space page table maps and directories. 262 */ 263 #ifdef _KERNEL 264 #define addr_PTmap (KVADDR(PML4PML4I, 0, 0, 0)) 265 #define addr_PDmap (KVADDR(PML4PML4I, PML4PML4I, 0, 0)) 266 #define addr_PDPmap (KVADDR(PML4PML4I, PML4PML4I, PML4PML4I, 0)) 267 #define addr_PML4map (KVADDR(PML4PML4I, PML4PML4I, PML4PML4I, PML4PML4I)) 268 #define addr_PML4pml4e (addr_PML4map + (PML4PML4I * sizeof(pml4_entry_t))) 269 #define PTmap ((pt_entry_t *)(addr_PTmap)) 270 #define PDmap ((pd_entry_t *)(addr_PDmap)) 271 #define PDPmap ((pd_entry_t *)(addr_PDPmap)) 272 #define PML4map ((pd_entry_t *)(addr_PML4map)) 273 #define PML4pml4e ((pd_entry_t *)(addr_PML4pml4e)) 274 275 extern int nkpt; /* Initial number of kernel page tables */ 276 extern u_int64_t KPDPphys; /* physical address of kernel level 3 */ 277 extern u_int64_t KPML4phys; /* physical address of kernel level 4 */ 278 279 /* 280 * virtual address to page table entry and 281 * to physical address. 282 * Note: these work recursively, thus vtopte of a pte will give 283 * the corresponding pde that in turn maps it. 284 */ 285 pt_entry_t *vtopte(vm_offset_t); 286 #define vtophys(va) pmap_kextract(((vm_offset_t) (va))) 287 288 #define pte_load_store(ptep, pte) atomic_swap_long(ptep, pte) 289 #define pte_load_clear(ptep) atomic_swap_long(ptep, 0) 290 #define pte_store(ptep, pte) do { \ 291 *(u_long *)(ptep) = (u_long)(pte); \ 292 } while (0) 293 #define pte_clear(ptep) pte_store(ptep, 0) 294 295 #define pde_store(pdep, pde) pte_store(pdep, pde) 296 297 extern pt_entry_t pg_nx; 298 299 #endif /* _KERNEL */ 300 301 /* 302 * Pmap stuff 303 */ 304 struct pv_entry; 305 struct pv_chunk; 306 307 /* 308 * Locks 309 * (p) PV list lock 310 */ 311 struct md_page { 312 TAILQ_HEAD(, pv_entry) pv_list; /* (p) */ 313 int pv_gen; /* (p) */ 314 int pat_mode; 315 }; 316 317 enum pmap_type { 318 PT_X86, /* regular x86 page tables */ 319 PT_EPT, /* Intel's nested page tables */ 320 PT_RVI, /* AMD's nested page tables */ 321 }; 322 323 struct pmap_pcids { 324 uint32_t pm_pcid; 325 uint32_t pm_gen; 326 }; 327 328 /* 329 * The kernel virtual address (KVA) of the level 4 page table page is always 330 * within the direct map (DMAP) region. 331 */ 332 struct pmap { 333 struct mtx pm_mtx; 334 pml4_entry_t *pm_pml4; /* KVA of level 4 page table */ 335 pml4_entry_t *pm_pml4u; /* KVA of user l4 page table */ 336 uint64_t pm_cr3; 337 uint64_t pm_ucr3; 338 TAILQ_HEAD(,pv_chunk) pm_pvchunk; /* list of mappings in pmap */ 339 cpuset_t pm_active; /* active on cpus */ 340 enum pmap_type pm_type; /* regular or nested tables */ 341 struct pmap_statistics pm_stats; /* pmap statistics */ 342 struct vm_radix pm_root; /* spare page table pages */ 343 long pm_eptgen; /* EPT pmap generation id */ 344 int pm_flags; 345 struct pmap_pcids pm_pcids[MAXCPU]; 346 struct rangeset pm_pkru; 347 }; 348 349 /* flags */ 350 #define PMAP_NESTED_IPIMASK 0xff 351 #define PMAP_PDE_SUPERPAGE (1 << 8) /* supports 2MB superpages */ 352 #define PMAP_EMULATE_AD_BITS (1 << 9) /* needs A/D bits emulation */ 353 #define PMAP_SUPPORTS_EXEC_ONLY (1 << 10) /* execute only mappings ok */ 354 355 typedef struct pmap *pmap_t; 356 357 #ifdef _KERNEL 358 extern struct pmap kernel_pmap_store; 359 #define kernel_pmap (&kernel_pmap_store) 360 361 #define PMAP_LOCK(pmap) mtx_lock(&(pmap)->pm_mtx) 362 #define PMAP_LOCK_ASSERT(pmap, type) \ 363 mtx_assert(&(pmap)->pm_mtx, (type)) 364 #define PMAP_LOCK_DESTROY(pmap) mtx_destroy(&(pmap)->pm_mtx) 365 #define PMAP_LOCK_INIT(pmap) mtx_init(&(pmap)->pm_mtx, "pmap", \ 366 NULL, MTX_DEF | MTX_DUPOK) 367 #define PMAP_LOCKED(pmap) mtx_owned(&(pmap)->pm_mtx) 368 #define PMAP_MTX(pmap) (&(pmap)->pm_mtx) 369 #define PMAP_TRYLOCK(pmap) mtx_trylock(&(pmap)->pm_mtx) 370 #define PMAP_UNLOCK(pmap) mtx_unlock(&(pmap)->pm_mtx) 371 372 int pmap_pinit_type(pmap_t pmap, enum pmap_type pm_type, int flags); 373 int pmap_emulate_accessed_dirty(pmap_t pmap, vm_offset_t va, int ftype); 374 #endif 375 376 /* 377 * For each vm_page_t, there is a list of all currently valid virtual 378 * mappings of that page. An entry is a pv_entry_t, the list is pv_list. 379 */ 380 typedef struct pv_entry { 381 vm_offset_t pv_va; /* virtual address for mapping */ 382 TAILQ_ENTRY(pv_entry) pv_next; 383 } *pv_entry_t; 384 385 /* 386 * pv_entries are allocated in chunks per-process. This avoids the 387 * need to track per-pmap assignments. 388 */ 389 #define _NPCM 3 390 #define _NPCPV 168 391 #define PV_CHUNK_HEADER \ 392 pmap_t pc_pmap; \ 393 TAILQ_ENTRY(pv_chunk) pc_list; \ 394 uint64_t pc_map[_NPCM]; /* bitmap; 1 = free */ \ 395 TAILQ_ENTRY(pv_chunk) pc_lru; 396 397 struct pv_chunk_header { 398 PV_CHUNK_HEADER 399 }; 400 401 struct pv_chunk { 402 PV_CHUNK_HEADER 403 struct pv_entry pc_pventry[_NPCPV]; 404 }; 405 406 #ifdef _KERNEL 407 408 extern caddr_t CADDR1; 409 extern pt_entry_t *CMAP1; 410 extern vm_paddr_t phys_avail[]; 411 extern vm_paddr_t dump_avail[]; 412 extern vm_offset_t virtual_avail; 413 extern vm_offset_t virtual_end; 414 extern vm_paddr_t dmaplimit; 415 extern int pmap_pcid_enabled; 416 extern int invpcid_works; 417 418 #define pmap_page_get_memattr(m) ((vm_memattr_t)(m)->md.pat_mode) 419 #define pmap_page_is_write_mapped(m) (((m)->aflags & PGA_WRITEABLE) != 0) 420 #define pmap_unmapbios(va, sz) pmap_unmapdev((va), (sz)) 421 422 struct thread; 423 424 void pmap_activate_boot(pmap_t pmap); 425 void pmap_activate_sw(struct thread *); 426 void pmap_bootstrap(vm_paddr_t *); 427 int pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde); 428 int pmap_change_attr(vm_offset_t, vm_size_t, int); 429 void pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate); 430 void pmap_flush_cache_range(vm_offset_t, vm_offset_t); 431 void pmap_flush_cache_phys_range(vm_paddr_t, vm_paddr_t, vm_memattr_t); 432 void pmap_init_pat(void); 433 void pmap_kenter(vm_offset_t va, vm_paddr_t pa); 434 void *pmap_kenter_temporary(vm_paddr_t pa, int i); 435 vm_paddr_t pmap_kextract(vm_offset_t); 436 void pmap_kremove(vm_offset_t); 437 int pmap_large_map(vm_paddr_t, vm_size_t, void **, vm_memattr_t); 438 void pmap_large_map_wb(void *sva, vm_size_t len); 439 void pmap_large_unmap(void *sva, vm_size_t len); 440 void *pmap_mapbios(vm_paddr_t, vm_size_t); 441 void *pmap_mapdev(vm_paddr_t, vm_size_t); 442 void *pmap_mapdev_attr(vm_paddr_t, vm_size_t, int); 443 void *pmap_mapdev_pciecfg(vm_paddr_t pa, vm_size_t size); 444 boolean_t pmap_page_is_mapped(vm_page_t m); 445 void pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma); 446 void pmap_pinit_pml4(vm_page_t); 447 bool pmap_ps_enabled(pmap_t pmap); 448 void pmap_unmapdev(vm_offset_t, vm_size_t); 449 void pmap_invalidate_page(pmap_t, vm_offset_t); 450 void pmap_invalidate_range(pmap_t, vm_offset_t, vm_offset_t); 451 void pmap_invalidate_all(pmap_t); 452 void pmap_invalidate_cache(void); 453 void pmap_invalidate_cache_pages(vm_page_t *pages, int count); 454 void pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva); 455 void pmap_force_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva); 456 void pmap_get_mapping(pmap_t pmap, vm_offset_t va, uint64_t *ptr, int *num); 457 boolean_t pmap_map_io_transient(vm_page_t *, vm_offset_t *, int, boolean_t); 458 void pmap_unmap_io_transient(vm_page_t *, vm_offset_t *, int, boolean_t); 459 void pmap_pti_add_kva(vm_offset_t sva, vm_offset_t eva, bool exec); 460 void pmap_pti_remove_kva(vm_offset_t sva, vm_offset_t eva); 461 void pmap_pti_pcid_invalidate(uint64_t ucr3, uint64_t kcr3); 462 void pmap_pti_pcid_invlpg(uint64_t ucr3, uint64_t kcr3, vm_offset_t va); 463 void pmap_pti_pcid_invlrng(uint64_t ucr3, uint64_t kcr3, vm_offset_t sva, 464 vm_offset_t eva); 465 int pmap_pkru_clear(pmap_t pmap, vm_offset_t sva, vm_offset_t eva); 466 int pmap_pkru_set(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 467 u_int keyidx, int flags); 468 int pmap_vmspace_copy(pmap_t dst_pmap, pmap_t src_pmap); 469 #endif /* _KERNEL */ 470 471 /* Return various clipped indexes for a given VA */ 472 static __inline vm_pindex_t 473 pmap_pte_index(vm_offset_t va) 474 { 475 476 return ((va >> PAGE_SHIFT) & ((1ul << NPTEPGSHIFT) - 1)); 477 } 478 479 static __inline vm_pindex_t 480 pmap_pde_index(vm_offset_t va) 481 { 482 483 return ((va >> PDRSHIFT) & ((1ul << NPDEPGSHIFT) - 1)); 484 } 485 486 static __inline vm_pindex_t 487 pmap_pdpe_index(vm_offset_t va) 488 { 489 490 return ((va >> PDPSHIFT) & ((1ul << NPDPEPGSHIFT) - 1)); 491 } 492 493 static __inline vm_pindex_t 494 pmap_pml4e_index(vm_offset_t va) 495 { 496 497 return ((va >> PML4SHIFT) & ((1ul << NPML4EPGSHIFT) - 1)); 498 } 499 500 #endif /* !LOCORE */ 501 502 #endif /* !_MACHINE_PMAP_H_ */ 503