1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) Peter Wemm <peter@netplex.com.au> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifdef __i386__ 30 #include <i386/pcpu.h> 31 #else /* !__i386__ */ 32 33 #ifndef _MACHINE_PCPU_H_ 34 #define _MACHINE_PCPU_H_ 35 36 #include <machine/_pmap.h> 37 #include <machine/segments.h> 38 #include <machine/tss.h> 39 40 #define PC_PTI_STACK_SZ 16 41 42 struct monitorbuf { 43 int idle_state; /* Used by cpu_idle_mwait. */ 44 int stop_state; /* Used by cpustop_handler. */ 45 char padding[128 - (2 * sizeof(int))]; 46 }; 47 _Static_assert(sizeof(struct monitorbuf) == 128, "2x cache line"); 48 49 /* 50 * The SMP parts are setup in pmap.c and locore.s for the BSP, and 51 * mp_machdep.c sets up the data for the AP's to "see" when they awake. 52 * The reason for doing it via a struct is so that an array of pointers 53 * to each CPU's data can be set up for things like "check curproc on all 54 * other processors" 55 */ 56 #define PCPU_MD_FIELDS \ 57 struct monitorbuf pc_monitorbuf __aligned(128); /* cache line */\ 58 struct pcpu *pc_prvspace; /* Self-reference */ \ 59 struct pmap *pc_curpmap; \ 60 struct amd64tss *pc_tssp; /* TSS segment active on CPU */ \ 61 void *pc_pad0; \ 62 uint64_t pc_kcr3; \ 63 uint64_t pc_ucr3; \ 64 uint64_t pc_saved_ucr3; \ 65 register_t pc_rsp0; \ 66 register_t pc_scratch_rsp; /* User %rsp in syscall */ \ 67 register_t pc_scratch_rax; \ 68 u_int pc_apic_id; \ 69 u_int pc_acpi_id; /* ACPI CPU id */ \ 70 /* Pointer to the CPU %fs descriptor */ \ 71 struct user_segment_descriptor *pc_fs32p; \ 72 /* Pointer to the CPU %gs descriptor */ \ 73 struct user_segment_descriptor *pc_gs32p; \ 74 /* Pointer to the CPU LDT descriptor */ \ 75 struct system_segment_descriptor *pc_ldt; \ 76 /* Pointer to the CPU TSS descriptor */ \ 77 struct system_segment_descriptor *pc_tss; \ 78 u_int pc_cmci_mask; /* MCx banks for CMCI */ \ 79 uint64_t pc_dbreg[16]; /* ddb debugging regs */ \ 80 uint64_t pc_pti_stack[PC_PTI_STACK_SZ]; \ 81 register_t pc_pti_rsp0; \ 82 int pc_dbreg_cmd; /* ddb debugging reg cmd */ \ 83 u_int pc_vcpu_id; /* Xen vCPU ID */ \ 84 uint32_t pc_pcid_next; \ 85 uint32_t pc_pcid_gen; \ 86 uint32_t pc_unused; \ 87 uint32_t pc_ibpb_set; \ 88 void *pc_mds_buf; \ 89 void *pc_mds_buf64; \ 90 uint32_t pc_pad[4]; \ 91 uint8_t pc_mds_tmp[64]; \ 92 u_int pc_ipi_bitmap; \ 93 struct amd64tss pc_common_tss; \ 94 struct user_segment_descriptor pc_gdt[NGDT]; \ 95 void *pc_smp_tlb_pmap; \ 96 uint64_t pc_smp_tlb_addr1; \ 97 uint64_t pc_smp_tlb_addr2; \ 98 uint32_t pc_smp_tlb_gen; \ 99 u_int pc_smp_tlb_op; \ 100 uint64_t pc_ucr3_load_mask; \ 101 u_int pc_small_core; \ 102 u_int pc_pcid_invlpg_workaround; \ 103 struct pmap_pcid pc_kpmap_store; \ 104 uint64_t pc_msr_memctl; \ 105 char __pad[2892] /* pad to UMA_PCPU_ALLOC_SIZE */ 106 107 #define PC_DBREG_CMD_NONE 0 108 #define PC_DBREG_CMD_LOAD 1 109 110 #ifdef _KERNEL 111 112 #define MONITOR_STOPSTATE_RUNNING 0 113 #define MONITOR_STOPSTATE_STOPPED 1 114 115 /* 116 * Evaluates to the type of the per-cpu variable name. 117 */ 118 #define __pcpu_type(name) \ 119 __typeof(((struct pcpu *)0)->name) 120 121 #ifdef __SEG_GS 122 #define get_pcpu() __extension__ ({ \ 123 static struct pcpu __seg_gs *__pc = 0; \ 124 \ 125 __pc->pc_prvspace; \ 126 }) 127 128 /* 129 * Evaluates to the address of the per-cpu variable name. 130 */ 131 #define __PCPU_PTR(name) __extension__ ({ \ 132 struct pcpu *__pc = get_pcpu(); \ 133 \ 134 &__pc->name; \ 135 }) 136 137 /* 138 * Evaluates to the value of the per-cpu variable name. 139 */ 140 #define __PCPU_GET(name) __extension__ ({ \ 141 static struct pcpu __seg_gs *__pc = 0; \ 142 \ 143 __pc->name; \ 144 }) 145 146 /* 147 * Adds the value to the per-cpu counter name. The implementation 148 * must be atomic with respect to interrupts. 149 */ 150 #define __PCPU_ADD(name, val) do { \ 151 static struct pcpu __seg_gs *__pc = 0; \ 152 __pcpu_type(name) __val; \ 153 \ 154 __val = (val); \ 155 if (sizeof(__val) == 1 || sizeof(__val) == 2 || \ 156 sizeof(__val) == 4 || sizeof(__val) == 8) { \ 157 __pc->name += __val; \ 158 } else \ 159 *__PCPU_PTR(name) += __val; \ 160 } while (0) 161 162 /* 163 * Sets the value of the per-cpu variable name to value val. 164 */ 165 #define __PCPU_SET(name, val) do { \ 166 static struct pcpu __seg_gs *__pc = 0; \ 167 __pcpu_type(name) __val; \ 168 \ 169 __val = (val); \ 170 if (sizeof(__val) == 1 || sizeof(__val) == 2 || \ 171 sizeof(__val) == 4 || sizeof(__val) == 8) { \ 172 __pc->name = __val; \ 173 } else \ 174 *__PCPU_PTR(name) = __val; \ 175 } while (0) 176 #else /* !__SEG_GS */ 177 /* 178 * Evaluates to the byte offset of the per-cpu variable name. 179 */ 180 #define __pcpu_offset(name) \ 181 __offsetof(struct pcpu, name) 182 183 /* 184 * Evaluates to the address of the per-cpu variable name. 185 */ 186 #define __PCPU_PTR(name) \ 187 (&get_pcpu()->name) 188 189 /* 190 * Evaluates to the value of the per-cpu variable name. 191 */ 192 #define __PCPU_GET(name) __extension__ ({ \ 193 __pcpu_type(name) __res; \ 194 struct __s { \ 195 u_char __b[MIN(sizeof(__pcpu_type(name)), 8)]; \ 196 }; \ 197 \ 198 if (sizeof(__res) == 1 || sizeof(__res) == 2 || \ 199 sizeof(__res) == 4 || sizeof(__res) == 8) { \ 200 __asm __volatile("mov %%gs:%c1,%0" \ 201 : "=r" (*(struct __s *)(void *)&__res) \ 202 : "i" (__pcpu_offset(name))); \ 203 } else { \ 204 __res = *__PCPU_PTR(name); \ 205 } \ 206 __res; \ 207 }) 208 209 /* 210 * Adds the value to the per-cpu counter name. The implementation 211 * must be atomic with respect to interrupts. 212 */ 213 #define __PCPU_ADD(name, val) do { \ 214 __pcpu_type(name) __val; \ 215 struct __s { \ 216 u_char __b[MIN(sizeof(__pcpu_type(name)), 8)]; \ 217 }; \ 218 \ 219 __val = (val); \ 220 if (sizeof(__val) == 1 || sizeof(__val) == 2 || \ 221 sizeof(__val) == 4 || sizeof(__val) == 8) { \ 222 __asm __volatile("add %1,%%gs:%c0" \ 223 : \ 224 : "i" (__pcpu_offset(name)), \ 225 "r" (*(struct __s *)(void *)&__val) \ 226 : "cc", "memory"); \ 227 } else \ 228 *__PCPU_PTR(name) += __val; \ 229 } while (0) 230 231 /* 232 * Sets the value of the per-cpu variable name to value val. 233 */ 234 #define __PCPU_SET(name, val) do { \ 235 __pcpu_type(name) __val; \ 236 struct __s { \ 237 u_char __b[MIN(sizeof(__pcpu_type(name)), 8)]; \ 238 }; \ 239 \ 240 __val = (val); \ 241 if (sizeof(__val) == 1 || sizeof(__val) == 2 || \ 242 sizeof(__val) == 4 || sizeof(__val) == 8) { \ 243 __asm __volatile("mov %1,%%gs:%c0" \ 244 : \ 245 : "i" (__pcpu_offset(name)), \ 246 "r" (*(struct __s *)(void *)&__val) \ 247 : "memory"); \ 248 } else { \ 249 *__PCPU_PTR(name) = __val; \ 250 } \ 251 } while (0) 252 253 #define get_pcpu() __extension__ ({ \ 254 struct pcpu *__pc; \ 255 \ 256 __asm __volatile("movq %%gs:%c1,%0" \ 257 : "=r" (__pc) \ 258 : "i" (__pcpu_offset(pc_prvspace))); \ 259 __pc; \ 260 }) 261 #endif /* !__SEG_GS */ 262 263 #define PCPU_GET(member) __PCPU_GET(pc_ ## member) 264 #define PCPU_ADD(member, val) __PCPU_ADD(pc_ ## member, val) 265 #define PCPU_PTR(member) __PCPU_PTR(pc_ ## member) 266 #define PCPU_SET(member, val) __PCPU_SET(pc_ ## member, val) 267 268 #define IS_BSP() (PCPU_GET(cpuid) == 0) 269 270 #define zpcpu_offset_cpu(cpu) ((uintptr_t)&__pcpu[0] + UMA_PCPU_ALLOC_SIZE * cpu) 271 #define zpcpu_base_to_offset(base) (void *)((uintptr_t)(base) - (uintptr_t)&__pcpu[0]) 272 #define zpcpu_offset_to_base(base) (void *)((uintptr_t)(base) + (uintptr_t)&__pcpu[0]) 273 274 #define zpcpu_sub_protected(base, n) do { \ 275 ZPCPU_ASSERT_PROTECTED(); \ 276 zpcpu_sub(base, n); \ 277 } while (0) 278 279 #define zpcpu_set_protected(base, n) do { \ 280 __typeof(*base) __n = (n); \ 281 ZPCPU_ASSERT_PROTECTED(); \ 282 switch (sizeof(*base)) { \ 283 case 4: \ 284 __asm __volatile("movl\t%1,%%gs:(%0)" \ 285 : : "r" (base), "ri" (__n) : "memory", "cc"); \ 286 break; \ 287 case 8: \ 288 __asm __volatile("movq\t%1,%%gs:(%0)" \ 289 : : "r" (base), "ri" (__n) : "memory", "cc"); \ 290 break; \ 291 default: \ 292 *zpcpu_get(base) = __n; \ 293 } \ 294 } while (0); 295 296 #define zpcpu_add(base, n) do { \ 297 __typeof(*base) __n = (n); \ 298 CTASSERT(sizeof(*base) == 4 || sizeof(*base) == 8); \ 299 switch (sizeof(*base)) { \ 300 case 4: \ 301 __asm __volatile("addl\t%1,%%gs:(%0)" \ 302 : : "r" (base), "ri" (__n) : "memory", "cc"); \ 303 break; \ 304 case 8: \ 305 __asm __volatile("addq\t%1,%%gs:(%0)" \ 306 : : "r" (base), "ri" (__n) : "memory", "cc"); \ 307 break; \ 308 } \ 309 } while (0) 310 311 #define zpcpu_add_protected(base, n) do { \ 312 ZPCPU_ASSERT_PROTECTED(); \ 313 zpcpu_add(base, n); \ 314 } while (0) 315 316 #define zpcpu_sub(base, n) do { \ 317 __typeof(*base) __n = (n); \ 318 CTASSERT(sizeof(*base) == 4 || sizeof(*base) == 8); \ 319 switch (sizeof(*base)) { \ 320 case 4: \ 321 __asm __volatile("subl\t%1,%%gs:(%0)" \ 322 : : "r" (base), "ri" (__n) : "memory", "cc"); \ 323 break; \ 324 case 8: \ 325 __asm __volatile("subq\t%1,%%gs:(%0)" \ 326 : : "r" (base), "ri" (__n) : "memory", "cc"); \ 327 break; \ 328 } \ 329 } while (0); 330 331 #endif /* _KERNEL */ 332 333 #endif /* !_MACHINE_PCPU_H_ */ 334 335 #endif /* __i386__ */ 336