1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) Peter Wemm <peter@netplex.com.au> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #ifdef __i386__ 32 #include <i386/pcpu.h> 33 #else /* !__i386__ */ 34 35 #ifndef _MACHINE_PCPU_H_ 36 #define _MACHINE_PCPU_H_ 37 38 #include <machine/_pmap.h> 39 #include <machine/segments.h> 40 #include <machine/tss.h> 41 42 #define PC_PTI_STACK_SZ 16 43 44 struct monitorbuf { 45 int idle_state; /* Used by cpu_idle_mwait. */ 46 int stop_state; /* Used by cpustop_handler. */ 47 char padding[128 - (2 * sizeof(int))]; 48 }; 49 _Static_assert(sizeof(struct monitorbuf) == 128, "2x cache line"); 50 51 /* 52 * The SMP parts are setup in pmap.c and locore.s for the BSP, and 53 * mp_machdep.c sets up the data for the AP's to "see" when they awake. 54 * The reason for doing it via a struct is so that an array of pointers 55 * to each CPU's data can be set up for things like "check curproc on all 56 * other processors" 57 */ 58 #define PCPU_MD_FIELDS \ 59 struct monitorbuf pc_monitorbuf __aligned(128); /* cache line */\ 60 struct pcpu *pc_prvspace; /* Self-reference */ \ 61 struct pmap *pc_curpmap; \ 62 struct amd64tss *pc_tssp; /* TSS segment active on CPU */ \ 63 void *pc_pad0; \ 64 uint64_t pc_kcr3; \ 65 uint64_t pc_ucr3; \ 66 uint64_t pc_saved_ucr3; \ 67 register_t pc_rsp0; \ 68 register_t pc_scratch_rsp; /* User %rsp in syscall */ \ 69 register_t pc_scratch_rax; \ 70 u_int pc_apic_id; \ 71 u_int pc_acpi_id; /* ACPI CPU id */ \ 72 /* Pointer to the CPU %fs descriptor */ \ 73 struct user_segment_descriptor *pc_fs32p; \ 74 /* Pointer to the CPU %gs descriptor */ \ 75 struct user_segment_descriptor *pc_gs32p; \ 76 /* Pointer to the CPU LDT descriptor */ \ 77 struct system_segment_descriptor *pc_ldt; \ 78 /* Pointer to the CPU TSS descriptor */ \ 79 struct system_segment_descriptor *pc_tss; \ 80 u_int pc_cmci_mask; /* MCx banks for CMCI */ \ 81 uint64_t pc_dbreg[16]; /* ddb debugging regs */ \ 82 uint64_t pc_pti_stack[PC_PTI_STACK_SZ]; \ 83 register_t pc_pti_rsp0; \ 84 int pc_dbreg_cmd; /* ddb debugging reg cmd */ \ 85 u_int pc_vcpu_id; /* Xen vCPU ID */ \ 86 uint32_t pc_pcid_next; \ 87 uint32_t pc_pcid_gen; \ 88 uint32_t pc_unused; \ 89 uint32_t pc_ibpb_set; \ 90 void *pc_mds_buf; \ 91 void *pc_mds_buf64; \ 92 uint32_t pc_pad[4]; \ 93 uint8_t pc_mds_tmp[64]; \ 94 u_int pc_ipi_bitmap; \ 95 struct amd64tss pc_common_tss; \ 96 struct user_segment_descriptor pc_gdt[NGDT]; \ 97 void *pc_smp_tlb_pmap; \ 98 uint64_t pc_smp_tlb_addr1; \ 99 uint64_t pc_smp_tlb_addr2; \ 100 uint32_t pc_smp_tlb_gen; \ 101 u_int pc_smp_tlb_op; \ 102 uint64_t pc_ucr3_load_mask; \ 103 u_int pc_small_core; \ 104 u_int pc_pcid_invlpg_workaround; \ 105 struct pmap_pcid pc_kpmap_store; \ 106 char __pad[2900] /* pad to UMA_PCPU_ALLOC_SIZE */ 107 108 #define PC_DBREG_CMD_NONE 0 109 #define PC_DBREG_CMD_LOAD 1 110 111 #ifdef _KERNEL 112 113 #define MONITOR_STOPSTATE_RUNNING 0 114 #define MONITOR_STOPSTATE_STOPPED 1 115 116 /* 117 * Evaluates to the byte offset of the per-cpu variable name. 118 */ 119 #define __pcpu_offset(name) \ 120 __offsetof(struct pcpu, name) 121 122 /* 123 * Evaluates to the type of the per-cpu variable name. 124 */ 125 #define __pcpu_type(name) \ 126 __typeof(((struct pcpu *)0)->name) 127 128 /* 129 * Evaluates to the address of the per-cpu variable name. 130 */ 131 #define __PCPU_PTR(name) __extension__ ({ \ 132 __pcpu_type(name) *__p; \ 133 \ 134 __asm __volatile("movq %%gs:%1,%0; addq %2,%0" \ 135 : "=r" (__p) \ 136 : "m" (*(struct pcpu *)(__pcpu_offset(pc_prvspace))), \ 137 "i" (__pcpu_offset(name))); \ 138 \ 139 __p; \ 140 }) 141 142 /* 143 * Evaluates to the value of the per-cpu variable name. 144 */ 145 #define __PCPU_GET(name) __extension__ ({ \ 146 __pcpu_type(name) __res; \ 147 struct __s { \ 148 u_char __b[MIN(sizeof(__pcpu_type(name)), 8)]; \ 149 } __s; \ 150 \ 151 if (sizeof(__res) == 1 || sizeof(__res) == 2 || \ 152 sizeof(__res) == 4 || sizeof(__res) == 8) { \ 153 __asm __volatile("mov %%gs:%1,%0" \ 154 : "=r" (__s) \ 155 : "m" (*(struct __s *)(__pcpu_offset(name)))); \ 156 *(struct __s *)(void *)&__res = __s; \ 157 } else { \ 158 __res = *__PCPU_PTR(name); \ 159 } \ 160 __res; \ 161 }) 162 163 /* 164 * Adds the value to the per-cpu counter name. The implementation 165 * must be atomic with respect to interrupts. 166 */ 167 #define __PCPU_ADD(name, val) do { \ 168 __pcpu_type(name) __val; \ 169 struct __s { \ 170 u_char __b[MIN(sizeof(__pcpu_type(name)), 8)]; \ 171 } __s; \ 172 \ 173 __val = (val); \ 174 if (sizeof(__val) == 1 || sizeof(__val) == 2 || \ 175 sizeof(__val) == 4 || sizeof(__val) == 8) { \ 176 __s = *(struct __s *)(void *)&__val; \ 177 __asm __volatile("add %1,%%gs:%0" \ 178 : "=m" (*(struct __s *)(__pcpu_offset(name))) \ 179 : "r" (__s)); \ 180 } else \ 181 *__PCPU_PTR(name) += __val; \ 182 } while (0) 183 184 /* 185 * Sets the value of the per-cpu variable name to value val. 186 */ 187 #define __PCPU_SET(name, val) { \ 188 __pcpu_type(name) __val; \ 189 struct __s { \ 190 u_char __b[MIN(sizeof(__pcpu_type(name)), 8)]; \ 191 } __s; \ 192 \ 193 __val = (val); \ 194 if (sizeof(__val) == 1 || sizeof(__val) == 2 || \ 195 sizeof(__val) == 4 || sizeof(__val) == 8) { \ 196 __s = *(struct __s *)(void *)&__val; \ 197 __asm __volatile("mov %1,%%gs:%0" \ 198 : "=m" (*(struct __s *)(__pcpu_offset(name))) \ 199 : "r" (__s)); \ 200 } else { \ 201 *__PCPU_PTR(name) = __val; \ 202 } \ 203 } 204 205 #define get_pcpu() __extension__ ({ \ 206 struct pcpu *__pc; \ 207 \ 208 __asm __volatile("movq %%gs:%1,%0" \ 209 : "=r" (__pc) \ 210 : "m" (*(struct pcpu *)(__pcpu_offset(pc_prvspace)))); \ 211 __pc; \ 212 }) 213 214 #define PCPU_GET(member) __PCPU_GET(pc_ ## member) 215 #define PCPU_ADD(member, val) __PCPU_ADD(pc_ ## member, val) 216 #define PCPU_PTR(member) __PCPU_PTR(pc_ ## member) 217 #define PCPU_SET(member, val) __PCPU_SET(pc_ ## member, val) 218 219 #define IS_BSP() (PCPU_GET(cpuid) == 0) 220 221 #define zpcpu_offset_cpu(cpu) ((uintptr_t)&__pcpu[0] + UMA_PCPU_ALLOC_SIZE * cpu) 222 #define zpcpu_base_to_offset(base) (void *)((uintptr_t)(base) - (uintptr_t)&__pcpu[0]) 223 #define zpcpu_offset_to_base(base) (void *)((uintptr_t)(base) + (uintptr_t)&__pcpu[0]) 224 225 #define zpcpu_sub_protected(base, n) do { \ 226 ZPCPU_ASSERT_PROTECTED(); \ 227 zpcpu_sub(base, n); \ 228 } while (0) 229 230 #define zpcpu_set_protected(base, n) do { \ 231 __typeof(*base) __n = (n); \ 232 ZPCPU_ASSERT_PROTECTED(); \ 233 switch (sizeof(*base)) { \ 234 case 4: \ 235 __asm __volatile("movl\t%1,%%gs:(%0)" \ 236 : : "r" (base), "ri" (__n) : "memory", "cc"); \ 237 break; \ 238 case 8: \ 239 __asm __volatile("movq\t%1,%%gs:(%0)" \ 240 : : "r" (base), "ri" (__n) : "memory", "cc"); \ 241 break; \ 242 default: \ 243 *zpcpu_get(base) = __n; \ 244 } \ 245 } while (0); 246 247 #define zpcpu_add(base, n) do { \ 248 __typeof(*base) __n = (n); \ 249 CTASSERT(sizeof(*base) == 4 || sizeof(*base) == 8); \ 250 switch (sizeof(*base)) { \ 251 case 4: \ 252 __asm __volatile("addl\t%1,%%gs:(%0)" \ 253 : : "r" (base), "ri" (__n) : "memory", "cc"); \ 254 break; \ 255 case 8: \ 256 __asm __volatile("addq\t%1,%%gs:(%0)" \ 257 : : "r" (base), "ri" (__n) : "memory", "cc"); \ 258 break; \ 259 } \ 260 } while (0) 261 262 #define zpcpu_add_protected(base, n) do { \ 263 ZPCPU_ASSERT_PROTECTED(); \ 264 zpcpu_add(base, n); \ 265 } while (0) 266 267 #define zpcpu_sub(base, n) do { \ 268 __typeof(*base) __n = (n); \ 269 CTASSERT(sizeof(*base) == 4 || sizeof(*base) == 8); \ 270 switch (sizeof(*base)) { \ 271 case 4: \ 272 __asm __volatile("subl\t%1,%%gs:(%0)" \ 273 : : "r" (base), "ri" (__n) : "memory", "cc"); \ 274 break; \ 275 case 8: \ 276 __asm __volatile("subq\t%1,%%gs:(%0)" \ 277 : : "r" (base), "ri" (__n) : "memory", "cc"); \ 278 break; \ 279 } \ 280 } while (0); 281 282 #endif /* _KERNEL */ 283 284 #endif /* !_MACHINE_PCPU_H_ */ 285 286 #endif /* __i386__ */ 287