1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) Peter Wemm <peter@netplex.com.au> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #ifdef __i386__ 32 #include <i386/pcpu.h> 33 #else /* !__i386__ */ 34 35 #ifndef _MACHINE_PCPU_H_ 36 #define _MACHINE_PCPU_H_ 37 38 #include <machine/_pmap.h> 39 #include <machine/segments.h> 40 #include <machine/tss.h> 41 42 #define PC_PTI_STACK_SZ 16 43 44 struct monitorbuf { 45 int idle_state; /* Used by cpu_idle_mwait. */ 46 int stop_state; /* Used by cpustop_handler. */ 47 char padding[128 - (2 * sizeof(int))]; 48 }; 49 _Static_assert(sizeof(struct monitorbuf) == 128, "2x cache line"); 50 51 /* 52 * The SMP parts are setup in pmap.c and locore.s for the BSP, and 53 * mp_machdep.c sets up the data for the AP's to "see" when they awake. 54 * The reason for doing it via a struct is so that an array of pointers 55 * to each CPU's data can be set up for things like "check curproc on all 56 * other processors" 57 */ 58 #define PCPU_MD_FIELDS \ 59 struct monitorbuf pc_monitorbuf __aligned(128); /* cache line */\ 60 struct pcpu *pc_prvspace; /* Self-reference */ \ 61 struct pmap *pc_curpmap; \ 62 struct amd64tss *pc_tssp; /* TSS segment active on CPU */ \ 63 void *pc_pad0; \ 64 uint64_t pc_kcr3; \ 65 uint64_t pc_ucr3; \ 66 uint64_t pc_saved_ucr3; \ 67 register_t pc_rsp0; \ 68 register_t pc_scratch_rsp; /* User %rsp in syscall */ \ 69 register_t pc_scratch_rax; \ 70 u_int pc_apic_id; \ 71 u_int pc_acpi_id; /* ACPI CPU id */ \ 72 /* Pointer to the CPU %fs descriptor */ \ 73 struct user_segment_descriptor *pc_fs32p; \ 74 /* Pointer to the CPU %gs descriptor */ \ 75 struct user_segment_descriptor *pc_gs32p; \ 76 /* Pointer to the CPU LDT descriptor */ \ 77 struct system_segment_descriptor *pc_ldt; \ 78 /* Pointer to the CPU TSS descriptor */ \ 79 struct system_segment_descriptor *pc_tss; \ 80 u_int pc_cmci_mask; /* MCx banks for CMCI */ \ 81 uint64_t pc_dbreg[16]; /* ddb debugging regs */ \ 82 uint64_t pc_pti_stack[PC_PTI_STACK_SZ]; \ 83 register_t pc_pti_rsp0; \ 84 int pc_dbreg_cmd; /* ddb debugging reg cmd */ \ 85 u_int pc_vcpu_id; /* Xen vCPU ID */ \ 86 uint32_t pc_pcid_next; \ 87 uint32_t pc_pcid_gen; \ 88 uint32_t pc_unused; \ 89 uint32_t pc_ibpb_set; \ 90 void *pc_mds_buf; \ 91 void *pc_mds_buf64; \ 92 uint32_t pc_pad[4]; \ 93 uint8_t pc_mds_tmp[64]; \ 94 u_int pc_ipi_bitmap; \ 95 struct amd64tss pc_common_tss; \ 96 struct user_segment_descriptor pc_gdt[NGDT]; \ 97 void *pc_smp_tlb_pmap; \ 98 uint64_t pc_smp_tlb_addr1; \ 99 uint64_t pc_smp_tlb_addr2; \ 100 uint32_t pc_smp_tlb_gen; \ 101 u_int pc_smp_tlb_op; \ 102 uint64_t pc_ucr3_load_mask; \ 103 u_int pc_small_core; \ 104 u_int pc_pcid_invlpg_workaround; \ 105 struct pmap_pcid pc_kpmap_store; \ 106 char __pad[2900] /* pad to UMA_PCPU_ALLOC_SIZE */ 107 108 #define PC_DBREG_CMD_NONE 0 109 #define PC_DBREG_CMD_LOAD 1 110 111 #ifdef _KERNEL 112 113 #define MONITOR_STOPSTATE_RUNNING 0 114 #define MONITOR_STOPSTATE_STOPPED 1 115 116 /* 117 * Evaluates to the type of the per-cpu variable name. 118 */ 119 #define __pcpu_type(name) \ 120 __typeof(((struct pcpu *)0)->name) 121 122 #ifdef __SEG_GS 123 #define get_pcpu() __extension__ ({ \ 124 static struct pcpu __seg_gs *__pc = 0; \ 125 \ 126 __pc->pc_prvspace; \ 127 }) 128 129 /* 130 * Evaluates to the address of the per-cpu variable name. 131 */ 132 #define __PCPU_PTR(name) __extension__ ({ \ 133 struct pcpu *__pc = get_pcpu(); \ 134 \ 135 &__pc->name; \ 136 }) 137 138 /* 139 * Evaluates to the value of the per-cpu variable name. 140 */ 141 #define __PCPU_GET(name) __extension__ ({ \ 142 static struct pcpu __seg_gs *__pc = 0; \ 143 \ 144 __pc->name; \ 145 }) 146 147 /* 148 * Adds the value to the per-cpu counter name. The implementation 149 * must be atomic with respect to interrupts. 150 */ 151 #define __PCPU_ADD(name, val) do { \ 152 static struct pcpu __seg_gs *__pc = 0; \ 153 __pcpu_type(name) __val; \ 154 \ 155 __val = (val); \ 156 if (sizeof(__val) == 1 || sizeof(__val) == 2 || \ 157 sizeof(__val) == 4 || sizeof(__val) == 8) { \ 158 __pc->name += __val; \ 159 } else \ 160 *__PCPU_PTR(name) += __val; \ 161 } while (0) 162 163 /* 164 * Sets the value of the per-cpu variable name to value val. 165 */ 166 #define __PCPU_SET(name, val) do { \ 167 static struct pcpu __seg_gs *__pc = 0; \ 168 __pcpu_type(name) __val; \ 169 \ 170 __val = (val); \ 171 if (sizeof(__val) == 1 || sizeof(__val) == 2 || \ 172 sizeof(__val) == 4 || sizeof(__val) == 8) { \ 173 __pc->name = __val; \ 174 } else \ 175 *__PCPU_PTR(name) = __val; \ 176 } while (0) 177 #else /* !__SEG_GS */ 178 /* 179 * Evaluates to the byte offset of the per-cpu variable name. 180 */ 181 #define __pcpu_offset(name) \ 182 __offsetof(struct pcpu, name) 183 184 /* 185 * Evaluates to the address of the per-cpu variable name. 186 */ 187 #define __PCPU_PTR(name) __extension__ ({ \ 188 __pcpu_type(name) *__p; \ 189 \ 190 __asm __volatile("movq %%gs:%1,%0; addq %2,%0" \ 191 : "=r" (__p) \ 192 : "m" (*(struct pcpu *)(__pcpu_offset(pc_prvspace))), \ 193 "i" (__pcpu_offset(name))); \ 194 \ 195 __p; \ 196 }) 197 198 /* 199 * Evaluates to the value of the per-cpu variable name. 200 */ 201 #define __PCPU_GET(name) __extension__ ({ \ 202 __pcpu_type(name) __res; \ 203 struct __s { \ 204 u_char __b[MIN(sizeof(__pcpu_type(name)), 8)]; \ 205 } __s; \ 206 \ 207 if (sizeof(__res) == 1 || sizeof(__res) == 2 || \ 208 sizeof(__res) == 4 || sizeof(__res) == 8) { \ 209 __asm __volatile("mov %%gs:%1,%0" \ 210 : "=r" (__s) \ 211 : "m" (*(struct __s *)(__pcpu_offset(name)))); \ 212 *(struct __s *)(void *)&__res = __s; \ 213 } else { \ 214 __res = *__PCPU_PTR(name); \ 215 } \ 216 __res; \ 217 }) 218 219 /* 220 * Adds the value to the per-cpu counter name. The implementation 221 * must be atomic with respect to interrupts. 222 */ 223 #define __PCPU_ADD(name, val) do { \ 224 __pcpu_type(name) __val; \ 225 struct __s { \ 226 u_char __b[MIN(sizeof(__pcpu_type(name)), 8)]; \ 227 } __s; \ 228 \ 229 __val = (val); \ 230 if (sizeof(__val) == 1 || sizeof(__val) == 2 || \ 231 sizeof(__val) == 4 || sizeof(__val) == 8) { \ 232 __s = *(struct __s *)(void *)&__val; \ 233 __asm __volatile("add %1,%%gs:%0" \ 234 : "=m" (*(struct __s *)(__pcpu_offset(name))) \ 235 : "r" (__s)); \ 236 } else \ 237 *__PCPU_PTR(name) += __val; \ 238 } while (0) 239 240 /* 241 * Sets the value of the per-cpu variable name to value val. 242 */ 243 #define __PCPU_SET(name, val) { \ 244 __pcpu_type(name) __val; \ 245 struct __s { \ 246 u_char __b[MIN(sizeof(__pcpu_type(name)), 8)]; \ 247 } __s; \ 248 \ 249 __val = (val); \ 250 if (sizeof(__val) == 1 || sizeof(__val) == 2 || \ 251 sizeof(__val) == 4 || sizeof(__val) == 8) { \ 252 __s = *(struct __s *)(void *)&__val; \ 253 __asm __volatile("mov %1,%%gs:%0" \ 254 : "=m" (*(struct __s *)(__pcpu_offset(name))) \ 255 : "r" (__s)); \ 256 } else { \ 257 *__PCPU_PTR(name) = __val; \ 258 } \ 259 } 260 261 #define get_pcpu() __extension__ ({ \ 262 struct pcpu *__pc; \ 263 \ 264 __asm __volatile("movq %%gs:%1,%0" \ 265 : "=r" (__pc) \ 266 : "m" (*(struct pcpu *)(__pcpu_offset(pc_prvspace)))); \ 267 __pc; \ 268 }) 269 #endif /* !__SEG_GS */ 270 271 #define PCPU_GET(member) __PCPU_GET(pc_ ## member) 272 #define PCPU_ADD(member, val) __PCPU_ADD(pc_ ## member, val) 273 #define PCPU_PTR(member) __PCPU_PTR(pc_ ## member) 274 #define PCPU_SET(member, val) __PCPU_SET(pc_ ## member, val) 275 276 #define IS_BSP() (PCPU_GET(cpuid) == 0) 277 278 #define zpcpu_offset_cpu(cpu) ((uintptr_t)&__pcpu[0] + UMA_PCPU_ALLOC_SIZE * cpu) 279 #define zpcpu_base_to_offset(base) (void *)((uintptr_t)(base) - (uintptr_t)&__pcpu[0]) 280 #define zpcpu_offset_to_base(base) (void *)((uintptr_t)(base) + (uintptr_t)&__pcpu[0]) 281 282 #define zpcpu_sub_protected(base, n) do { \ 283 ZPCPU_ASSERT_PROTECTED(); \ 284 zpcpu_sub(base, n); \ 285 } while (0) 286 287 #define zpcpu_set_protected(base, n) do { \ 288 __typeof(*base) __n = (n); \ 289 ZPCPU_ASSERT_PROTECTED(); \ 290 switch (sizeof(*base)) { \ 291 case 4: \ 292 __asm __volatile("movl\t%1,%%gs:(%0)" \ 293 : : "r" (base), "ri" (__n) : "memory", "cc"); \ 294 break; \ 295 case 8: \ 296 __asm __volatile("movq\t%1,%%gs:(%0)" \ 297 : : "r" (base), "ri" (__n) : "memory", "cc"); \ 298 break; \ 299 default: \ 300 *zpcpu_get(base) = __n; \ 301 } \ 302 } while (0); 303 304 #define zpcpu_add(base, n) do { \ 305 __typeof(*base) __n = (n); \ 306 CTASSERT(sizeof(*base) == 4 || sizeof(*base) == 8); \ 307 switch (sizeof(*base)) { \ 308 case 4: \ 309 __asm __volatile("addl\t%1,%%gs:(%0)" \ 310 : : "r" (base), "ri" (__n) : "memory", "cc"); \ 311 break; \ 312 case 8: \ 313 __asm __volatile("addq\t%1,%%gs:(%0)" \ 314 : : "r" (base), "ri" (__n) : "memory", "cc"); \ 315 break; \ 316 } \ 317 } while (0) 318 319 #define zpcpu_add_protected(base, n) do { \ 320 ZPCPU_ASSERT_PROTECTED(); \ 321 zpcpu_add(base, n); \ 322 } while (0) 323 324 #define zpcpu_sub(base, n) do { \ 325 __typeof(*base) __n = (n); \ 326 CTASSERT(sizeof(*base) == 4 || sizeof(*base) == 8); \ 327 switch (sizeof(*base)) { \ 328 case 4: \ 329 __asm __volatile("subl\t%1,%%gs:(%0)" \ 330 : : "r" (base), "ri" (__n) : "memory", "cc"); \ 331 break; \ 332 case 8: \ 333 __asm __volatile("subq\t%1,%%gs:(%0)" \ 334 : : "r" (base), "ri" (__n) : "memory", "cc"); \ 335 break; \ 336 } \ 337 } while (0); 338 339 #endif /* _KERNEL */ 340 341 #endif /* !_MACHINE_PCPU_H_ */ 342 343 #endif /* __i386__ */ 344