xref: /freebsd/sys/amd64/include/pcpu.h (revision 1f1e2261e341e6ca6862f82261066ef1705f0a7a)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3  *
4  * Copyright (c) Peter Wemm <peter@netplex.com.au>
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  *
28  * $FreeBSD$
29  */
30 
31 #ifdef __i386__
32 #include <i386/pcpu.h>
33 #else /* !__i386__ */
34 
35 #ifndef _MACHINE_PCPU_H_
36 #define	_MACHINE_PCPU_H_
37 
38 #include <machine/segments.h>
39 #include <machine/tss.h>
40 
41 #define	PC_PTI_STACK_SZ	16
42 
43 struct monitorbuf {
44 	int idle_state;		/* Used by cpu_idle_mwait. */
45 	int stop_state;		/* Used by cpustop_handler. */
46 	char padding[128 - (2 * sizeof(int))];
47 };
48 _Static_assert(sizeof(struct monitorbuf) == 128, "2x cache line");
49 
50 /*
51  * The SMP parts are setup in pmap.c and locore.s for the BSP, and
52  * mp_machdep.c sets up the data for the AP's to "see" when they awake.
53  * The reason for doing it via a struct is so that an array of pointers
54  * to each CPU's data can be set up for things like "check curproc on all
55  * other processors"
56  */
57 #define	PCPU_MD_FIELDS							\
58 	struct monitorbuf pc_monitorbuf __aligned(128);	/* cache line */\
59 	struct	pcpu *pc_prvspace;	/* Self-reference */		\
60 	struct	pmap *pc_curpmap;					\
61 	struct	amd64tss *pc_tssp;	/* TSS segment active on CPU */	\
62 	void	*pc_pad0;						\
63 	uint64_t pc_kcr3;						\
64 	uint64_t pc_ucr3;						\
65 	uint64_t pc_saved_ucr3;						\
66 	register_t pc_rsp0;						\
67 	register_t pc_scratch_rsp;	/* User %rsp in syscall */	\
68 	register_t pc_scratch_rax;					\
69 	u_int	pc_apic_id;						\
70 	u_int   pc_acpi_id;		/* ACPI CPU id */		\
71 	/* Pointer to the CPU %fs descriptor */				\
72 	struct user_segment_descriptor	*pc_fs32p;			\
73 	/* Pointer to the CPU %gs descriptor */				\
74 	struct user_segment_descriptor	*pc_gs32p;			\
75 	/* Pointer to the CPU LDT descriptor */				\
76 	struct system_segment_descriptor *pc_ldt;			\
77 	/* Pointer to the CPU TSS descriptor */				\
78 	struct system_segment_descriptor *pc_tss;			\
79 	u_int	pc_cmci_mask;		/* MCx banks for CMCI */	\
80 	uint64_t pc_dbreg[16];		/* ddb debugging regs */	\
81 	uint64_t pc_pti_stack[PC_PTI_STACK_SZ];				\
82 	register_t pc_pti_rsp0;						\
83 	int pc_dbreg_cmd;		/* ddb debugging reg cmd */	\
84 	u_int	pc_vcpu_id;		/* Xen vCPU ID */		\
85 	uint32_t pc_pcid_next;						\
86 	uint32_t pc_pcid_gen;						\
87 	uint32_t pc_unused;						\
88 	uint32_t pc_ibpb_set;						\
89 	void	*pc_mds_buf;						\
90 	void	*pc_mds_buf64;						\
91 	uint32_t pc_pad[4];						\
92 	uint8_t	pc_mds_tmp[64];						\
93 	u_int 	pc_ipi_bitmap;						\
94 	struct amd64tss pc_common_tss;					\
95 	struct user_segment_descriptor pc_gdt[NGDT];			\
96 	void	*pc_smp_tlb_pmap;					\
97 	uint64_t pc_smp_tlb_addr1;					\
98 	uint64_t pc_smp_tlb_addr2;					\
99 	uint32_t pc_smp_tlb_gen;					\
100 	u_int	pc_smp_tlb_op;						\
101 	uint64_t pc_ucr3_load_mask;					\
102 	char	__pad[2916]		/* pad to UMA_PCPU_ALLOC_SIZE */
103 
104 #define	PC_DBREG_CMD_NONE	0
105 #define	PC_DBREG_CMD_LOAD	1
106 
107 #ifdef _KERNEL
108 
109 #define MONITOR_STOPSTATE_RUNNING	0
110 #define MONITOR_STOPSTATE_STOPPED	1
111 
112 /*
113  * Evaluates to the byte offset of the per-cpu variable name.
114  */
115 #define	__pcpu_offset(name)						\
116 	__offsetof(struct pcpu, name)
117 
118 /*
119  * Evaluates to the type of the per-cpu variable name.
120  */
121 #define	__pcpu_type(name)						\
122 	__typeof(((struct pcpu *)0)->name)
123 
124 /*
125  * Evaluates to the address of the per-cpu variable name.
126  */
127 #define	__PCPU_PTR(name) __extension__ ({				\
128 	__pcpu_type(name) *__p;						\
129 									\
130 	__asm __volatile("movq %%gs:%1,%0; addq %2,%0"			\
131 	    : "=r" (__p)						\
132 	    : "m" (*(struct pcpu *)(__pcpu_offset(pc_prvspace))),	\
133 	      "i" (__pcpu_offset(name)));				\
134 									\
135 	__p;								\
136 })
137 
138 /*
139  * Evaluates to the value of the per-cpu variable name.
140  */
141 #define	__PCPU_GET(name) __extension__ ({				\
142 	__pcpu_type(name) __res;					\
143 	struct __s {							\
144 		u_char	__b[MIN(sizeof(__pcpu_type(name)), 8)];		\
145 	} __s;								\
146 									\
147 	if (sizeof(__res) == 1 || sizeof(__res) == 2 ||			\
148 	    sizeof(__res) == 4 || sizeof(__res) == 8) {			\
149 		__asm __volatile("mov %%gs:%1,%0"			\
150 		    : "=r" (__s)					\
151 		    : "m" (*(struct __s *)(__pcpu_offset(name))));	\
152 		*(struct __s *)(void *)&__res = __s;			\
153 	} else {							\
154 		__res = *__PCPU_PTR(name);				\
155 	}								\
156 	__res;								\
157 })
158 
159 /*
160  * Adds the value to the per-cpu counter name.  The implementation
161  * must be atomic with respect to interrupts.
162  */
163 #define	__PCPU_ADD(name, val) do {					\
164 	__pcpu_type(name) __val;					\
165 	struct __s {							\
166 		u_char	__b[MIN(sizeof(__pcpu_type(name)), 8)];		\
167 	} __s;								\
168 									\
169 	__val = (val);							\
170 	if (sizeof(__val) == 1 || sizeof(__val) == 2 ||			\
171 	    sizeof(__val) == 4 || sizeof(__val) == 8) {			\
172 		__s = *(struct __s *)(void *)&__val;			\
173 		__asm __volatile("add %1,%%gs:%0"			\
174 		    : "=m" (*(struct __s *)(__pcpu_offset(name)))	\
175 		    : "r" (__s));					\
176 	} else								\
177 		*__PCPU_PTR(name) += __val;				\
178 } while (0)
179 
180 /*
181  * Sets the value of the per-cpu variable name to value val.
182  */
183 #define	__PCPU_SET(name, val) {						\
184 	__pcpu_type(name) __val;					\
185 	struct __s {							\
186 		u_char	__b[MIN(sizeof(__pcpu_type(name)), 8)];		\
187 	} __s;								\
188 									\
189 	__val = (val);							\
190 	if (sizeof(__val) == 1 || sizeof(__val) == 2 ||			\
191 	    sizeof(__val) == 4 || sizeof(__val) == 8) {			\
192 		__s = *(struct __s *)(void *)&__val;			\
193 		__asm __volatile("mov %1,%%gs:%0"			\
194 		    : "=m" (*(struct __s *)(__pcpu_offset(name)))	\
195 		    : "r" (__s));					\
196 	} else {							\
197 		*__PCPU_PTR(name) = __val;				\
198 	}								\
199 }
200 
201 #define	get_pcpu() __extension__ ({					\
202 	struct pcpu *__pc;						\
203 									\
204 	__asm __volatile("movq %%gs:%1,%0"				\
205 	    : "=r" (__pc)						\
206 	    : "m" (*(struct pcpu *)(__pcpu_offset(pc_prvspace))));	\
207 	__pc;								\
208 })
209 
210 #define	PCPU_GET(member)	__PCPU_GET(pc_ ## member)
211 #define	PCPU_ADD(member, val)	__PCPU_ADD(pc_ ## member, val)
212 #define	PCPU_PTR(member)	__PCPU_PTR(pc_ ## member)
213 #define	PCPU_SET(member, val)	__PCPU_SET(pc_ ## member, val)
214 
215 #define	IS_BSP()	(PCPU_GET(cpuid) == 0)
216 
217 #define zpcpu_offset_cpu(cpu)	((uintptr_t)&__pcpu[0] + UMA_PCPU_ALLOC_SIZE * cpu)
218 #define zpcpu_base_to_offset(base) (void *)((uintptr_t)(base) - (uintptr_t)&__pcpu[0])
219 #define zpcpu_offset_to_base(base) (void *)((uintptr_t)(base) + (uintptr_t)&__pcpu[0])
220 
221 #define zpcpu_sub_protected(base, n) do {				\
222 	ZPCPU_ASSERT_PROTECTED();					\
223 	zpcpu_sub(base, n);						\
224 } while (0)
225 
226 #define zpcpu_set_protected(base, n) do {				\
227 	__typeof(*base) __n = (n);					\
228 	ZPCPU_ASSERT_PROTECTED();					\
229 	switch (sizeof(*base)) {					\
230 	case 4:								\
231 		__asm __volatile("movl\t%1,%%gs:(%0)"			\
232 		    : : "r" (base), "ri" (__n) : "memory", "cc");	\
233 		break;							\
234 	case 8:								\
235 		__asm __volatile("movq\t%1,%%gs:(%0)"			\
236 		    : : "r" (base), "ri" (__n) : "memory", "cc");	\
237 		break;							\
238 	default:							\
239 		*zpcpu_get(base) = __n;					\
240 	}								\
241 } while (0);
242 
243 #define zpcpu_add(base, n) do {						\
244 	__typeof(*base) __n = (n);					\
245 	CTASSERT(sizeof(*base) == 4 || sizeof(*base) == 8);		\
246 	switch (sizeof(*base)) {					\
247 	case 4:								\
248 		__asm __volatile("addl\t%1,%%gs:(%0)"			\
249 		    : : "r" (base), "ri" (__n) : "memory", "cc");	\
250 		break;							\
251 	case 8:								\
252 		__asm __volatile("addq\t%1,%%gs:(%0)"			\
253 		    : : "r" (base), "ri" (__n) : "memory", "cc");	\
254 		break;							\
255 	}								\
256 } while (0)
257 
258 #define zpcpu_add_protected(base, n) do {				\
259 	ZPCPU_ASSERT_PROTECTED();					\
260 	zpcpu_add(base, n);						\
261 } while (0)
262 
263 #define zpcpu_sub(base, n) do {						\
264 	__typeof(*base) __n = (n);					\
265 	CTASSERT(sizeof(*base) == 4 || sizeof(*base) == 8);		\
266 	switch (sizeof(*base)) {					\
267 	case 4:								\
268 		__asm __volatile("subl\t%1,%%gs:(%0)"			\
269 		    : : "r" (base), "ri" (__n) : "memory", "cc");	\
270 		break;							\
271 	case 8:								\
272 		__asm __volatile("subq\t%1,%%gs:(%0)"			\
273 		    : : "r" (base), "ri" (__n) : "memory", "cc");	\
274 		break;							\
275 	}								\
276 } while (0);
277 
278 #endif /* _KERNEL */
279 
280 #endif /* !_MACHINE_PCPU_H_ */
281 
282 #endif /* __i386__ */
283