1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) Peter Wemm <peter@netplex.com.au> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #ifndef _MACHINE_PCPU_H_ 32 #define _MACHINE_PCPU_H_ 33 34 #include <machine/segments.h> 35 #include <machine/tss.h> 36 37 #define PC_PTI_STACK_SZ 16 38 39 struct monitorbuf { 40 int idle_state; /* Used by cpu_idle_mwait. */ 41 int stop_state; /* Used by cpustop_handler. */ 42 char padding[128 - (2 * sizeof(int))]; 43 }; 44 _Static_assert(sizeof(struct monitorbuf) == 128, "2x cache line"); 45 46 /* 47 * The SMP parts are setup in pmap.c and locore.s for the BSP, and 48 * mp_machdep.c sets up the data for the AP's to "see" when they awake. 49 * The reason for doing it via a struct is so that an array of pointers 50 * to each CPU's data can be set up for things like "check curproc on all 51 * other processors" 52 */ 53 #define PCPU_MD_FIELDS \ 54 struct monitorbuf pc_monitorbuf __aligned(128); /* cache line */\ 55 struct pcpu *pc_prvspace; /* Self-reference */ \ 56 struct pmap *pc_curpmap; \ 57 struct amd64tss *pc_tssp; /* TSS segment active on CPU */ \ 58 void *pc_pad0; \ 59 uint64_t pc_kcr3; \ 60 uint64_t pc_ucr3; \ 61 uint64_t pc_saved_ucr3; \ 62 register_t pc_rsp0; \ 63 register_t pc_scratch_rsp; /* User %rsp in syscall */ \ 64 register_t pc_scratch_rax; \ 65 u_int pc_apic_id; \ 66 u_int pc_acpi_id; /* ACPI CPU id */ \ 67 /* Pointer to the CPU %fs descriptor */ \ 68 struct user_segment_descriptor *pc_fs32p; \ 69 /* Pointer to the CPU %gs descriptor */ \ 70 struct user_segment_descriptor *pc_gs32p; \ 71 /* Pointer to the CPU LDT descriptor */ \ 72 struct system_segment_descriptor *pc_ldt; \ 73 /* Pointer to the CPU TSS descriptor */ \ 74 struct system_segment_descriptor *pc_tss; \ 75 u_int pc_cmci_mask; /* MCx banks for CMCI */ \ 76 uint64_t pc_dbreg[16]; /* ddb debugging regs */ \ 77 uint64_t pc_pti_stack[PC_PTI_STACK_SZ]; \ 78 register_t pc_pti_rsp0; \ 79 int pc_dbreg_cmd; /* ddb debugging reg cmd */ \ 80 u_int pc_vcpu_id; /* Xen vCPU ID */ \ 81 uint32_t pc_pcid_next; \ 82 uint32_t pc_pcid_gen; \ 83 uint32_t pc_unused; \ 84 uint32_t pc_ibpb_set; \ 85 void *pc_mds_buf; \ 86 void *pc_mds_buf64; \ 87 uint32_t pc_pad[4]; \ 88 uint8_t pc_mds_tmp[64]; \ 89 u_int pc_ipi_bitmap; \ 90 struct amd64tss pc_common_tss; \ 91 struct user_segment_descriptor pc_gdt[NGDT]; \ 92 void *pc_smp_tlb_pmap; \ 93 uint64_t pc_smp_tlb_addr1; \ 94 uint64_t pc_smp_tlb_addr2; \ 95 uint32_t pc_smp_tlb_gen; \ 96 u_int pc_smp_tlb_op; \ 97 uint64_t pc_ucr3_load_mask; \ 98 char __pad[2916] /* pad to UMA_PCPU_ALLOC_SIZE */ 99 100 #define PC_DBREG_CMD_NONE 0 101 #define PC_DBREG_CMD_LOAD 1 102 103 #ifdef _KERNEL 104 105 #define MONITOR_STOPSTATE_RUNNING 0 106 #define MONITOR_STOPSTATE_STOPPED 1 107 108 /* 109 * Evaluates to the byte offset of the per-cpu variable name. 110 */ 111 #define __pcpu_offset(name) \ 112 __offsetof(struct pcpu, name) 113 114 /* 115 * Evaluates to the type of the per-cpu variable name. 116 */ 117 #define __pcpu_type(name) \ 118 __typeof(((struct pcpu *)0)->name) 119 120 /* 121 * Evaluates to the address of the per-cpu variable name. 122 */ 123 #define __PCPU_PTR(name) __extension__ ({ \ 124 __pcpu_type(name) *__p; \ 125 \ 126 __asm __volatile("movq %%gs:%1,%0; addq %2,%0" \ 127 : "=r" (__p) \ 128 : "m" (*(struct pcpu *)(__pcpu_offset(pc_prvspace))), \ 129 "i" (__pcpu_offset(name))); \ 130 \ 131 __p; \ 132 }) 133 134 /* 135 * Evaluates to the value of the per-cpu variable name. 136 */ 137 #define __PCPU_GET(name) __extension__ ({ \ 138 __pcpu_type(name) __res; \ 139 struct __s { \ 140 u_char __b[MIN(sizeof(__pcpu_type(name)), 8)]; \ 141 } __s; \ 142 \ 143 if (sizeof(__res) == 1 || sizeof(__res) == 2 || \ 144 sizeof(__res) == 4 || sizeof(__res) == 8) { \ 145 __asm __volatile("mov %%gs:%1,%0" \ 146 : "=r" (__s) \ 147 : "m" (*(struct __s *)(__pcpu_offset(name)))); \ 148 *(struct __s *)(void *)&__res = __s; \ 149 } else { \ 150 __res = *__PCPU_PTR(name); \ 151 } \ 152 __res; \ 153 }) 154 155 /* 156 * Adds the value to the per-cpu counter name. The implementation 157 * must be atomic with respect to interrupts. 158 */ 159 #define __PCPU_ADD(name, val) do { \ 160 __pcpu_type(name) __val; \ 161 struct __s { \ 162 u_char __b[MIN(sizeof(__pcpu_type(name)), 8)]; \ 163 } __s; \ 164 \ 165 __val = (val); \ 166 if (sizeof(__val) == 1 || sizeof(__val) == 2 || \ 167 sizeof(__val) == 4 || sizeof(__val) == 8) { \ 168 __s = *(struct __s *)(void *)&__val; \ 169 __asm __volatile("add %1,%%gs:%0" \ 170 : "=m" (*(struct __s *)(__pcpu_offset(name))) \ 171 : "r" (__s)); \ 172 } else \ 173 *__PCPU_PTR(name) += __val; \ 174 } while (0) 175 176 /* 177 * Sets the value of the per-cpu variable name to value val. 178 */ 179 #define __PCPU_SET(name, val) { \ 180 __pcpu_type(name) __val; \ 181 struct __s { \ 182 u_char __b[MIN(sizeof(__pcpu_type(name)), 8)]; \ 183 } __s; \ 184 \ 185 __val = (val); \ 186 if (sizeof(__val) == 1 || sizeof(__val) == 2 || \ 187 sizeof(__val) == 4 || sizeof(__val) == 8) { \ 188 __s = *(struct __s *)(void *)&__val; \ 189 __asm __volatile("mov %1,%%gs:%0" \ 190 : "=m" (*(struct __s *)(__pcpu_offset(name))) \ 191 : "r" (__s)); \ 192 } else { \ 193 *__PCPU_PTR(name) = __val; \ 194 } \ 195 } 196 197 #define get_pcpu() __extension__ ({ \ 198 struct pcpu *__pc; \ 199 \ 200 __asm __volatile("movq %%gs:%1,%0" \ 201 : "=r" (__pc) \ 202 : "m" (*(struct pcpu *)(__pcpu_offset(pc_prvspace)))); \ 203 __pc; \ 204 }) 205 206 #define PCPU_GET(member) __PCPU_GET(pc_ ## member) 207 #define PCPU_ADD(member, val) __PCPU_ADD(pc_ ## member, val) 208 #define PCPU_PTR(member) __PCPU_PTR(pc_ ## member) 209 #define PCPU_SET(member, val) __PCPU_SET(pc_ ## member, val) 210 211 #define IS_BSP() (PCPU_GET(cpuid) == 0) 212 213 #define zpcpu_offset_cpu(cpu) ((uintptr_t)&__pcpu[0] + UMA_PCPU_ALLOC_SIZE * cpu) 214 #define zpcpu_base_to_offset(base) (void *)((uintptr_t)(base) - (uintptr_t)&__pcpu[0]) 215 #define zpcpu_offset_to_base(base) (void *)((uintptr_t)(base) + (uintptr_t)&__pcpu[0]) 216 217 #define zpcpu_sub_protected(base, n) do { \ 218 ZPCPU_ASSERT_PROTECTED(); \ 219 zpcpu_sub(base, n); \ 220 } while (0) 221 222 #define zpcpu_set_protected(base, n) do { \ 223 __typeof(*base) __n = (n); \ 224 ZPCPU_ASSERT_PROTECTED(); \ 225 switch (sizeof(*base)) { \ 226 case 4: \ 227 __asm __volatile("movl\t%1,%%gs:(%0)" \ 228 : : "r" (base), "ri" (__n) : "memory", "cc"); \ 229 break; \ 230 case 8: \ 231 __asm __volatile("movq\t%1,%%gs:(%0)" \ 232 : : "r" (base), "ri" (__n) : "memory", "cc"); \ 233 break; \ 234 default: \ 235 *zpcpu_get(base) = __n; \ 236 } \ 237 } while (0); 238 239 #define zpcpu_add(base, n) do { \ 240 __typeof(*base) __n = (n); \ 241 CTASSERT(sizeof(*base) == 4 || sizeof(*base) == 8); \ 242 switch (sizeof(*base)) { \ 243 case 4: \ 244 __asm __volatile("addl\t%1,%%gs:(%0)" \ 245 : : "r" (base), "ri" (__n) : "memory", "cc"); \ 246 break; \ 247 case 8: \ 248 __asm __volatile("addq\t%1,%%gs:(%0)" \ 249 : : "r" (base), "ri" (__n) : "memory", "cc"); \ 250 break; \ 251 } \ 252 } while (0) 253 254 #define zpcpu_add_protected(base, n) do { \ 255 ZPCPU_ASSERT_PROTECTED(); \ 256 zpcpu_add(base, n); \ 257 } while (0) 258 259 #define zpcpu_sub(base, n) do { \ 260 __typeof(*base) __n = (n); \ 261 CTASSERT(sizeof(*base) == 4 || sizeof(*base) == 8); \ 262 switch (sizeof(*base)) { \ 263 case 4: \ 264 __asm __volatile("subl\t%1,%%gs:(%0)" \ 265 : : "r" (base), "ri" (__n) : "memory", "cc"); \ 266 break; \ 267 case 8: \ 268 __asm __volatile("subq\t%1,%%gs:(%0)" \ 269 : : "r" (base), "ri" (__n) : "memory", "cc"); \ 270 break; \ 271 } \ 272 } while (0); 273 274 #endif /* _KERNEL */ 275 276 #endif /* !_MACHINE_PCPU_H_ */ 277