1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #ifndef __MACHINE_INTR_MACHDEP_H__ 32 #define __MACHINE_INTR_MACHDEP_H__ 33 34 #ifdef _KERNEL 35 36 /* 37 * The maximum number of I/O interrupts we allow. This number is rather 38 * arbitrary as it is just the maximum IRQ resource value. The interrupt 39 * source for a given IRQ maps that I/O interrupt to device interrupt 40 * source whether it be a pin on an interrupt controller or an MSI interrupt. 41 * The 16 ISA IRQs are assigned fixed IDT vectors, but all other device 42 * interrupts allocate IDT vectors on demand. Currently we have 191 IDT 43 * vectors available for device interrupts. On many systems with I/O APICs, 44 * a lot of the IRQs are not used, so this number can be much larger than 45 * 191 and still be safe since only interrupt sources in actual use will 46 * allocate IDT vectors. 47 * 48 * The first 255 IRQs (0 - 254) are reserved for ISA IRQs and PCI intline IRQs. 49 * IRQ values from 256 to 767 are used by MSI. When running under the Xen 50 * Hypervisor, IRQ values from 768 to 4863 are available for binding to 51 * event channel events. We leave 255 unused to avoid confusion since 255 is 52 * used in PCI to indicate an invalid IRQ. 53 */ 54 #define NUM_MSI_INTS 512 55 #define FIRST_MSI_INT 256 56 #ifdef XENHVM 57 #include <xen/xen-os.h> 58 #include <xen/interface/event_channel.h> 59 #define NUM_EVTCHN_INTS NR_EVENT_CHANNELS 60 #define FIRST_EVTCHN_INT \ 61 (FIRST_MSI_INT + NUM_MSI_INTS) 62 #define LAST_EVTCHN_INT \ 63 (FIRST_EVTCHN_INT + NUM_EVTCHN_INTS - 1) 64 #else 65 #define NUM_EVTCHN_INTS 0 66 #endif 67 #define NUM_IO_INTS (FIRST_MSI_INT + NUM_MSI_INTS + NUM_EVTCHN_INTS) 68 69 /* 70 * Default base address for MSI messages on x86 platforms. 71 */ 72 #define MSI_INTEL_ADDR_BASE 0xfee00000 73 74 /* 75 * - 1 ??? dummy counter. 76 * - 2 counters for each I/O interrupt. 77 * - 1 counter for each CPU for lapic timer. 78 * - 8 counters for each CPU for IPI counters for SMP. 79 */ 80 #ifdef SMP 81 #define INTRCNT_COUNT (1 + NUM_IO_INTS * 2 + (1 + 8) * MAXCPU) 82 #else 83 #define INTRCNT_COUNT (1 + NUM_IO_INTS * 2 + 1) 84 #endif 85 86 #ifndef LOCORE 87 88 typedef void inthand_t(void); 89 90 #define IDTVEC(name) __CONCAT(X,name) 91 92 struct intsrc; 93 94 /* 95 * Methods that a PIC provides to mask/unmask a given interrupt source, 96 * "turn on" the interrupt on the CPU side by setting up an IDT entry, and 97 * return the vector associated with this source. 98 */ 99 struct pic { 100 void (*pic_enable_source)(struct intsrc *); 101 void (*pic_disable_source)(struct intsrc *, int); 102 void (*pic_eoi_source)(struct intsrc *); 103 void (*pic_enable_intr)(struct intsrc *); 104 void (*pic_disable_intr)(struct intsrc *); 105 int (*pic_vector)(struct intsrc *); 106 int (*pic_source_pending)(struct intsrc *); 107 void (*pic_suspend)(struct pic *); 108 void (*pic_resume)(struct pic *, bool suspend_cancelled); 109 int (*pic_config_intr)(struct intsrc *, enum intr_trigger, 110 enum intr_polarity); 111 int (*pic_assign_cpu)(struct intsrc *, u_int apic_id); 112 void (*pic_reprogram_pin)(struct intsrc *); 113 TAILQ_ENTRY(pic) pics; 114 }; 115 116 /* Flags for pic_disable_source() */ 117 enum { 118 PIC_EOI, 119 PIC_NO_EOI, 120 }; 121 122 /* 123 * An interrupt source. The upper-layer code uses the PIC methods to 124 * control a given source. The lower-layer PIC drivers can store additional 125 * private data in a given interrupt source such as an interrupt pin number 126 * or an I/O APIC pointer. 127 */ 128 struct intsrc { 129 struct pic *is_pic; 130 struct intr_event *is_event; 131 u_long *is_count; 132 u_long *is_straycount; 133 u_int is_index; 134 u_int is_handlers; 135 u_int is_domain; 136 u_int is_cpu; 137 }; 138 139 struct trapframe; 140 141 /* 142 * The following data structure holds per-cpu data, and is placed just 143 * above the top of the space used for the NMI and MC# stacks. 144 */ 145 struct nmi_pcpu { 146 register_t np_pcpu; 147 register_t __padding; /* pad to 16 bytes */ 148 }; 149 150 #ifdef SMP 151 extern cpuset_t intr_cpus; 152 #endif 153 extern struct mtx icu_lock; 154 extern int elcr_found; 155 #ifdef SMP 156 extern int msix_disable_migration; 157 #endif 158 159 #ifndef DEV_ATPIC 160 void atpic_reset(void); 161 #endif 162 /* XXX: The elcr_* prototypes probably belong somewhere else. */ 163 int elcr_probe(void); 164 enum intr_trigger elcr_read_trigger(u_int irq); 165 void elcr_resume(void); 166 void elcr_write_trigger(u_int irq, enum intr_trigger trigger); 167 #ifdef SMP 168 void intr_add_cpu(u_int cpu); 169 #endif 170 int intr_add_handler(const char *name, int vector, driver_filter_t filter, 171 driver_intr_t handler, void *arg, enum intr_type flags, 172 void **cookiep, int domain); 173 #ifdef SMP 174 int intr_bind(u_int vector, u_char cpu); 175 #endif 176 int intr_config_intr(int vector, enum intr_trigger trig, 177 enum intr_polarity pol); 178 int intr_describe(u_int vector, void *ih, const char *descr); 179 void intr_execute_handlers(struct intsrc *isrc, struct trapframe *frame); 180 u_int intr_next_cpu(int domain); 181 struct intsrc *intr_lookup_source(int vector); 182 int intr_register_pic(struct pic *pic); 183 int intr_register_source(struct intsrc *isrc); 184 int intr_remove_handler(void *cookie); 185 void intr_resume(bool suspend_cancelled); 186 void intr_suspend(void); 187 void intr_reprogram(void); 188 void intrcnt_add(const char *name, u_long **countp); 189 void nexus_add_irq(u_long irq); 190 int msi_alloc(device_t dev, int count, int maxcount, int *irqs); 191 void msi_init(void); 192 int msi_map(int irq, uint64_t *addr, uint32_t *data); 193 int msi_release(int *irqs, int count); 194 int msix_alloc(device_t dev, int *irq); 195 int msix_release(int irq); 196 197 #endif /* !LOCORE */ 198 #endif /* _KERNEL */ 199 #endif /* !__MACHINE_INTR_MACHDEP_H__ */ 200