1 /*- 2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef __MACHINE_INTR_MACHDEP_H__ 30 #define __MACHINE_INTR_MACHDEP_H__ 31 32 #ifdef _KERNEL 33 34 /* 35 * The maximum number of I/O interrupts we allow. This number is rather 36 * arbitrary as it is just the maximum IRQ resource value. The interrupt 37 * source for a given IRQ maps that I/O interrupt to device interrupt 38 * source whether it be a pin on an interrupt controller or an MSI interrupt. 39 * The 16 ISA IRQs are assigned fixed IDT vectors, but all other device 40 * interrupts allocate IDT vectors on demand. Currently we have 191 IDT 41 * vectors available for device interrupts. On many systems with I/O APICs, 42 * a lot of the IRQs are not used, so this number can be much larger than 43 * 191 and still be safe since only interrupt sources in actual use will 44 * allocate IDT vectors. 45 * 46 * The first 255 IRQs (0 - 254) are reserved for ISA IRQs and PCI intline IRQs. 47 * IRQ values from 256 to 767 are used by MSI. When running under the Xen 48 * Hypervisor, IRQ values from 768 to 4863 are available for binding to 49 * event channel events. We leave 255 unused to avoid confusion since 255 is 50 * used in PCI to indicate an invalid IRQ. 51 */ 52 #define NUM_MSI_INTS 512 53 #define FIRST_MSI_INT 256 54 #ifdef XENHVM 55 #include <xen/xen-os.h> 56 #include <xen/interface/event_channel.h> 57 #define NUM_EVTCHN_INTS NR_EVENT_CHANNELS 58 #define FIRST_EVTCHN_INT \ 59 (FIRST_MSI_INT + NUM_MSI_INTS) 60 #define LAST_EVTCHN_INT \ 61 (FIRST_EVTCHN_INT + NUM_EVTCHN_INTS - 1) 62 #else 63 #define NUM_EVTCHN_INTS 0 64 #endif 65 #define NUM_IO_INTS (FIRST_MSI_INT + NUM_MSI_INTS + NUM_EVTCHN_INTS) 66 67 /* 68 * Default base address for MSI messages on x86 platforms. 69 */ 70 #define MSI_INTEL_ADDR_BASE 0xfee00000 71 72 /* 73 * - 1 ??? dummy counter. 74 * - 2 counters for each I/O interrupt. 75 * - 1 counter for each CPU for lapic timer. 76 * - 8 counters for each CPU for IPI counters for SMP. 77 */ 78 #ifdef SMP 79 #define INTRCNT_COUNT (1 + NUM_IO_INTS * 2 + (1 + 8) * MAXCPU) 80 #else 81 #define INTRCNT_COUNT (1 + NUM_IO_INTS * 2 + 1) 82 #endif 83 84 #ifndef LOCORE 85 86 typedef void inthand_t(void); 87 88 #define IDTVEC(name) __CONCAT(X,name) 89 90 struct intsrc; 91 92 /* 93 * Methods that a PIC provides to mask/unmask a given interrupt source, 94 * "turn on" the interrupt on the CPU side by setting up an IDT entry, and 95 * return the vector associated with this source. 96 */ 97 struct pic { 98 void (*pic_enable_source)(struct intsrc *); 99 void (*pic_disable_source)(struct intsrc *, int); 100 void (*pic_eoi_source)(struct intsrc *); 101 void (*pic_enable_intr)(struct intsrc *); 102 void (*pic_disable_intr)(struct intsrc *); 103 int (*pic_vector)(struct intsrc *); 104 int (*pic_source_pending)(struct intsrc *); 105 void (*pic_suspend)(struct pic *); 106 void (*pic_resume)(struct pic *, bool suspend_cancelled); 107 int (*pic_config_intr)(struct intsrc *, enum intr_trigger, 108 enum intr_polarity); 109 int (*pic_assign_cpu)(struct intsrc *, u_int apic_id); 110 void (*pic_reprogram_pin)(struct intsrc *); 111 TAILQ_ENTRY(pic) pics; 112 }; 113 114 /* Flags for pic_disable_source() */ 115 enum { 116 PIC_EOI, 117 PIC_NO_EOI, 118 }; 119 120 /* 121 * An interrupt source. The upper-layer code uses the PIC methods to 122 * control a given source. The lower-layer PIC drivers can store additional 123 * private data in a given interrupt source such as an interrupt pin number 124 * or an I/O APIC pointer. 125 */ 126 struct intsrc { 127 struct pic *is_pic; 128 struct intr_event *is_event; 129 u_long *is_count; 130 u_long *is_straycount; 131 u_int is_index; 132 u_int is_handlers; 133 }; 134 135 struct trapframe; 136 137 /* 138 * The following data structure holds per-cpu data, and is placed just 139 * above the top of the space used for the NMI stack. 140 */ 141 struct nmi_pcpu { 142 register_t np_pcpu; 143 register_t __padding; /* pad to 16 bytes */ 144 }; 145 146 #ifdef SMP 147 extern cpuset_t intr_cpus; 148 #endif 149 extern struct mtx icu_lock; 150 extern int elcr_found; 151 152 #ifndef DEV_ATPIC 153 void atpic_reset(void); 154 #endif 155 /* XXX: The elcr_* prototypes probably belong somewhere else. */ 156 int elcr_probe(void); 157 enum intr_trigger elcr_read_trigger(u_int irq); 158 void elcr_resume(void); 159 void elcr_write_trigger(u_int irq, enum intr_trigger trigger); 160 #ifdef SMP 161 void intr_add_cpu(u_int cpu); 162 #endif 163 int intr_add_handler(const char *name, int vector, driver_filter_t filter, 164 driver_intr_t handler, void *arg, enum intr_type flags, 165 void **cookiep); 166 #ifdef SMP 167 int intr_bind(u_int vector, u_char cpu); 168 #endif 169 int intr_config_intr(int vector, enum intr_trigger trig, 170 enum intr_polarity pol); 171 int intr_describe(u_int vector, void *ih, const char *descr); 172 void intr_execute_handlers(struct intsrc *isrc, struct trapframe *frame); 173 u_int intr_next_cpu(void); 174 struct intsrc *intr_lookup_source(int vector); 175 int intr_register_pic(struct pic *pic); 176 int intr_register_source(struct intsrc *isrc); 177 int intr_remove_handler(void *cookie); 178 void intr_resume(bool suspend_cancelled); 179 void intr_suspend(void); 180 void intr_reprogram(void); 181 void intrcnt_add(const char *name, u_long **countp); 182 void nexus_add_irq(u_long irq); 183 int msi_alloc(device_t dev, int count, int maxcount, int *irqs); 184 void msi_init(void); 185 int msi_map(int irq, uint64_t *addr, uint32_t *data); 186 int msi_release(int *irqs, int count); 187 int msix_alloc(device_t dev, int *irq); 188 int msix_release(int irq); 189 190 #endif /* !LOCORE */ 191 #endif /* _KERNEL */ 192 #endif /* !__MACHINE_INTR_MACHDEP_H__ */ 193