1 /*- 2 * Copyright (c) 2003 Peter Wemm. 3 * Copyright (c) 1993 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 4. Neither the name of the University nor the names of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD$ 31 */ 32 33 /* 34 * Functions to provide access to special i386 instructions. 35 * This in included in sys/systm.h, and that file should be 36 * used in preference to this. 37 */ 38 39 #ifndef _MACHINE_CPUFUNC_H_ 40 #define _MACHINE_CPUFUNC_H_ 41 42 #ifndef _SYS_CDEFS_H_ 43 #error this file needs sys/cdefs.h as a prerequisite 44 #endif 45 46 struct region_descriptor; 47 48 #define readb(va) (*(volatile uint8_t *) (va)) 49 #define readw(va) (*(volatile uint16_t *) (va)) 50 #define readl(va) (*(volatile uint32_t *) (va)) 51 #define readq(va) (*(volatile uint64_t *) (va)) 52 53 #define writeb(va, d) (*(volatile uint8_t *) (va) = (d)) 54 #define writew(va, d) (*(volatile uint16_t *) (va) = (d)) 55 #define writel(va, d) (*(volatile uint32_t *) (va) = (d)) 56 #define writeq(va, d) (*(volatile uint64_t *) (va) = (d)) 57 58 #if defined(__GNUCLIKE_ASM) && defined(__CC_SUPPORTS___INLINE) 59 60 static __inline void 61 breakpoint(void) 62 { 63 __asm __volatile("int $3"); 64 } 65 66 static __inline u_int 67 bsfl(u_int mask) 68 { 69 u_int result; 70 71 __asm __volatile("bsfl %1,%0" : "=r" (result) : "rm" (mask)); 72 return (result); 73 } 74 75 static __inline u_long 76 bsfq(u_long mask) 77 { 78 u_long result; 79 80 __asm __volatile("bsfq %1,%0" : "=r" (result) : "rm" (mask)); 81 return (result); 82 } 83 84 static __inline u_int 85 bsrl(u_int mask) 86 { 87 u_int result; 88 89 __asm __volatile("bsrl %1,%0" : "=r" (result) : "rm" (mask)); 90 return (result); 91 } 92 93 static __inline u_long 94 bsrq(u_long mask) 95 { 96 u_long result; 97 98 __asm __volatile("bsrq %1,%0" : "=r" (result) : "rm" (mask)); 99 return (result); 100 } 101 102 static __inline void 103 clflush(u_long addr) 104 { 105 106 __asm __volatile("clflush %0" : : "m" (*(char *)addr)); 107 } 108 109 static __inline void 110 clflushopt(u_long addr) 111 { 112 113 __asm __volatile(".byte 0x66;clflush %0" : : "m" (*(char *)addr)); 114 } 115 116 static __inline void 117 clts(void) 118 { 119 120 __asm __volatile("clts"); 121 } 122 123 static __inline void 124 disable_intr(void) 125 { 126 __asm __volatile("cli" : : : "memory"); 127 } 128 129 static __inline void 130 do_cpuid(u_int ax, u_int *p) 131 { 132 __asm __volatile("cpuid" 133 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3]) 134 : "0" (ax)); 135 } 136 137 static __inline void 138 cpuid_count(u_int ax, u_int cx, u_int *p) 139 { 140 __asm __volatile("cpuid" 141 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3]) 142 : "0" (ax), "c" (cx)); 143 } 144 145 static __inline void 146 enable_intr(void) 147 { 148 __asm __volatile("sti"); 149 } 150 151 #ifdef _KERNEL 152 153 #define HAVE_INLINE_FFS 154 #define ffs(x) __builtin_ffs(x) 155 156 #define HAVE_INLINE_FFSL 157 158 static __inline int 159 ffsl(long mask) 160 { 161 return (mask == 0 ? mask : (int)bsfq((u_long)mask) + 1); 162 } 163 164 #define HAVE_INLINE_FFSLL 165 166 static __inline int 167 ffsll(long long mask) 168 { 169 return (ffsl((long)mask)); 170 } 171 172 #define HAVE_INLINE_FLS 173 174 static __inline int 175 fls(int mask) 176 { 177 return (mask == 0 ? mask : (int)bsrl((u_int)mask) + 1); 178 } 179 180 #define HAVE_INLINE_FLSL 181 182 static __inline int 183 flsl(long mask) 184 { 185 return (mask == 0 ? mask : (int)bsrq((u_long)mask) + 1); 186 } 187 188 #define HAVE_INLINE_FLSLL 189 190 static __inline int 191 flsll(long long mask) 192 { 193 return (flsl((long)mask)); 194 } 195 196 #endif /* _KERNEL */ 197 198 static __inline void 199 halt(void) 200 { 201 __asm __volatile("hlt"); 202 } 203 204 static __inline u_char 205 inb(u_int port) 206 { 207 u_char data; 208 209 __asm __volatile("inb %w1, %0" : "=a" (data) : "Nd" (port)); 210 return (data); 211 } 212 213 static __inline u_int 214 inl(u_int port) 215 { 216 u_int data; 217 218 __asm __volatile("inl %w1, %0" : "=a" (data) : "Nd" (port)); 219 return (data); 220 } 221 222 static __inline void 223 insb(u_int port, void *addr, size_t count) 224 { 225 __asm __volatile("cld; rep; insb" 226 : "+D" (addr), "+c" (count) 227 : "d" (port) 228 : "memory"); 229 } 230 231 static __inline void 232 insw(u_int port, void *addr, size_t count) 233 { 234 __asm __volatile("cld; rep; insw" 235 : "+D" (addr), "+c" (count) 236 : "d" (port) 237 : "memory"); 238 } 239 240 static __inline void 241 insl(u_int port, void *addr, size_t count) 242 { 243 __asm __volatile("cld; rep; insl" 244 : "+D" (addr), "+c" (count) 245 : "d" (port) 246 : "memory"); 247 } 248 249 static __inline void 250 invd(void) 251 { 252 __asm __volatile("invd"); 253 } 254 255 static __inline u_short 256 inw(u_int port) 257 { 258 u_short data; 259 260 __asm __volatile("inw %w1, %0" : "=a" (data) : "Nd" (port)); 261 return (data); 262 } 263 264 static __inline void 265 outb(u_int port, u_char data) 266 { 267 __asm __volatile("outb %0, %w1" : : "a" (data), "Nd" (port)); 268 } 269 270 static __inline void 271 outl(u_int port, u_int data) 272 { 273 __asm __volatile("outl %0, %w1" : : "a" (data), "Nd" (port)); 274 } 275 276 static __inline void 277 outsb(u_int port, const void *addr, size_t count) 278 { 279 __asm __volatile("cld; rep; outsb" 280 : "+S" (addr), "+c" (count) 281 : "d" (port)); 282 } 283 284 static __inline void 285 outsw(u_int port, const void *addr, size_t count) 286 { 287 __asm __volatile("cld; rep; outsw" 288 : "+S" (addr), "+c" (count) 289 : "d" (port)); 290 } 291 292 static __inline void 293 outsl(u_int port, const void *addr, size_t count) 294 { 295 __asm __volatile("cld; rep; outsl" 296 : "+S" (addr), "+c" (count) 297 : "d" (port)); 298 } 299 300 static __inline void 301 outw(u_int port, u_short data) 302 { 303 __asm __volatile("outw %0, %w1" : : "a" (data), "Nd" (port)); 304 } 305 306 static __inline u_long 307 popcntq(u_long mask) 308 { 309 u_long result; 310 311 __asm __volatile("popcntq %1,%0" : "=r" (result) : "rm" (mask)); 312 return (result); 313 } 314 315 static __inline void 316 lfence(void) 317 { 318 319 __asm __volatile("lfence" : : : "memory"); 320 } 321 322 static __inline void 323 mfence(void) 324 { 325 326 __asm __volatile("mfence" : : : "memory"); 327 } 328 329 static __inline void 330 ia32_pause(void) 331 { 332 __asm __volatile("pause"); 333 } 334 335 static __inline u_long 336 read_rflags(void) 337 { 338 u_long rf; 339 340 __asm __volatile("pushfq; popq %0" : "=r" (rf)); 341 return (rf); 342 } 343 344 static __inline uint64_t 345 rdmsr(u_int msr) 346 { 347 uint32_t low, high; 348 349 __asm __volatile("rdmsr" : "=a" (low), "=d" (high) : "c" (msr)); 350 return (low | ((uint64_t)high << 32)); 351 } 352 353 static __inline uint32_t 354 rdmsr32(u_int msr) 355 { 356 uint32_t low; 357 358 __asm __volatile("rdmsr" : "=a" (low) : "c" (msr) : "rdx"); 359 return (low); 360 } 361 362 static __inline uint64_t 363 rdpmc(u_int pmc) 364 { 365 uint32_t low, high; 366 367 __asm __volatile("rdpmc" : "=a" (low), "=d" (high) : "c" (pmc)); 368 return (low | ((uint64_t)high << 32)); 369 } 370 371 static __inline uint64_t 372 rdtsc(void) 373 { 374 uint32_t low, high; 375 376 __asm __volatile("rdtsc" : "=a" (low), "=d" (high)); 377 return (low | ((uint64_t)high << 32)); 378 } 379 380 static __inline uint32_t 381 rdtsc32(void) 382 { 383 uint32_t rv; 384 385 __asm __volatile("rdtsc" : "=a" (rv) : : "edx"); 386 return (rv); 387 } 388 389 static __inline void 390 wbinvd(void) 391 { 392 __asm __volatile("wbinvd"); 393 } 394 395 static __inline void 396 write_rflags(u_long rf) 397 { 398 __asm __volatile("pushq %0; popfq" : : "r" (rf)); 399 } 400 401 static __inline void 402 wrmsr(u_int msr, uint64_t newval) 403 { 404 uint32_t low, high; 405 406 low = newval; 407 high = newval >> 32; 408 __asm __volatile("wrmsr" : : "a" (low), "d" (high), "c" (msr)); 409 } 410 411 static __inline void 412 load_cr0(u_long data) 413 { 414 415 __asm __volatile("movq %0,%%cr0" : : "r" (data)); 416 } 417 418 static __inline u_long 419 rcr0(void) 420 { 421 u_long data; 422 423 __asm __volatile("movq %%cr0,%0" : "=r" (data)); 424 return (data); 425 } 426 427 static __inline u_long 428 rcr2(void) 429 { 430 u_long data; 431 432 __asm __volatile("movq %%cr2,%0" : "=r" (data)); 433 return (data); 434 } 435 436 static __inline void 437 load_cr3(u_long data) 438 { 439 440 __asm __volatile("movq %0,%%cr3" : : "r" (data) : "memory"); 441 } 442 443 static __inline u_long 444 rcr3(void) 445 { 446 u_long data; 447 448 __asm __volatile("movq %%cr3,%0" : "=r" (data)); 449 return (data); 450 } 451 452 static __inline void 453 load_cr4(u_long data) 454 { 455 __asm __volatile("movq %0,%%cr4" : : "r" (data)); 456 } 457 458 static __inline u_long 459 rcr4(void) 460 { 461 u_long data; 462 463 __asm __volatile("movq %%cr4,%0" : "=r" (data)); 464 return (data); 465 } 466 467 static __inline u_long 468 rxcr(u_int reg) 469 { 470 u_int low, high; 471 472 __asm __volatile("xgetbv" : "=a" (low), "=d" (high) : "c" (reg)); 473 return (low | ((uint64_t)high << 32)); 474 } 475 476 static __inline void 477 load_xcr(u_int reg, u_long val) 478 { 479 u_int low, high; 480 481 low = val; 482 high = val >> 32; 483 __asm __volatile("xsetbv" : : "c" (reg), "a" (low), "d" (high)); 484 } 485 486 /* 487 * Global TLB flush (except for thise for pages marked PG_G) 488 */ 489 static __inline void 490 invltlb(void) 491 { 492 493 load_cr3(rcr3()); 494 } 495 496 #ifndef CR4_PGE 497 #define CR4_PGE 0x00000080 /* Page global enable */ 498 #endif 499 500 /* 501 * Perform the guaranteed invalidation of all TLB entries. This 502 * includes the global entries, and entries in all PCIDs, not only the 503 * current context. The function works both on non-PCID CPUs and CPUs 504 * with the PCID turned off or on. See IA-32 SDM Vol. 3a 4.10.4.1 505 * Operations that Invalidate TLBs and Paging-Structure Caches. 506 */ 507 static __inline void 508 invltlb_glob(void) 509 { 510 uint64_t cr4; 511 512 cr4 = rcr4(); 513 load_cr4(cr4 & ~CR4_PGE); 514 /* 515 * Although preemption at this point could be detrimental to 516 * performance, it would not lead to an error. PG_G is simply 517 * ignored if CR4.PGE is clear. Moreover, in case this block 518 * is re-entered, the load_cr4() either above or below will 519 * modify CR4.PGE flushing the TLB. 520 */ 521 load_cr4(cr4 | CR4_PGE); 522 } 523 524 /* 525 * TLB flush for an individual page (even if it has PG_G). 526 * Only works on 486+ CPUs (i386 does not have PG_G). 527 */ 528 static __inline void 529 invlpg(u_long addr) 530 { 531 532 __asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory"); 533 } 534 535 #define INVPCID_ADDR 0 536 #define INVPCID_CTX 1 537 #define INVPCID_CTXGLOB 2 538 #define INVPCID_ALLCTX 3 539 540 struct invpcid_descr { 541 uint64_t pcid:12 __packed; 542 uint64_t pad:52 __packed; 543 uint64_t addr; 544 } __packed; 545 546 static __inline void 547 invpcid(struct invpcid_descr *d, int type) 548 { 549 550 __asm __volatile("invpcid (%0),%1" 551 : : "r" (d), "r" ((u_long)type) : "memory"); 552 } 553 554 static __inline u_short 555 rfs(void) 556 { 557 u_short sel; 558 __asm __volatile("movw %%fs,%0" : "=rm" (sel)); 559 return (sel); 560 } 561 562 static __inline u_short 563 rgs(void) 564 { 565 u_short sel; 566 __asm __volatile("movw %%gs,%0" : "=rm" (sel)); 567 return (sel); 568 } 569 570 static __inline u_short 571 rss(void) 572 { 573 u_short sel; 574 __asm __volatile("movw %%ss,%0" : "=rm" (sel)); 575 return (sel); 576 } 577 578 static __inline void 579 load_ds(u_short sel) 580 { 581 __asm __volatile("movw %0,%%ds" : : "rm" (sel)); 582 } 583 584 static __inline void 585 load_es(u_short sel) 586 { 587 __asm __volatile("movw %0,%%es" : : "rm" (sel)); 588 } 589 590 static __inline void 591 cpu_monitor(const void *addr, u_long extensions, u_int hints) 592 { 593 594 __asm __volatile("monitor" 595 : : "a" (addr), "c" (extensions), "d" (hints)); 596 } 597 598 static __inline void 599 cpu_mwait(u_long extensions, u_int hints) 600 { 601 602 __asm __volatile("mwait" : : "a" (hints), "c" (extensions)); 603 } 604 605 #ifdef _KERNEL 606 /* This is defined in <machine/specialreg.h> but is too painful to get to */ 607 #ifndef MSR_FSBASE 608 #define MSR_FSBASE 0xc0000100 609 #endif 610 static __inline void 611 load_fs(u_short sel) 612 { 613 /* Preserve the fsbase value across the selector load */ 614 __asm __volatile("rdmsr; movw %0,%%fs; wrmsr" 615 : : "rm" (sel), "c" (MSR_FSBASE) : "eax", "edx"); 616 } 617 618 #ifndef MSR_GSBASE 619 #define MSR_GSBASE 0xc0000101 620 #endif 621 static __inline void 622 load_gs(u_short sel) 623 { 624 /* 625 * Preserve the gsbase value across the selector load. 626 * Note that we have to disable interrupts because the gsbase 627 * being trashed happens to be the kernel gsbase at the time. 628 */ 629 __asm __volatile("pushfq; cli; rdmsr; movw %0,%%gs; wrmsr; popfq" 630 : : "rm" (sel), "c" (MSR_GSBASE) : "eax", "edx"); 631 } 632 #else 633 /* Usable by userland */ 634 static __inline void 635 load_fs(u_short sel) 636 { 637 __asm __volatile("movw %0,%%fs" : : "rm" (sel)); 638 } 639 640 static __inline void 641 load_gs(u_short sel) 642 { 643 __asm __volatile("movw %0,%%gs" : : "rm" (sel)); 644 } 645 #endif 646 647 static __inline void 648 bare_lgdt(struct region_descriptor *addr) 649 { 650 __asm __volatile("lgdt (%0)" : : "r" (addr)); 651 } 652 653 static __inline void 654 sgdt(struct region_descriptor *addr) 655 { 656 char *loc; 657 658 loc = (char *)addr; 659 __asm __volatile("sgdt %0" : "=m" (*loc) : : "memory"); 660 } 661 662 static __inline void 663 lidt(struct region_descriptor *addr) 664 { 665 __asm __volatile("lidt (%0)" : : "r" (addr)); 666 } 667 668 static __inline void 669 sidt(struct region_descriptor *addr) 670 { 671 char *loc; 672 673 loc = (char *)addr; 674 __asm __volatile("sidt %0" : "=m" (*loc) : : "memory"); 675 } 676 677 static __inline void 678 lldt(u_short sel) 679 { 680 __asm __volatile("lldt %0" : : "r" (sel)); 681 } 682 683 static __inline void 684 ltr(u_short sel) 685 { 686 __asm __volatile("ltr %0" : : "r" (sel)); 687 } 688 689 static __inline uint32_t 690 read_tr(void) 691 { 692 u_short sel; 693 694 __asm __volatile("str %0" : "=r" (sel)); 695 return (sel); 696 } 697 698 static __inline uint64_t 699 rdr0(void) 700 { 701 uint64_t data; 702 __asm __volatile("movq %%dr0,%0" : "=r" (data)); 703 return (data); 704 } 705 706 static __inline void 707 load_dr0(uint64_t dr0) 708 { 709 __asm __volatile("movq %0,%%dr0" : : "r" (dr0)); 710 } 711 712 static __inline uint64_t 713 rdr1(void) 714 { 715 uint64_t data; 716 __asm __volatile("movq %%dr1,%0" : "=r" (data)); 717 return (data); 718 } 719 720 static __inline void 721 load_dr1(uint64_t dr1) 722 { 723 __asm __volatile("movq %0,%%dr1" : : "r" (dr1)); 724 } 725 726 static __inline uint64_t 727 rdr2(void) 728 { 729 uint64_t data; 730 __asm __volatile("movq %%dr2,%0" : "=r" (data)); 731 return (data); 732 } 733 734 static __inline void 735 load_dr2(uint64_t dr2) 736 { 737 __asm __volatile("movq %0,%%dr2" : : "r" (dr2)); 738 } 739 740 static __inline uint64_t 741 rdr3(void) 742 { 743 uint64_t data; 744 __asm __volatile("movq %%dr3,%0" : "=r" (data)); 745 return (data); 746 } 747 748 static __inline void 749 load_dr3(uint64_t dr3) 750 { 751 __asm __volatile("movq %0,%%dr3" : : "r" (dr3)); 752 } 753 754 static __inline uint64_t 755 rdr4(void) 756 { 757 uint64_t data; 758 __asm __volatile("movq %%dr4,%0" : "=r" (data)); 759 return (data); 760 } 761 762 static __inline void 763 load_dr4(uint64_t dr4) 764 { 765 __asm __volatile("movq %0,%%dr4" : : "r" (dr4)); 766 } 767 768 static __inline uint64_t 769 rdr5(void) 770 { 771 uint64_t data; 772 __asm __volatile("movq %%dr5,%0" : "=r" (data)); 773 return (data); 774 } 775 776 static __inline void 777 load_dr5(uint64_t dr5) 778 { 779 __asm __volatile("movq %0,%%dr5" : : "r" (dr5)); 780 } 781 782 static __inline uint64_t 783 rdr6(void) 784 { 785 uint64_t data; 786 __asm __volatile("movq %%dr6,%0" : "=r" (data)); 787 return (data); 788 } 789 790 static __inline void 791 load_dr6(uint64_t dr6) 792 { 793 __asm __volatile("movq %0,%%dr6" : : "r" (dr6)); 794 } 795 796 static __inline uint64_t 797 rdr7(void) 798 { 799 uint64_t data; 800 __asm __volatile("movq %%dr7,%0" : "=r" (data)); 801 return (data); 802 } 803 804 static __inline void 805 load_dr7(uint64_t dr7) 806 { 807 __asm __volatile("movq %0,%%dr7" : : "r" (dr7)); 808 } 809 810 static __inline register_t 811 intr_disable(void) 812 { 813 register_t rflags; 814 815 rflags = read_rflags(); 816 disable_intr(); 817 return (rflags); 818 } 819 820 static __inline void 821 intr_restore(register_t rflags) 822 { 823 write_rflags(rflags); 824 } 825 826 #else /* !(__GNUCLIKE_ASM && __CC_SUPPORTS___INLINE) */ 827 828 int breakpoint(void); 829 u_int bsfl(u_int mask); 830 u_int bsrl(u_int mask); 831 void clflush(u_long addr); 832 void clts(void); 833 void cpuid_count(u_int ax, u_int cx, u_int *p); 834 void disable_intr(void); 835 void do_cpuid(u_int ax, u_int *p); 836 void enable_intr(void); 837 void halt(void); 838 void ia32_pause(void); 839 u_char inb(u_int port); 840 u_int inl(u_int port); 841 void insb(u_int port, void *addr, size_t count); 842 void insl(u_int port, void *addr, size_t count); 843 void insw(u_int port, void *addr, size_t count); 844 register_t intr_disable(void); 845 void intr_restore(register_t rf); 846 void invd(void); 847 void invlpg(u_int addr); 848 void invltlb(void); 849 u_short inw(u_int port); 850 void lidt(struct region_descriptor *addr); 851 void lldt(u_short sel); 852 void load_cr0(u_long cr0); 853 void load_cr3(u_long cr3); 854 void load_cr4(u_long cr4); 855 void load_dr0(uint64_t dr0); 856 void load_dr1(uint64_t dr1); 857 void load_dr2(uint64_t dr2); 858 void load_dr3(uint64_t dr3); 859 void load_dr4(uint64_t dr4); 860 void load_dr5(uint64_t dr5); 861 void load_dr6(uint64_t dr6); 862 void load_dr7(uint64_t dr7); 863 void load_fs(u_short sel); 864 void load_gs(u_short sel); 865 void ltr(u_short sel); 866 void outb(u_int port, u_char data); 867 void outl(u_int port, u_int data); 868 void outsb(u_int port, const void *addr, size_t count); 869 void outsl(u_int port, const void *addr, size_t count); 870 void outsw(u_int port, const void *addr, size_t count); 871 void outw(u_int port, u_short data); 872 u_long rcr0(void); 873 u_long rcr2(void); 874 u_long rcr3(void); 875 u_long rcr4(void); 876 uint64_t rdmsr(u_int msr); 877 uint32_t rdmsr32(u_int msr); 878 uint64_t rdpmc(u_int pmc); 879 uint64_t rdr0(void); 880 uint64_t rdr1(void); 881 uint64_t rdr2(void); 882 uint64_t rdr3(void); 883 uint64_t rdr4(void); 884 uint64_t rdr5(void); 885 uint64_t rdr6(void); 886 uint64_t rdr7(void); 887 uint64_t rdtsc(void); 888 u_long read_rflags(void); 889 u_int rfs(void); 890 u_int rgs(void); 891 void wbinvd(void); 892 void write_rflags(u_int rf); 893 void wrmsr(u_int msr, uint64_t newval); 894 895 #endif /* __GNUCLIKE_ASM && __CC_SUPPORTS___INLINE */ 896 897 void reset_dbregs(void); 898 899 #ifdef _KERNEL 900 int rdmsr_safe(u_int msr, uint64_t *val); 901 int wrmsr_safe(u_int msr, uint64_t newval); 902 #endif 903 904 #endif /* !_MACHINE_CPUFUNC_H_ */ 905