1 /*- 2 * Copyright (c) 2003 Peter Wemm. 3 * Copyright (c) 1993 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 4. Neither the name of the University nor the names of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD$ 31 */ 32 33 /* 34 * Functions to provide access to special i386 instructions. 35 * This in included in sys/systm.h, and that file should be 36 * used in preference to this. 37 */ 38 39 #ifndef _MACHINE_CPUFUNC_H_ 40 #define _MACHINE_CPUFUNC_H_ 41 42 #ifndef _SYS_CDEFS_H_ 43 #error this file needs sys/cdefs.h as a prerequisite 44 #endif 45 46 struct region_descriptor; 47 48 #define readb(va) (*(volatile uint8_t *) (va)) 49 #define readw(va) (*(volatile uint16_t *) (va)) 50 #define readl(va) (*(volatile uint32_t *) (va)) 51 #define readq(va) (*(volatile uint64_t *) (va)) 52 53 #define writeb(va, d) (*(volatile uint8_t *) (va) = (d)) 54 #define writew(va, d) (*(volatile uint16_t *) (va) = (d)) 55 #define writel(va, d) (*(volatile uint32_t *) (va) = (d)) 56 #define writeq(va, d) (*(volatile uint64_t *) (va) = (d)) 57 58 #if defined(__GNUCLIKE_ASM) && defined(__CC_SUPPORTS___INLINE) 59 60 static __inline void 61 breakpoint(void) 62 { 63 __asm __volatile("int $3"); 64 } 65 66 static __inline u_int 67 bsfl(u_int mask) 68 { 69 u_int result; 70 71 __asm __volatile("bsfl %1,%0" : "=r" (result) : "rm" (mask)); 72 return (result); 73 } 74 75 static __inline u_long 76 bsfq(u_long mask) 77 { 78 u_long result; 79 80 __asm __volatile("bsfq %1,%0" : "=r" (result) : "rm" (mask)); 81 return (result); 82 } 83 84 static __inline u_int 85 bsrl(u_int mask) 86 { 87 u_int result; 88 89 __asm __volatile("bsrl %1,%0" : "=r" (result) : "rm" (mask)); 90 return (result); 91 } 92 93 static __inline u_long 94 bsrq(u_long mask) 95 { 96 u_long result; 97 98 __asm __volatile("bsrq %1,%0" : "=r" (result) : "rm" (mask)); 99 return (result); 100 } 101 102 static __inline void 103 clflush(u_long addr) 104 { 105 106 __asm __volatile("clflush %0" : : "m" (*(char *)addr)); 107 } 108 109 static __inline void 110 clts(void) 111 { 112 113 __asm __volatile("clts"); 114 } 115 116 static __inline void 117 disable_intr(void) 118 { 119 __asm __volatile("cli" : : : "memory"); 120 } 121 122 static __inline void 123 do_cpuid(u_int ax, u_int *p) 124 { 125 __asm __volatile("cpuid" 126 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3]) 127 : "0" (ax)); 128 } 129 130 static __inline void 131 cpuid_count(u_int ax, u_int cx, u_int *p) 132 { 133 __asm __volatile("cpuid" 134 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3]) 135 : "0" (ax), "c" (cx)); 136 } 137 138 static __inline void 139 enable_intr(void) 140 { 141 __asm __volatile("sti"); 142 } 143 144 #ifdef _KERNEL 145 146 #define HAVE_INLINE_FFS 147 #define ffs(x) __builtin_ffs(x) 148 149 #define HAVE_INLINE_FFSL 150 151 static __inline int 152 ffsl(long mask) 153 { 154 return (mask == 0 ? mask : (int)bsfq((u_long)mask) + 1); 155 } 156 157 #define HAVE_INLINE_FFSLL 158 159 static __inline int 160 ffsll(long long mask) 161 { 162 return (ffsl((long)mask)); 163 } 164 165 #define HAVE_INLINE_FLS 166 167 static __inline int 168 fls(int mask) 169 { 170 return (mask == 0 ? mask : (int)bsrl((u_int)mask) + 1); 171 } 172 173 #define HAVE_INLINE_FLSL 174 175 static __inline int 176 flsl(long mask) 177 { 178 return (mask == 0 ? mask : (int)bsrq((u_long)mask) + 1); 179 } 180 181 #define HAVE_INLINE_FLSLL 182 183 static __inline int 184 flsll(long long mask) 185 { 186 return (flsl((long)mask)); 187 } 188 189 #endif /* _KERNEL */ 190 191 static __inline void 192 halt(void) 193 { 194 __asm __volatile("hlt"); 195 } 196 197 static __inline u_char 198 inb(u_int port) 199 { 200 u_char data; 201 202 __asm __volatile("inb %w1, %0" : "=a" (data) : "Nd" (port)); 203 return (data); 204 } 205 206 static __inline u_int 207 inl(u_int port) 208 { 209 u_int data; 210 211 __asm __volatile("inl %w1, %0" : "=a" (data) : "Nd" (port)); 212 return (data); 213 } 214 215 static __inline void 216 insb(u_int port, void *addr, size_t count) 217 { 218 __asm __volatile("cld; rep; insb" 219 : "+D" (addr), "+c" (count) 220 : "d" (port) 221 : "memory"); 222 } 223 224 static __inline void 225 insw(u_int port, void *addr, size_t count) 226 { 227 __asm __volatile("cld; rep; insw" 228 : "+D" (addr), "+c" (count) 229 : "d" (port) 230 : "memory"); 231 } 232 233 static __inline void 234 insl(u_int port, void *addr, size_t count) 235 { 236 __asm __volatile("cld; rep; insl" 237 : "+D" (addr), "+c" (count) 238 : "d" (port) 239 : "memory"); 240 } 241 242 static __inline void 243 invd(void) 244 { 245 __asm __volatile("invd"); 246 } 247 248 static __inline u_short 249 inw(u_int port) 250 { 251 u_short data; 252 253 __asm __volatile("inw %w1, %0" : "=a" (data) : "Nd" (port)); 254 return (data); 255 } 256 257 static __inline void 258 outb(u_int port, u_char data) 259 { 260 __asm __volatile("outb %0, %w1" : : "a" (data), "Nd" (port)); 261 } 262 263 static __inline void 264 outl(u_int port, u_int data) 265 { 266 __asm __volatile("outl %0, %w1" : : "a" (data), "Nd" (port)); 267 } 268 269 static __inline void 270 outsb(u_int port, const void *addr, size_t count) 271 { 272 __asm __volatile("cld; rep; outsb" 273 : "+S" (addr), "+c" (count) 274 : "d" (port)); 275 } 276 277 static __inline void 278 outsw(u_int port, const void *addr, size_t count) 279 { 280 __asm __volatile("cld; rep; outsw" 281 : "+S" (addr), "+c" (count) 282 : "d" (port)); 283 } 284 285 static __inline void 286 outsl(u_int port, const void *addr, size_t count) 287 { 288 __asm __volatile("cld; rep; outsl" 289 : "+S" (addr), "+c" (count) 290 : "d" (port)); 291 } 292 293 static __inline void 294 outw(u_int port, u_short data) 295 { 296 __asm __volatile("outw %0, %w1" : : "a" (data), "Nd" (port)); 297 } 298 299 static __inline u_long 300 popcntq(u_long mask) 301 { 302 u_long result; 303 304 __asm __volatile("popcntq %1,%0" : "=r" (result) : "rm" (mask)); 305 return (result); 306 } 307 308 static __inline void 309 lfence(void) 310 { 311 312 __asm __volatile("lfence" : : : "memory"); 313 } 314 315 static __inline void 316 mfence(void) 317 { 318 319 __asm __volatile("mfence" : : : "memory"); 320 } 321 322 static __inline void 323 ia32_pause(void) 324 { 325 __asm __volatile("pause"); 326 } 327 328 static __inline u_long 329 read_rflags(void) 330 { 331 u_long rf; 332 333 __asm __volatile("pushfq; popq %0" : "=r" (rf)); 334 return (rf); 335 } 336 337 static __inline uint64_t 338 rdmsr(u_int msr) 339 { 340 uint32_t low, high; 341 342 __asm __volatile("rdmsr" : "=a" (low), "=d" (high) : "c" (msr)); 343 return (low | ((uint64_t)high << 32)); 344 } 345 346 static __inline uint64_t 347 rdpmc(u_int pmc) 348 { 349 uint32_t low, high; 350 351 __asm __volatile("rdpmc" : "=a" (low), "=d" (high) : "c" (pmc)); 352 return (low | ((uint64_t)high << 32)); 353 } 354 355 static __inline uint64_t 356 rdtsc(void) 357 { 358 uint32_t low, high; 359 360 __asm __volatile("rdtsc" : "=a" (low), "=d" (high)); 361 return (low | ((uint64_t)high << 32)); 362 } 363 364 static __inline uint32_t 365 rdtsc32(void) 366 { 367 uint32_t rv; 368 369 __asm __volatile("rdtsc" : "=a" (rv) : : "edx"); 370 return (rv); 371 } 372 373 static __inline void 374 wbinvd(void) 375 { 376 __asm __volatile("wbinvd"); 377 } 378 379 static __inline void 380 write_rflags(u_long rf) 381 { 382 __asm __volatile("pushq %0; popfq" : : "r" (rf)); 383 } 384 385 static __inline void 386 wrmsr(u_int msr, uint64_t newval) 387 { 388 uint32_t low, high; 389 390 low = newval; 391 high = newval >> 32; 392 __asm __volatile("wrmsr" : : "a" (low), "d" (high), "c" (msr)); 393 } 394 395 static __inline void 396 load_cr0(u_long data) 397 { 398 399 __asm __volatile("movq %0,%%cr0" : : "r" (data)); 400 } 401 402 static __inline u_long 403 rcr0(void) 404 { 405 u_long data; 406 407 __asm __volatile("movq %%cr0,%0" : "=r" (data)); 408 return (data); 409 } 410 411 static __inline u_long 412 rcr2(void) 413 { 414 u_long data; 415 416 __asm __volatile("movq %%cr2,%0" : "=r" (data)); 417 return (data); 418 } 419 420 static __inline void 421 load_cr3(u_long data) 422 { 423 424 __asm __volatile("movq %0,%%cr3" : : "r" (data) : "memory"); 425 } 426 427 static __inline u_long 428 rcr3(void) 429 { 430 u_long data; 431 432 __asm __volatile("movq %%cr3,%0" : "=r" (data)); 433 return (data); 434 } 435 436 static __inline void 437 load_cr4(u_long data) 438 { 439 __asm __volatile("movq %0,%%cr4" : : "r" (data)); 440 } 441 442 static __inline u_long 443 rcr4(void) 444 { 445 u_long data; 446 447 __asm __volatile("movq %%cr4,%0" : "=r" (data)); 448 return (data); 449 } 450 451 static __inline u_long 452 rxcr(u_int reg) 453 { 454 u_int low, high; 455 456 __asm __volatile("xgetbv" : "=a" (low), "=d" (high) : "c" (reg)); 457 return (low | ((uint64_t)high << 32)); 458 } 459 460 static __inline void 461 load_xcr(u_int reg, u_long val) 462 { 463 u_int low, high; 464 465 low = val; 466 high = val >> 32; 467 __asm __volatile("xsetbv" : : "c" (reg), "a" (low), "d" (high)); 468 } 469 470 /* 471 * Global TLB flush (except for thise for pages marked PG_G) 472 */ 473 static __inline void 474 invltlb(void) 475 { 476 477 load_cr3(rcr3()); 478 } 479 480 #ifndef CR4_PGE 481 #define CR4_PGE 0x00000080 /* Page global enable */ 482 #endif 483 484 /* 485 * Perform the guaranteed invalidation of all TLB entries. This 486 * includes the global entries, and entries in all PCIDs, not only the 487 * current context. The function works both on non-PCID CPUs and CPUs 488 * with the PCID turned off or on. See IA-32 SDM Vol. 3a 4.10.4.1 489 * Operations that Invalidate TLBs and Paging-Structure Caches. 490 */ 491 static __inline void 492 invltlb_globpcid(void) 493 { 494 uint64_t cr4; 495 496 cr4 = rcr4(); 497 load_cr4(cr4 & ~CR4_PGE); 498 /* 499 * Although preemption at this point could be detrimental to 500 * performance, it would not lead to an error. PG_G is simply 501 * ignored if CR4.PGE is clear. Moreover, in case this block 502 * is re-entered, the load_cr4() either above or below will 503 * modify CR4.PGE flushing the TLB. 504 */ 505 load_cr4(cr4 | CR4_PGE); 506 } 507 508 /* 509 * TLB flush for an individual page (even if it has PG_G). 510 * Only works on 486+ CPUs (i386 does not have PG_G). 511 */ 512 static __inline void 513 invlpg(u_long addr) 514 { 515 516 __asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory"); 517 } 518 519 #define INVPCID_ADDR 0 520 #define INVPCID_CTX 1 521 #define INVPCID_CTXGLOB 2 522 #define INVPCID_ALLCTX 3 523 524 struct invpcid_descr { 525 uint64_t pcid:12 __packed; 526 uint64_t pad:52 __packed; 527 uint64_t addr; 528 } __packed; 529 530 static __inline void 531 invpcid(struct invpcid_descr *d, int type) 532 { 533 534 /* invpcid (%rdx),%rax */ 535 __asm __volatile(".byte 0x66,0x0f,0x38,0x82,0x02" 536 : : "d" (d), "a" ((u_long)type) : "memory"); 537 } 538 539 static __inline u_short 540 rfs(void) 541 { 542 u_short sel; 543 __asm __volatile("movw %%fs,%0" : "=rm" (sel)); 544 return (sel); 545 } 546 547 static __inline u_short 548 rgs(void) 549 { 550 u_short sel; 551 __asm __volatile("movw %%gs,%0" : "=rm" (sel)); 552 return (sel); 553 } 554 555 static __inline u_short 556 rss(void) 557 { 558 u_short sel; 559 __asm __volatile("movw %%ss,%0" : "=rm" (sel)); 560 return (sel); 561 } 562 563 static __inline void 564 load_ds(u_short sel) 565 { 566 __asm __volatile("movw %0,%%ds" : : "rm" (sel)); 567 } 568 569 static __inline void 570 load_es(u_short sel) 571 { 572 __asm __volatile("movw %0,%%es" : : "rm" (sel)); 573 } 574 575 static __inline void 576 cpu_monitor(const void *addr, u_long extensions, u_int hints) 577 { 578 579 __asm __volatile("monitor" 580 : : "a" (addr), "c" (extensions), "d" (hints)); 581 } 582 583 static __inline void 584 cpu_mwait(u_long extensions, u_int hints) 585 { 586 587 __asm __volatile("mwait" : : "a" (hints), "c" (extensions)); 588 } 589 590 #ifdef _KERNEL 591 /* This is defined in <machine/specialreg.h> but is too painful to get to */ 592 #ifndef MSR_FSBASE 593 #define MSR_FSBASE 0xc0000100 594 #endif 595 static __inline void 596 load_fs(u_short sel) 597 { 598 /* Preserve the fsbase value across the selector load */ 599 __asm __volatile("rdmsr; movw %0,%%fs; wrmsr" 600 : : "rm" (sel), "c" (MSR_FSBASE) : "eax", "edx"); 601 } 602 603 #ifndef MSR_GSBASE 604 #define MSR_GSBASE 0xc0000101 605 #endif 606 static __inline void 607 load_gs(u_short sel) 608 { 609 /* 610 * Preserve the gsbase value across the selector load. 611 * Note that we have to disable interrupts because the gsbase 612 * being trashed happens to be the kernel gsbase at the time. 613 */ 614 __asm __volatile("pushfq; cli; rdmsr; movw %0,%%gs; wrmsr; popfq" 615 : : "rm" (sel), "c" (MSR_GSBASE) : "eax", "edx"); 616 } 617 #else 618 /* Usable by userland */ 619 static __inline void 620 load_fs(u_short sel) 621 { 622 __asm __volatile("movw %0,%%fs" : : "rm" (sel)); 623 } 624 625 static __inline void 626 load_gs(u_short sel) 627 { 628 __asm __volatile("movw %0,%%gs" : : "rm" (sel)); 629 } 630 #endif 631 632 static __inline void 633 lidt(struct region_descriptor *addr) 634 { 635 __asm __volatile("lidt (%0)" : : "r" (addr)); 636 } 637 638 static __inline void 639 lldt(u_short sel) 640 { 641 __asm __volatile("lldt %0" : : "r" (sel)); 642 } 643 644 static __inline void 645 ltr(u_short sel) 646 { 647 __asm __volatile("ltr %0" : : "r" (sel)); 648 } 649 650 static __inline uint64_t 651 rdr0(void) 652 { 653 uint64_t data; 654 __asm __volatile("movq %%dr0,%0" : "=r" (data)); 655 return (data); 656 } 657 658 static __inline void 659 load_dr0(uint64_t dr0) 660 { 661 __asm __volatile("movq %0,%%dr0" : : "r" (dr0)); 662 } 663 664 static __inline uint64_t 665 rdr1(void) 666 { 667 uint64_t data; 668 __asm __volatile("movq %%dr1,%0" : "=r" (data)); 669 return (data); 670 } 671 672 static __inline void 673 load_dr1(uint64_t dr1) 674 { 675 __asm __volatile("movq %0,%%dr1" : : "r" (dr1)); 676 } 677 678 static __inline uint64_t 679 rdr2(void) 680 { 681 uint64_t data; 682 __asm __volatile("movq %%dr2,%0" : "=r" (data)); 683 return (data); 684 } 685 686 static __inline void 687 load_dr2(uint64_t dr2) 688 { 689 __asm __volatile("movq %0,%%dr2" : : "r" (dr2)); 690 } 691 692 static __inline uint64_t 693 rdr3(void) 694 { 695 uint64_t data; 696 __asm __volatile("movq %%dr3,%0" : "=r" (data)); 697 return (data); 698 } 699 700 static __inline void 701 load_dr3(uint64_t dr3) 702 { 703 __asm __volatile("movq %0,%%dr3" : : "r" (dr3)); 704 } 705 706 static __inline uint64_t 707 rdr4(void) 708 { 709 uint64_t data; 710 __asm __volatile("movq %%dr4,%0" : "=r" (data)); 711 return (data); 712 } 713 714 static __inline void 715 load_dr4(uint64_t dr4) 716 { 717 __asm __volatile("movq %0,%%dr4" : : "r" (dr4)); 718 } 719 720 static __inline uint64_t 721 rdr5(void) 722 { 723 uint64_t data; 724 __asm __volatile("movq %%dr5,%0" : "=r" (data)); 725 return (data); 726 } 727 728 static __inline void 729 load_dr5(uint64_t dr5) 730 { 731 __asm __volatile("movq %0,%%dr5" : : "r" (dr5)); 732 } 733 734 static __inline uint64_t 735 rdr6(void) 736 { 737 uint64_t data; 738 __asm __volatile("movq %%dr6,%0" : "=r" (data)); 739 return (data); 740 } 741 742 static __inline void 743 load_dr6(uint64_t dr6) 744 { 745 __asm __volatile("movq %0,%%dr6" : : "r" (dr6)); 746 } 747 748 static __inline uint64_t 749 rdr7(void) 750 { 751 uint64_t data; 752 __asm __volatile("movq %%dr7,%0" : "=r" (data)); 753 return (data); 754 } 755 756 static __inline void 757 load_dr7(uint64_t dr7) 758 { 759 __asm __volatile("movq %0,%%dr7" : : "r" (dr7)); 760 } 761 762 static __inline register_t 763 intr_disable(void) 764 { 765 register_t rflags; 766 767 rflags = read_rflags(); 768 disable_intr(); 769 return (rflags); 770 } 771 772 static __inline void 773 intr_restore(register_t rflags) 774 { 775 write_rflags(rflags); 776 } 777 778 #else /* !(__GNUCLIKE_ASM && __CC_SUPPORTS___INLINE) */ 779 780 int breakpoint(void); 781 u_int bsfl(u_int mask); 782 u_int bsrl(u_int mask); 783 void clflush(u_long addr); 784 void clts(void); 785 void cpuid_count(u_int ax, u_int cx, u_int *p); 786 void disable_intr(void); 787 void do_cpuid(u_int ax, u_int *p); 788 void enable_intr(void); 789 void halt(void); 790 void ia32_pause(void); 791 u_char inb(u_int port); 792 u_int inl(u_int port); 793 void insb(u_int port, void *addr, size_t count); 794 void insl(u_int port, void *addr, size_t count); 795 void insw(u_int port, void *addr, size_t count); 796 register_t intr_disable(void); 797 void intr_restore(register_t rf); 798 void invd(void); 799 void invlpg(u_int addr); 800 void invltlb(void); 801 u_short inw(u_int port); 802 void lidt(struct region_descriptor *addr); 803 void lldt(u_short sel); 804 void load_cr0(u_long cr0); 805 void load_cr3(u_long cr3); 806 void load_cr4(u_long cr4); 807 void load_dr0(uint64_t dr0); 808 void load_dr1(uint64_t dr1); 809 void load_dr2(uint64_t dr2); 810 void load_dr3(uint64_t dr3); 811 void load_dr4(uint64_t dr4); 812 void load_dr5(uint64_t dr5); 813 void load_dr6(uint64_t dr6); 814 void load_dr7(uint64_t dr7); 815 void load_fs(u_short sel); 816 void load_gs(u_short sel); 817 void ltr(u_short sel); 818 void outb(u_int port, u_char data); 819 void outl(u_int port, u_int data); 820 void outsb(u_int port, const void *addr, size_t count); 821 void outsl(u_int port, const void *addr, size_t count); 822 void outsw(u_int port, const void *addr, size_t count); 823 void outw(u_int port, u_short data); 824 u_long rcr0(void); 825 u_long rcr2(void); 826 u_long rcr3(void); 827 u_long rcr4(void); 828 uint64_t rdmsr(u_int msr); 829 uint64_t rdpmc(u_int pmc); 830 uint64_t rdr0(void); 831 uint64_t rdr1(void); 832 uint64_t rdr2(void); 833 uint64_t rdr3(void); 834 uint64_t rdr4(void); 835 uint64_t rdr5(void); 836 uint64_t rdr6(void); 837 uint64_t rdr7(void); 838 uint64_t rdtsc(void); 839 u_long read_rflags(void); 840 u_int rfs(void); 841 u_int rgs(void); 842 void wbinvd(void); 843 void write_rflags(u_int rf); 844 void wrmsr(u_int msr, uint64_t newval); 845 846 #endif /* __GNUCLIKE_ASM && __CC_SUPPORTS___INLINE */ 847 848 void reset_dbregs(void); 849 850 #ifdef _KERNEL 851 int rdmsr_safe(u_int msr, uint64_t *val); 852 int wrmsr_safe(u_int msr, uint64_t newval); 853 #endif 854 855 #endif /* !_MACHINE_CPUFUNC_H_ */ 856