1 /*- 2 * Copyright (c) 2003 Peter Wemm. 3 * Copyright (c) 1993 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 4. Neither the name of the University nor the names of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD$ 31 */ 32 33 /* 34 * Functions to provide access to special i386 instructions. 35 * This in included in sys/systm.h, and that file should be 36 * used in preference to this. 37 */ 38 39 #ifndef _MACHINE_CPUFUNC_H_ 40 #define _MACHINE_CPUFUNC_H_ 41 42 #ifndef _SYS_CDEFS_H_ 43 #error this file needs sys/cdefs.h as a prerequisite 44 #endif 45 46 struct region_descriptor; 47 48 #define readb(va) (*(volatile uint8_t *) (va)) 49 #define readw(va) (*(volatile uint16_t *) (va)) 50 #define readl(va) (*(volatile uint32_t *) (va)) 51 #define readq(va) (*(volatile uint64_t *) (va)) 52 53 #define writeb(va, d) (*(volatile uint8_t *) (va) = (d)) 54 #define writew(va, d) (*(volatile uint16_t *) (va) = (d)) 55 #define writel(va, d) (*(volatile uint32_t *) (va) = (d)) 56 #define writeq(va, d) (*(volatile uint64_t *) (va) = (d)) 57 58 #if defined(__GNUCLIKE_ASM) && defined(__CC_SUPPORTS___INLINE) 59 60 static __inline void 61 breakpoint(void) 62 { 63 __asm __volatile("int $3"); 64 } 65 66 static __inline u_int 67 bsfl(u_int mask) 68 { 69 u_int result; 70 71 __asm __volatile("bsfl %1,%0" : "=r" (result) : "rm" (mask)); 72 return (result); 73 } 74 75 static __inline u_long 76 bsfq(u_long mask) 77 { 78 u_long result; 79 80 __asm __volatile("bsfq %1,%0" : "=r" (result) : "rm" (mask)); 81 return (result); 82 } 83 84 static __inline u_int 85 bsrl(u_int mask) 86 { 87 u_int result; 88 89 __asm __volatile("bsrl %1,%0" : "=r" (result) : "rm" (mask)); 90 return (result); 91 } 92 93 static __inline u_long 94 bsrq(u_long mask) 95 { 96 u_long result; 97 98 __asm __volatile("bsrq %1,%0" : "=r" (result) : "rm" (mask)); 99 return (result); 100 } 101 102 static __inline void 103 clflush(u_long addr) 104 { 105 106 __asm __volatile("clflush %0" : : "m" (*(char *)addr)); 107 } 108 109 static __inline void 110 clts(void) 111 { 112 113 __asm __volatile("clts"); 114 } 115 116 static __inline void 117 disable_intr(void) 118 { 119 __asm __volatile("cli" : : : "memory"); 120 } 121 122 static __inline void 123 do_cpuid(u_int ax, u_int *p) 124 { 125 __asm __volatile("cpuid" 126 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3]) 127 : "0" (ax)); 128 } 129 130 static __inline void 131 cpuid_count(u_int ax, u_int cx, u_int *p) 132 { 133 __asm __volatile("cpuid" 134 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3]) 135 : "0" (ax), "c" (cx)); 136 } 137 138 static __inline void 139 enable_intr(void) 140 { 141 __asm __volatile("sti"); 142 } 143 144 #ifdef _KERNEL 145 146 #define HAVE_INLINE_FFS 147 #define ffs(x) __builtin_ffs(x) 148 149 #define HAVE_INLINE_FFSL 150 151 static __inline int 152 ffsl(long mask) 153 { 154 return (mask == 0 ? mask : (int)bsfq((u_long)mask) + 1); 155 } 156 157 #define HAVE_INLINE_FLS 158 159 static __inline int 160 fls(int mask) 161 { 162 return (mask == 0 ? mask : (int)bsrl((u_int)mask) + 1); 163 } 164 165 #define HAVE_INLINE_FLSL 166 167 static __inline int 168 flsl(long mask) 169 { 170 return (mask == 0 ? mask : (int)bsrq((u_long)mask) + 1); 171 } 172 173 #endif /* _KERNEL */ 174 175 static __inline void 176 halt(void) 177 { 178 __asm __volatile("hlt"); 179 } 180 181 static __inline u_char 182 inb(u_int port) 183 { 184 u_char data; 185 186 __asm __volatile("inb %w1, %0" : "=a" (data) : "Nd" (port)); 187 return (data); 188 } 189 190 static __inline u_int 191 inl(u_int port) 192 { 193 u_int data; 194 195 __asm __volatile("inl %w1, %0" : "=a" (data) : "Nd" (port)); 196 return (data); 197 } 198 199 static __inline void 200 insb(u_int port, void *addr, size_t count) 201 { 202 __asm __volatile("cld; rep; insb" 203 : "+D" (addr), "+c" (count) 204 : "d" (port) 205 : "memory"); 206 } 207 208 static __inline void 209 insw(u_int port, void *addr, size_t count) 210 { 211 __asm __volatile("cld; rep; insw" 212 : "+D" (addr), "+c" (count) 213 : "d" (port) 214 : "memory"); 215 } 216 217 static __inline void 218 insl(u_int port, void *addr, size_t count) 219 { 220 __asm __volatile("cld; rep; insl" 221 : "+D" (addr), "+c" (count) 222 : "d" (port) 223 : "memory"); 224 } 225 226 static __inline void 227 invd(void) 228 { 229 __asm __volatile("invd"); 230 } 231 232 static __inline u_short 233 inw(u_int port) 234 { 235 u_short data; 236 237 __asm __volatile("inw %w1, %0" : "=a" (data) : "Nd" (port)); 238 return (data); 239 } 240 241 static __inline void 242 outb(u_int port, u_char data) 243 { 244 __asm __volatile("outb %0, %w1" : : "a" (data), "Nd" (port)); 245 } 246 247 static __inline void 248 outl(u_int port, u_int data) 249 { 250 __asm __volatile("outl %0, %w1" : : "a" (data), "Nd" (port)); 251 } 252 253 static __inline void 254 outsb(u_int port, const void *addr, size_t count) 255 { 256 __asm __volatile("cld; rep; outsb" 257 : "+S" (addr), "+c" (count) 258 : "d" (port)); 259 } 260 261 static __inline void 262 outsw(u_int port, const void *addr, size_t count) 263 { 264 __asm __volatile("cld; rep; outsw" 265 : "+S" (addr), "+c" (count) 266 : "d" (port)); 267 } 268 269 static __inline void 270 outsl(u_int port, const void *addr, size_t count) 271 { 272 __asm __volatile("cld; rep; outsl" 273 : "+S" (addr), "+c" (count) 274 : "d" (port)); 275 } 276 277 static __inline void 278 outw(u_int port, u_short data) 279 { 280 __asm __volatile("outw %0, %w1" : : "a" (data), "Nd" (port)); 281 } 282 283 static __inline u_long 284 popcntq(u_long mask) 285 { 286 u_long result; 287 288 __asm __volatile("popcntq %1,%0" : "=r" (result) : "rm" (mask)); 289 return (result); 290 } 291 292 static __inline void 293 lfence(void) 294 { 295 296 __asm __volatile("lfence" : : : "memory"); 297 } 298 299 static __inline void 300 mfence(void) 301 { 302 303 __asm __volatile("mfence" : : : "memory"); 304 } 305 306 static __inline void 307 ia32_pause(void) 308 { 309 __asm __volatile("pause"); 310 } 311 312 static __inline u_long 313 read_rflags(void) 314 { 315 u_long rf; 316 317 __asm __volatile("pushfq; popq %0" : "=r" (rf)); 318 return (rf); 319 } 320 321 static __inline uint64_t 322 rdmsr(u_int msr) 323 { 324 uint32_t low, high; 325 326 __asm __volatile("rdmsr" : "=a" (low), "=d" (high) : "c" (msr)); 327 return (low | ((uint64_t)high << 32)); 328 } 329 330 static __inline uint64_t 331 rdpmc(u_int pmc) 332 { 333 uint32_t low, high; 334 335 __asm __volatile("rdpmc" : "=a" (low), "=d" (high) : "c" (pmc)); 336 return (low | ((uint64_t)high << 32)); 337 } 338 339 static __inline uint64_t 340 rdtsc(void) 341 { 342 uint32_t low, high; 343 344 __asm __volatile("rdtsc" : "=a" (low), "=d" (high)); 345 return (low | ((uint64_t)high << 32)); 346 } 347 348 static __inline uint32_t 349 rdtsc32(void) 350 { 351 uint32_t rv; 352 353 __asm __volatile("rdtsc" : "=a" (rv) : : "edx"); 354 return (rv); 355 } 356 357 static __inline void 358 wbinvd(void) 359 { 360 __asm __volatile("wbinvd"); 361 } 362 363 static __inline void 364 write_rflags(u_long rf) 365 { 366 __asm __volatile("pushq %0; popfq" : : "r" (rf)); 367 } 368 369 static __inline void 370 wrmsr(u_int msr, uint64_t newval) 371 { 372 uint32_t low, high; 373 374 low = newval; 375 high = newval >> 32; 376 __asm __volatile("wrmsr" : : "a" (low), "d" (high), "c" (msr)); 377 } 378 379 static __inline void 380 load_cr0(u_long data) 381 { 382 383 __asm __volatile("movq %0,%%cr0" : : "r" (data)); 384 } 385 386 static __inline u_long 387 rcr0(void) 388 { 389 u_long data; 390 391 __asm __volatile("movq %%cr0,%0" : "=r" (data)); 392 return (data); 393 } 394 395 static __inline u_long 396 rcr2(void) 397 { 398 u_long data; 399 400 __asm __volatile("movq %%cr2,%0" : "=r" (data)); 401 return (data); 402 } 403 404 static __inline void 405 load_cr3(u_long data) 406 { 407 408 __asm __volatile("movq %0,%%cr3" : : "r" (data) : "memory"); 409 } 410 411 static __inline u_long 412 rcr3(void) 413 { 414 u_long data; 415 416 __asm __volatile("movq %%cr3,%0" : "=r" (data)); 417 return (data); 418 } 419 420 static __inline void 421 load_cr4(u_long data) 422 { 423 __asm __volatile("movq %0,%%cr4" : : "r" (data)); 424 } 425 426 static __inline u_long 427 rcr4(void) 428 { 429 u_long data; 430 431 __asm __volatile("movq %%cr4,%0" : "=r" (data)); 432 return (data); 433 } 434 435 static __inline u_long 436 rxcr(u_int reg) 437 { 438 u_int low, high; 439 440 __asm __volatile("xgetbv" : "=a" (low), "=d" (high) : "c" (reg)); 441 return (low | ((uint64_t)high << 32)); 442 } 443 444 static __inline void 445 load_xcr(u_int reg, u_long val) 446 { 447 u_int low, high; 448 449 low = val; 450 high = val >> 32; 451 __asm __volatile("xsetbv" : : "c" (reg), "a" (low), "d" (high)); 452 } 453 454 /* 455 * Global TLB flush (except for thise for pages marked PG_G) 456 */ 457 static __inline void 458 invltlb(void) 459 { 460 461 load_cr3(rcr3()); 462 } 463 464 /* 465 * TLB flush for an individual page (even if it has PG_G). 466 * Only works on 486+ CPUs (i386 does not have PG_G). 467 */ 468 static __inline void 469 invlpg(u_long addr) 470 { 471 472 __asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory"); 473 } 474 475 static __inline u_short 476 rfs(void) 477 { 478 u_short sel; 479 __asm __volatile("movw %%fs,%0" : "=rm" (sel)); 480 return (sel); 481 } 482 483 static __inline u_short 484 rgs(void) 485 { 486 u_short sel; 487 __asm __volatile("movw %%gs,%0" : "=rm" (sel)); 488 return (sel); 489 } 490 491 static __inline u_short 492 rss(void) 493 { 494 u_short sel; 495 __asm __volatile("movw %%ss,%0" : "=rm" (sel)); 496 return (sel); 497 } 498 499 static __inline void 500 load_ds(u_short sel) 501 { 502 __asm __volatile("movw %0,%%ds" : : "rm" (sel)); 503 } 504 505 static __inline void 506 load_es(u_short sel) 507 { 508 __asm __volatile("movw %0,%%es" : : "rm" (sel)); 509 } 510 511 static __inline void 512 cpu_monitor(const void *addr, u_long extensions, u_int hints) 513 { 514 515 __asm __volatile("monitor" 516 : : "a" (addr), "c" (extensions), "d" (hints)); 517 } 518 519 static __inline void 520 cpu_mwait(u_long extensions, u_int hints) 521 { 522 523 __asm __volatile("mwait" : : "a" (hints), "c" (extensions)); 524 } 525 526 #ifdef _KERNEL 527 /* This is defined in <machine/specialreg.h> but is too painful to get to */ 528 #ifndef MSR_FSBASE 529 #define MSR_FSBASE 0xc0000100 530 #endif 531 static __inline void 532 load_fs(u_short sel) 533 { 534 /* Preserve the fsbase value across the selector load */ 535 __asm __volatile("rdmsr; movw %0,%%fs; wrmsr" 536 : : "rm" (sel), "c" (MSR_FSBASE) : "eax", "edx"); 537 } 538 539 #ifndef MSR_GSBASE 540 #define MSR_GSBASE 0xc0000101 541 #endif 542 static __inline void 543 load_gs(u_short sel) 544 { 545 /* 546 * Preserve the gsbase value across the selector load. 547 * Note that we have to disable interrupts because the gsbase 548 * being trashed happens to be the kernel gsbase at the time. 549 */ 550 __asm __volatile("pushfq; cli; rdmsr; movw %0,%%gs; wrmsr; popfq" 551 : : "rm" (sel), "c" (MSR_GSBASE) : "eax", "edx"); 552 } 553 #else 554 /* Usable by userland */ 555 static __inline void 556 load_fs(u_short sel) 557 { 558 __asm __volatile("movw %0,%%fs" : : "rm" (sel)); 559 } 560 561 static __inline void 562 load_gs(u_short sel) 563 { 564 __asm __volatile("movw %0,%%gs" : : "rm" (sel)); 565 } 566 #endif 567 568 static __inline void 569 lidt(struct region_descriptor *addr) 570 { 571 __asm __volatile("lidt (%0)" : : "r" (addr)); 572 } 573 574 static __inline void 575 lldt(u_short sel) 576 { 577 __asm __volatile("lldt %0" : : "r" (sel)); 578 } 579 580 static __inline void 581 ltr(u_short sel) 582 { 583 __asm __volatile("ltr %0" : : "r" (sel)); 584 } 585 586 static __inline uint64_t 587 rdr0(void) 588 { 589 uint64_t data; 590 __asm __volatile("movq %%dr0,%0" : "=r" (data)); 591 return (data); 592 } 593 594 static __inline void 595 load_dr0(uint64_t dr0) 596 { 597 __asm __volatile("movq %0,%%dr0" : : "r" (dr0)); 598 } 599 600 static __inline uint64_t 601 rdr1(void) 602 { 603 uint64_t data; 604 __asm __volatile("movq %%dr1,%0" : "=r" (data)); 605 return (data); 606 } 607 608 static __inline void 609 load_dr1(uint64_t dr1) 610 { 611 __asm __volatile("movq %0,%%dr1" : : "r" (dr1)); 612 } 613 614 static __inline uint64_t 615 rdr2(void) 616 { 617 uint64_t data; 618 __asm __volatile("movq %%dr2,%0" : "=r" (data)); 619 return (data); 620 } 621 622 static __inline void 623 load_dr2(uint64_t dr2) 624 { 625 __asm __volatile("movq %0,%%dr2" : : "r" (dr2)); 626 } 627 628 static __inline uint64_t 629 rdr3(void) 630 { 631 uint64_t data; 632 __asm __volatile("movq %%dr3,%0" : "=r" (data)); 633 return (data); 634 } 635 636 static __inline void 637 load_dr3(uint64_t dr3) 638 { 639 __asm __volatile("movq %0,%%dr3" : : "r" (dr3)); 640 } 641 642 static __inline uint64_t 643 rdr4(void) 644 { 645 uint64_t data; 646 __asm __volatile("movq %%dr4,%0" : "=r" (data)); 647 return (data); 648 } 649 650 static __inline void 651 load_dr4(uint64_t dr4) 652 { 653 __asm __volatile("movq %0,%%dr4" : : "r" (dr4)); 654 } 655 656 static __inline uint64_t 657 rdr5(void) 658 { 659 uint64_t data; 660 __asm __volatile("movq %%dr5,%0" : "=r" (data)); 661 return (data); 662 } 663 664 static __inline void 665 load_dr5(uint64_t dr5) 666 { 667 __asm __volatile("movq %0,%%dr5" : : "r" (dr5)); 668 } 669 670 static __inline uint64_t 671 rdr6(void) 672 { 673 uint64_t data; 674 __asm __volatile("movq %%dr6,%0" : "=r" (data)); 675 return (data); 676 } 677 678 static __inline void 679 load_dr6(uint64_t dr6) 680 { 681 __asm __volatile("movq %0,%%dr6" : : "r" (dr6)); 682 } 683 684 static __inline uint64_t 685 rdr7(void) 686 { 687 uint64_t data; 688 __asm __volatile("movq %%dr7,%0" : "=r" (data)); 689 return (data); 690 } 691 692 static __inline void 693 load_dr7(uint64_t dr7) 694 { 695 __asm __volatile("movq %0,%%dr7" : : "r" (dr7)); 696 } 697 698 static __inline register_t 699 intr_disable(void) 700 { 701 register_t rflags; 702 703 rflags = read_rflags(); 704 disable_intr(); 705 return (rflags); 706 } 707 708 static __inline void 709 intr_restore(register_t rflags) 710 { 711 write_rflags(rflags); 712 } 713 714 #else /* !(__GNUCLIKE_ASM && __CC_SUPPORTS___INLINE) */ 715 716 int breakpoint(void); 717 u_int bsfl(u_int mask); 718 u_int bsrl(u_int mask); 719 void clflush(u_long addr); 720 void clts(void); 721 void cpuid_count(u_int ax, u_int cx, u_int *p); 722 void disable_intr(void); 723 void do_cpuid(u_int ax, u_int *p); 724 void enable_intr(void); 725 void halt(void); 726 void ia32_pause(void); 727 u_char inb(u_int port); 728 u_int inl(u_int port); 729 void insb(u_int port, void *addr, size_t count); 730 void insl(u_int port, void *addr, size_t count); 731 void insw(u_int port, void *addr, size_t count); 732 register_t intr_disable(void); 733 void intr_restore(register_t rf); 734 void invd(void); 735 void invlpg(u_int addr); 736 void invltlb(void); 737 u_short inw(u_int port); 738 void lidt(struct region_descriptor *addr); 739 void lldt(u_short sel); 740 void load_cr0(u_long cr0); 741 void load_cr3(u_long cr3); 742 void load_cr4(u_long cr4); 743 void load_dr0(uint64_t dr0); 744 void load_dr1(uint64_t dr1); 745 void load_dr2(uint64_t dr2); 746 void load_dr3(uint64_t dr3); 747 void load_dr4(uint64_t dr4); 748 void load_dr5(uint64_t dr5); 749 void load_dr6(uint64_t dr6); 750 void load_dr7(uint64_t dr7); 751 void load_fs(u_short sel); 752 void load_gs(u_short sel); 753 void ltr(u_short sel); 754 void outb(u_int port, u_char data); 755 void outl(u_int port, u_int data); 756 void outsb(u_int port, const void *addr, size_t count); 757 void outsl(u_int port, const void *addr, size_t count); 758 void outsw(u_int port, const void *addr, size_t count); 759 void outw(u_int port, u_short data); 760 u_long rcr0(void); 761 u_long rcr2(void); 762 u_long rcr3(void); 763 u_long rcr4(void); 764 uint64_t rdmsr(u_int msr); 765 uint64_t rdpmc(u_int pmc); 766 uint64_t rdr0(void); 767 uint64_t rdr1(void); 768 uint64_t rdr2(void); 769 uint64_t rdr3(void); 770 uint64_t rdr4(void); 771 uint64_t rdr5(void); 772 uint64_t rdr6(void); 773 uint64_t rdr7(void); 774 uint64_t rdtsc(void); 775 u_long read_rflags(void); 776 u_int rfs(void); 777 u_int rgs(void); 778 void wbinvd(void); 779 void write_rflags(u_int rf); 780 void wrmsr(u_int msr, uint64_t newval); 781 782 #endif /* __GNUCLIKE_ASM && __CC_SUPPORTS___INLINE */ 783 784 void reset_dbregs(void); 785 786 #ifdef _KERNEL 787 int rdmsr_safe(u_int msr, uint64_t *val); 788 int wrmsr_safe(u_int msr, uint64_t newval); 789 #endif 790 791 #endif /* !_MACHINE_CPUFUNC_H_ */ 792