1 /*- 2 * Copyright (c) 1998 Doug Rabson 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 #ifndef _MACHINE_ATOMIC_H_ 29 #define _MACHINE_ATOMIC_H_ 30 31 #ifndef _SYS_CDEFS_H_ 32 #error this file needs sys/cdefs.h as a prerequisite 33 #endif 34 35 /* 36 * To express interprocessor (as opposed to processor and device) memory 37 * ordering constraints, use the atomic_*() functions with acquire and release 38 * semantics rather than the *mb() functions. An architecture's memory 39 * ordering (or memory consistency) model governs the order in which a 40 * program's accesses to different locations may be performed by an 41 * implementation of that architecture. In general, for memory regions 42 * defined as writeback cacheable, the memory ordering implemented by amd64 43 * processors preserves the program ordering of a load followed by a load, a 44 * load followed by a store, and a store followed by a store. Only a store 45 * followed by a load to a different memory location may be reordered. 46 * Therefore, except for special cases, like non-temporal memory accesses or 47 * memory regions defined as write combining, the memory ordering effects 48 * provided by the sfence instruction in the wmb() function and the lfence 49 * instruction in the rmb() function are redundant. In contrast, the 50 * atomic_*() functions with acquire and release semantics do not perform 51 * redundant instructions for ordinary cases of interprocessor memory 52 * ordering on any architecture. 53 */ 54 #define mb() __asm __volatile("mfence;" : : : "memory") 55 #define wmb() __asm __volatile("sfence;" : : : "memory") 56 #define rmb() __asm __volatile("lfence;" : : : "memory") 57 58 /* 59 * Various simple operations on memory, each of which is atomic in the 60 * presence of interrupts and multiple processors. 61 * 62 * atomic_set_char(P, V) (*(u_char *)(P) |= (V)) 63 * atomic_clear_char(P, V) (*(u_char *)(P) &= ~(V)) 64 * atomic_add_char(P, V) (*(u_char *)(P) += (V)) 65 * atomic_subtract_char(P, V) (*(u_char *)(P) -= (V)) 66 * 67 * atomic_set_short(P, V) (*(u_short *)(P) |= (V)) 68 * atomic_clear_short(P, V) (*(u_short *)(P) &= ~(V)) 69 * atomic_add_short(P, V) (*(u_short *)(P) += (V)) 70 * atomic_subtract_short(P, V) (*(u_short *)(P) -= (V)) 71 * 72 * atomic_set_int(P, V) (*(u_int *)(P) |= (V)) 73 * atomic_clear_int(P, V) (*(u_int *)(P) &= ~(V)) 74 * atomic_add_int(P, V) (*(u_int *)(P) += (V)) 75 * atomic_subtract_int(P, V) (*(u_int *)(P) -= (V)) 76 * atomic_swap_int(P, V) (return (*(u_int *)(P)); *(u_int *)(P) = (V);) 77 * atomic_readandclear_int(P) (return (*(u_int *)(P)); *(u_int *)(P) = 0;) 78 * 79 * atomic_set_long(P, V) (*(u_long *)(P) |= (V)) 80 * atomic_clear_long(P, V) (*(u_long *)(P) &= ~(V)) 81 * atomic_add_long(P, V) (*(u_long *)(P) += (V)) 82 * atomic_subtract_long(P, V) (*(u_long *)(P) -= (V)) 83 * atomic_swap_long(P, V) (return (*(u_long *)(P)); *(u_long *)(P) = (V);) 84 * atomic_readandclear_long(P) (return (*(u_long *)(P)); *(u_long *)(P) = 0;) 85 */ 86 87 /* 88 * The above functions are expanded inline in the statically-linked 89 * kernel. Lock prefixes are generated if an SMP kernel is being 90 * built. 91 * 92 * Kernel modules call real functions which are built into the kernel. 93 * This allows kernel modules to be portable between UP and SMP systems. 94 */ 95 #if defined(KLD_MODULE) || !defined(__GNUCLIKE_ASM) 96 #define ATOMIC_ASM(NAME, TYPE, OP, CONS, V) \ 97 void atomic_##NAME##_##TYPE(volatile u_##TYPE *p, u_##TYPE v); \ 98 void atomic_##NAME##_barr_##TYPE(volatile u_##TYPE *p, u_##TYPE v) 99 100 int atomic_cmpset_int(volatile u_int *dst, u_int expect, u_int src); 101 int atomic_cmpset_long(volatile u_long *dst, u_long expect, u_long src); 102 u_int atomic_fetchadd_int(volatile u_int *p, u_int v); 103 u_long atomic_fetchadd_long(volatile u_long *p, u_long v); 104 int atomic_testandset_int(volatile u_int *p, u_int v); 105 int atomic_testandset_long(volatile u_long *p, u_int v); 106 void atomic_thread_fence_acq(void); 107 void atomic_thread_fence_acq_rel(void); 108 void atomic_thread_fence_rel(void); 109 void atomic_thread_fence_seq_cst(void); 110 111 #define ATOMIC_LOAD(TYPE) \ 112 u_##TYPE atomic_load_acq_##TYPE(volatile u_##TYPE *p) 113 #define ATOMIC_STORE(TYPE) \ 114 void atomic_store_rel_##TYPE(volatile u_##TYPE *p, u_##TYPE v) 115 116 #else /* !KLD_MODULE && __GNUCLIKE_ASM */ 117 118 /* 119 * For userland, always use lock prefixes so that the binaries will run 120 * on both SMP and !SMP systems. 121 */ 122 #if defined(SMP) || !defined(_KERNEL) 123 #define MPLOCKED "lock ; " 124 #else 125 #define MPLOCKED 126 #endif 127 128 /* 129 * The assembly is volatilized to avoid code chunk removal by the compiler. 130 * GCC aggressively reorders operations and memory clobbering is necessary 131 * in order to avoid that for memory barriers. 132 */ 133 #define ATOMIC_ASM(NAME, TYPE, OP, CONS, V) \ 134 static __inline void \ 135 atomic_##NAME##_##TYPE(volatile u_##TYPE *p, u_##TYPE v)\ 136 { \ 137 __asm __volatile(MPLOCKED OP \ 138 : "+m" (*p) \ 139 : CONS (V) \ 140 : "cc"); \ 141 } \ 142 \ 143 static __inline void \ 144 atomic_##NAME##_barr_##TYPE(volatile u_##TYPE *p, u_##TYPE v)\ 145 { \ 146 __asm __volatile(MPLOCKED OP \ 147 : "+m" (*p) \ 148 : CONS (V) \ 149 : "memory", "cc"); \ 150 } \ 151 struct __hack 152 153 /* 154 * Atomic compare and set, used by the mutex functions 155 * 156 * if (*dst == expect) *dst = src (all 32 bit words) 157 * 158 * Returns 0 on failure, non-zero on success 159 */ 160 161 static __inline int 162 atomic_cmpset_int(volatile u_int *dst, u_int expect, u_int src) 163 { 164 u_char res; 165 166 __asm __volatile( 167 " " MPLOCKED " " 168 " cmpxchgl %3,%1 ; " 169 " sete %0 ; " 170 "# atomic_cmpset_int" 171 : "=q" (res), /* 0 */ 172 "+m" (*dst), /* 1 */ 173 "+a" (expect) /* 2 */ 174 : "r" (src) /* 3 */ 175 : "memory", "cc"); 176 return (res); 177 } 178 179 static __inline int 180 atomic_cmpset_long(volatile u_long *dst, u_long expect, u_long src) 181 { 182 u_char res; 183 184 __asm __volatile( 185 " " MPLOCKED " " 186 " cmpxchgq %3,%1 ; " 187 " sete %0 ; " 188 "# atomic_cmpset_long" 189 : "=q" (res), /* 0 */ 190 "+m" (*dst), /* 1 */ 191 "+a" (expect) /* 2 */ 192 : "r" (src) /* 3 */ 193 : "memory", "cc"); 194 return (res); 195 } 196 197 /* 198 * Atomically add the value of v to the integer pointed to by p and return 199 * the previous value of *p. 200 */ 201 static __inline u_int 202 atomic_fetchadd_int(volatile u_int *p, u_int v) 203 { 204 205 __asm __volatile( 206 " " MPLOCKED " " 207 " xaddl %0,%1 ; " 208 "# atomic_fetchadd_int" 209 : "+r" (v), /* 0 */ 210 "+m" (*p) /* 1 */ 211 : : "cc"); 212 return (v); 213 } 214 215 /* 216 * Atomically add the value of v to the long integer pointed to by p and return 217 * the previous value of *p. 218 */ 219 static __inline u_long 220 atomic_fetchadd_long(volatile u_long *p, u_long v) 221 { 222 223 __asm __volatile( 224 " " MPLOCKED " " 225 " xaddq %0,%1 ; " 226 "# atomic_fetchadd_long" 227 : "+r" (v), /* 0 */ 228 "+m" (*p) /* 1 */ 229 : : "cc"); 230 return (v); 231 } 232 233 static __inline int 234 atomic_testandset_int(volatile u_int *p, u_int v) 235 { 236 u_char res; 237 238 __asm __volatile( 239 " " MPLOCKED " " 240 " btsl %2,%1 ; " 241 " setc %0 ; " 242 "# atomic_testandset_int" 243 : "=q" (res), /* 0 */ 244 "+m" (*p) /* 1 */ 245 : "Ir" (v & 0x1f) /* 2 */ 246 : "cc"); 247 return (res); 248 } 249 250 static __inline int 251 atomic_testandset_long(volatile u_long *p, u_int v) 252 { 253 u_char res; 254 255 __asm __volatile( 256 " " MPLOCKED " " 257 " btsq %2,%1 ; " 258 " setc %0 ; " 259 "# atomic_testandset_long" 260 : "=q" (res), /* 0 */ 261 "+m" (*p) /* 1 */ 262 : "Jr" ((u_long)(v & 0x3f)) /* 2 */ 263 : "cc"); 264 return (res); 265 } 266 267 /* 268 * We assume that a = b will do atomic loads and stores. Due to the 269 * IA32 memory model, a simple store guarantees release semantics. 270 * 271 * However, a load may pass a store if they are performed on distinct 272 * addresses, so we need a Store/Load barrier for sequentially 273 * consistent fences in SMP kernels. We use "lock addl $0,mem" for a 274 * Store/Load barrier, as recommended by the AMD Software Optimization 275 * Guide, and not mfence. To avoid false data dependencies, we use a 276 * special address for "mem". In the kernel, we use a private per-cpu 277 * cache line. In user space, we use a word in the stack's red zone 278 * (-8(%rsp)). 279 * 280 * For UP kernels, however, the memory of the single processor is 281 * always consistent, so we only need to stop the compiler from 282 * reordering accesses in a way that violates the semantics of acquire 283 * and release. 284 */ 285 286 #if defined(_KERNEL) 287 288 /* 289 * OFFSETOF_MONITORBUF == __pcpu_offset(pc_monitorbuf). 290 * 291 * The open-coded number is used instead of the symbolic expression to 292 * avoid a dependency on sys/pcpu.h in machine/atomic.h consumers. 293 * An assertion in amd64/vm_machdep.c ensures that the value is correct. 294 */ 295 #define OFFSETOF_MONITORBUF 0x180 296 297 #if defined(SMP) 298 static __inline void 299 __storeload_barrier(void) 300 { 301 302 __asm __volatile("lock; addl $0,%%gs:%0" 303 : "+m" (*(u_int *)OFFSETOF_MONITORBUF) : : "memory", "cc"); 304 } 305 #else /* _KERNEL && UP */ 306 static __inline void 307 __storeload_barrier(void) 308 { 309 310 __compiler_membar(); 311 } 312 #endif /* SMP */ 313 #else /* !_KERNEL */ 314 static __inline void 315 __storeload_barrier(void) 316 { 317 318 __asm __volatile("lock; addl $0,-8(%%rsp)" : : : "memory", "cc"); 319 } 320 #endif /* _KERNEL*/ 321 322 #define ATOMIC_LOAD(TYPE) \ 323 static __inline u_##TYPE \ 324 atomic_load_acq_##TYPE(volatile u_##TYPE *p) \ 325 { \ 326 u_##TYPE res; \ 327 \ 328 res = *p; \ 329 __compiler_membar(); \ 330 return (res); \ 331 } \ 332 struct __hack 333 334 #define ATOMIC_STORE(TYPE) \ 335 static __inline void \ 336 atomic_store_rel_##TYPE(volatile u_##TYPE *p, u_##TYPE v) \ 337 { \ 338 \ 339 __compiler_membar(); \ 340 *p = v; \ 341 } \ 342 struct __hack 343 344 static __inline void 345 atomic_thread_fence_acq(void) 346 { 347 348 __compiler_membar(); 349 } 350 351 static __inline void 352 atomic_thread_fence_rel(void) 353 { 354 355 __compiler_membar(); 356 } 357 358 static __inline void 359 atomic_thread_fence_acq_rel(void) 360 { 361 362 __compiler_membar(); 363 } 364 365 static __inline void 366 atomic_thread_fence_seq_cst(void) 367 { 368 369 __storeload_barrier(); 370 } 371 372 #endif /* KLD_MODULE || !__GNUCLIKE_ASM */ 373 374 ATOMIC_ASM(set, char, "orb %b1,%0", "iq", v); 375 ATOMIC_ASM(clear, char, "andb %b1,%0", "iq", ~v); 376 ATOMIC_ASM(add, char, "addb %b1,%0", "iq", v); 377 ATOMIC_ASM(subtract, char, "subb %b1,%0", "iq", v); 378 379 ATOMIC_ASM(set, short, "orw %w1,%0", "ir", v); 380 ATOMIC_ASM(clear, short, "andw %w1,%0", "ir", ~v); 381 ATOMIC_ASM(add, short, "addw %w1,%0", "ir", v); 382 ATOMIC_ASM(subtract, short, "subw %w1,%0", "ir", v); 383 384 ATOMIC_ASM(set, int, "orl %1,%0", "ir", v); 385 ATOMIC_ASM(clear, int, "andl %1,%0", "ir", ~v); 386 ATOMIC_ASM(add, int, "addl %1,%0", "ir", v); 387 ATOMIC_ASM(subtract, int, "subl %1,%0", "ir", v); 388 389 ATOMIC_ASM(set, long, "orq %1,%0", "ir", v); 390 ATOMIC_ASM(clear, long, "andq %1,%0", "ir", ~v); 391 ATOMIC_ASM(add, long, "addq %1,%0", "ir", v); 392 ATOMIC_ASM(subtract, long, "subq %1,%0", "ir", v); 393 394 #define ATOMIC_LOADSTORE(TYPE) \ 395 ATOMIC_LOAD(TYPE); \ 396 ATOMIC_STORE(TYPE) 397 398 ATOMIC_LOADSTORE(char); 399 ATOMIC_LOADSTORE(short); 400 ATOMIC_LOADSTORE(int); 401 ATOMIC_LOADSTORE(long); 402 403 #undef ATOMIC_ASM 404 #undef ATOMIC_LOAD 405 #undef ATOMIC_STORE 406 #undef ATOMIC_LOADSTORE 407 #ifndef WANT_FUNCTIONS 408 409 /* Read the current value and store a new value in the destination. */ 410 #ifdef __GNUCLIKE_ASM 411 412 static __inline u_int 413 atomic_swap_int(volatile u_int *p, u_int v) 414 { 415 416 __asm __volatile( 417 " xchgl %1,%0 ; " 418 "# atomic_swap_int" 419 : "+r" (v), /* 0 */ 420 "+m" (*p)); /* 1 */ 421 return (v); 422 } 423 424 static __inline u_long 425 atomic_swap_long(volatile u_long *p, u_long v) 426 { 427 428 __asm __volatile( 429 " xchgq %1,%0 ; " 430 "# atomic_swap_long" 431 : "+r" (v), /* 0 */ 432 "+m" (*p)); /* 1 */ 433 return (v); 434 } 435 436 #else /* !__GNUCLIKE_ASM */ 437 438 u_int atomic_swap_int(volatile u_int *p, u_int v); 439 u_long atomic_swap_long(volatile u_long *p, u_long v); 440 441 #endif /* __GNUCLIKE_ASM */ 442 443 #define atomic_set_acq_char atomic_set_barr_char 444 #define atomic_set_rel_char atomic_set_barr_char 445 #define atomic_clear_acq_char atomic_clear_barr_char 446 #define atomic_clear_rel_char atomic_clear_barr_char 447 #define atomic_add_acq_char atomic_add_barr_char 448 #define atomic_add_rel_char atomic_add_barr_char 449 #define atomic_subtract_acq_char atomic_subtract_barr_char 450 #define atomic_subtract_rel_char atomic_subtract_barr_char 451 452 #define atomic_set_acq_short atomic_set_barr_short 453 #define atomic_set_rel_short atomic_set_barr_short 454 #define atomic_clear_acq_short atomic_clear_barr_short 455 #define atomic_clear_rel_short atomic_clear_barr_short 456 #define atomic_add_acq_short atomic_add_barr_short 457 #define atomic_add_rel_short atomic_add_barr_short 458 #define atomic_subtract_acq_short atomic_subtract_barr_short 459 #define atomic_subtract_rel_short atomic_subtract_barr_short 460 461 #define atomic_set_acq_int atomic_set_barr_int 462 #define atomic_set_rel_int atomic_set_barr_int 463 #define atomic_clear_acq_int atomic_clear_barr_int 464 #define atomic_clear_rel_int atomic_clear_barr_int 465 #define atomic_add_acq_int atomic_add_barr_int 466 #define atomic_add_rel_int atomic_add_barr_int 467 #define atomic_subtract_acq_int atomic_subtract_barr_int 468 #define atomic_subtract_rel_int atomic_subtract_barr_int 469 #define atomic_cmpset_acq_int atomic_cmpset_int 470 #define atomic_cmpset_rel_int atomic_cmpset_int 471 472 #define atomic_set_acq_long atomic_set_barr_long 473 #define atomic_set_rel_long atomic_set_barr_long 474 #define atomic_clear_acq_long atomic_clear_barr_long 475 #define atomic_clear_rel_long atomic_clear_barr_long 476 #define atomic_add_acq_long atomic_add_barr_long 477 #define atomic_add_rel_long atomic_add_barr_long 478 #define atomic_subtract_acq_long atomic_subtract_barr_long 479 #define atomic_subtract_rel_long atomic_subtract_barr_long 480 #define atomic_cmpset_acq_long atomic_cmpset_long 481 #define atomic_cmpset_rel_long atomic_cmpset_long 482 483 #define atomic_readandclear_int(p) atomic_swap_int(p, 0) 484 #define atomic_readandclear_long(p) atomic_swap_long(p, 0) 485 486 /* Operations on 8-bit bytes. */ 487 #define atomic_set_8 atomic_set_char 488 #define atomic_set_acq_8 atomic_set_acq_char 489 #define atomic_set_rel_8 atomic_set_rel_char 490 #define atomic_clear_8 atomic_clear_char 491 #define atomic_clear_acq_8 atomic_clear_acq_char 492 #define atomic_clear_rel_8 atomic_clear_rel_char 493 #define atomic_add_8 atomic_add_char 494 #define atomic_add_acq_8 atomic_add_acq_char 495 #define atomic_add_rel_8 atomic_add_rel_char 496 #define atomic_subtract_8 atomic_subtract_char 497 #define atomic_subtract_acq_8 atomic_subtract_acq_char 498 #define atomic_subtract_rel_8 atomic_subtract_rel_char 499 #define atomic_load_acq_8 atomic_load_acq_char 500 #define atomic_store_rel_8 atomic_store_rel_char 501 502 /* Operations on 16-bit words. */ 503 #define atomic_set_16 atomic_set_short 504 #define atomic_set_acq_16 atomic_set_acq_short 505 #define atomic_set_rel_16 atomic_set_rel_short 506 #define atomic_clear_16 atomic_clear_short 507 #define atomic_clear_acq_16 atomic_clear_acq_short 508 #define atomic_clear_rel_16 atomic_clear_rel_short 509 #define atomic_add_16 atomic_add_short 510 #define atomic_add_acq_16 atomic_add_acq_short 511 #define atomic_add_rel_16 atomic_add_rel_short 512 #define atomic_subtract_16 atomic_subtract_short 513 #define atomic_subtract_acq_16 atomic_subtract_acq_short 514 #define atomic_subtract_rel_16 atomic_subtract_rel_short 515 #define atomic_load_acq_16 atomic_load_acq_short 516 #define atomic_store_rel_16 atomic_store_rel_short 517 518 /* Operations on 32-bit double words. */ 519 #define atomic_set_32 atomic_set_int 520 #define atomic_set_acq_32 atomic_set_acq_int 521 #define atomic_set_rel_32 atomic_set_rel_int 522 #define atomic_clear_32 atomic_clear_int 523 #define atomic_clear_acq_32 atomic_clear_acq_int 524 #define atomic_clear_rel_32 atomic_clear_rel_int 525 #define atomic_add_32 atomic_add_int 526 #define atomic_add_acq_32 atomic_add_acq_int 527 #define atomic_add_rel_32 atomic_add_rel_int 528 #define atomic_subtract_32 atomic_subtract_int 529 #define atomic_subtract_acq_32 atomic_subtract_acq_int 530 #define atomic_subtract_rel_32 atomic_subtract_rel_int 531 #define atomic_load_acq_32 atomic_load_acq_int 532 #define atomic_store_rel_32 atomic_store_rel_int 533 #define atomic_cmpset_32 atomic_cmpset_int 534 #define atomic_cmpset_acq_32 atomic_cmpset_acq_int 535 #define atomic_cmpset_rel_32 atomic_cmpset_rel_int 536 #define atomic_swap_32 atomic_swap_int 537 #define atomic_readandclear_32 atomic_readandclear_int 538 #define atomic_fetchadd_32 atomic_fetchadd_int 539 #define atomic_testandset_32 atomic_testandset_int 540 541 /* Operations on 64-bit quad words. */ 542 #define atomic_set_64 atomic_set_long 543 #define atomic_set_acq_64 atomic_set_acq_long 544 #define atomic_set_rel_64 atomic_set_rel_long 545 #define atomic_clear_64 atomic_clear_long 546 #define atomic_clear_acq_64 atomic_clear_acq_long 547 #define atomic_clear_rel_64 atomic_clear_rel_long 548 #define atomic_add_64 atomic_add_long 549 #define atomic_add_acq_64 atomic_add_acq_long 550 #define atomic_add_rel_64 atomic_add_rel_long 551 #define atomic_subtract_64 atomic_subtract_long 552 #define atomic_subtract_acq_64 atomic_subtract_acq_long 553 #define atomic_subtract_rel_64 atomic_subtract_rel_long 554 #define atomic_load_acq_64 atomic_load_acq_long 555 #define atomic_store_rel_64 atomic_store_rel_long 556 #define atomic_cmpset_64 atomic_cmpset_long 557 #define atomic_cmpset_acq_64 atomic_cmpset_acq_long 558 #define atomic_cmpset_rel_64 atomic_cmpset_rel_long 559 #define atomic_swap_64 atomic_swap_long 560 #define atomic_readandclear_64 atomic_readandclear_long 561 #define atomic_testandset_64 atomic_testandset_long 562 563 /* Operations on pointers. */ 564 #define atomic_set_ptr atomic_set_long 565 #define atomic_set_acq_ptr atomic_set_acq_long 566 #define atomic_set_rel_ptr atomic_set_rel_long 567 #define atomic_clear_ptr atomic_clear_long 568 #define atomic_clear_acq_ptr atomic_clear_acq_long 569 #define atomic_clear_rel_ptr atomic_clear_rel_long 570 #define atomic_add_ptr atomic_add_long 571 #define atomic_add_acq_ptr atomic_add_acq_long 572 #define atomic_add_rel_ptr atomic_add_rel_long 573 #define atomic_subtract_ptr atomic_subtract_long 574 #define atomic_subtract_acq_ptr atomic_subtract_acq_long 575 #define atomic_subtract_rel_ptr atomic_subtract_rel_long 576 #define atomic_load_acq_ptr atomic_load_acq_long 577 #define atomic_store_rel_ptr atomic_store_rel_long 578 #define atomic_cmpset_ptr atomic_cmpset_long 579 #define atomic_cmpset_acq_ptr atomic_cmpset_acq_long 580 #define atomic_cmpset_rel_ptr atomic_cmpset_rel_long 581 #define atomic_swap_ptr atomic_swap_long 582 #define atomic_readandclear_ptr atomic_readandclear_long 583 584 #endif /* !WANT_FUNCTIONS */ 585 586 #endif /* !_MACHINE_ATOMIC_H_ */ 587