1 /*- 2 * Copyright (c) KATO Takenori, 1997, 1998. 3 * 4 * All rights reserved. Unpublished rights reserved under the copyright 5 * laws of Japan. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer as 13 * the first lines of this file unmodified. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "opt_cpu.h" 34 35 #include <sys/param.h> 36 #include <sys/kernel.h> 37 #include <sys/pcpu.h> 38 #include <sys/systm.h> 39 #include <sys/sysctl.h> 40 41 #include <machine/cputypes.h> 42 #include <machine/md_var.h> 43 #include <machine/specialreg.h> 44 45 #include <vm/vm.h> 46 #include <vm/pmap.h> 47 48 static int hw_instruction_sse; 49 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD, 50 &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU"); 51 /* 52 * -1: automatic (default) 53 * 0: keep enable CLFLUSH 54 * 1: force disable CLFLUSH 55 */ 56 static int hw_clflush_disable = -1; 57 58 static void 59 init_amd(void) 60 { 61 uint64_t msr; 62 63 /* 64 * Work around Erratum 721 for Family 10h and 12h processors. 65 * These processors may incorrectly update the stack pointer 66 * after a long series of push and/or near-call instructions, 67 * or a long series of pop and/or near-return instructions. 68 * 69 * http://support.amd.com/us/Processor_TechDocs/41322_10h_Rev_Gd.pdf 70 * http://support.amd.com/us/Processor_TechDocs/44739_12h_Rev_Gd.pdf 71 * 72 * Hypervisors do not provide access to the errata MSR, 73 * causing #GP exception on attempt to apply the errata. The 74 * MSR write shall be done on host and persist globally 75 * anyway, so do not try to do it when under virtualization. 76 */ 77 switch (CPUID_TO_FAMILY(cpu_id)) { 78 case 0x10: 79 case 0x12: 80 if ((cpu_feature2 & CPUID2_HV) == 0) 81 wrmsr(0xc0011029, rdmsr(0xc0011029) | 1); 82 break; 83 } 84 85 /* 86 * BIOS may fail to set InitApicIdCpuIdLo to 1 as it should per BKDG. 87 * So, do it here or otherwise some tools could be confused by 88 * Initial Local APIC ID reported with CPUID Function 1 in EBX. 89 */ 90 if (CPUID_TO_FAMILY(cpu_id) == 0x10) { 91 if ((cpu_feature2 & CPUID2_HV) == 0) { 92 msr = rdmsr(MSR_NB_CFG1); 93 msr |= (uint64_t)1 << 54; 94 wrmsr(MSR_NB_CFG1, msr); 95 } 96 } 97 } 98 99 /* 100 * Initialize special VIA features 101 */ 102 static void 103 init_via(void) 104 { 105 u_int regs[4], val; 106 107 /* 108 * Check extended CPUID for PadLock features. 109 * 110 * http://www.via.com.tw/en/downloads/whitepapers/initiatives/padlock/programming_guide.pdf 111 */ 112 do_cpuid(0xc0000000, regs); 113 if (regs[0] >= 0xc0000001) { 114 do_cpuid(0xc0000001, regs); 115 val = regs[3]; 116 } else 117 return; 118 119 /* Enable RNG if present. */ 120 if ((val & VIA_CPUID_HAS_RNG) != 0) { 121 via_feature_rng = VIA_HAS_RNG; 122 wrmsr(0x110B, rdmsr(0x110B) | VIA_CPUID_DO_RNG); 123 } 124 125 /* Enable PadLock if present. */ 126 if ((val & VIA_CPUID_HAS_ACE) != 0) 127 via_feature_xcrypt |= VIA_HAS_AES; 128 if ((val & VIA_CPUID_HAS_ACE2) != 0) 129 via_feature_xcrypt |= VIA_HAS_AESCTR; 130 if ((val & VIA_CPUID_HAS_PHE) != 0) 131 via_feature_xcrypt |= VIA_HAS_SHA; 132 if ((val & VIA_CPUID_HAS_PMM) != 0) 133 via_feature_xcrypt |= VIA_HAS_MM; 134 if (via_feature_xcrypt != 0) 135 wrmsr(0x1107, rdmsr(0x1107) | (1 << 28)); 136 } 137 138 /* 139 * Initialize CPU control registers 140 */ 141 void 142 initializecpu(void) 143 { 144 uint64_t msr; 145 uint32_t cr4; 146 147 cr4 = rcr4(); 148 if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) { 149 cr4 |= CR4_FXSR | CR4_XMM; 150 cpu_fxsr = hw_instruction_sse = 1; 151 } 152 if (cpu_stdext_feature & CPUID_STDEXT_FSGSBASE) 153 cr4 |= CR4_FSGSBASE; 154 155 /* 156 * Postpone enabling the SMEP on the boot CPU until the page 157 * tables are switched from the boot loader identity mapping 158 * to the kernel tables. The boot loader enables the U bit in 159 * its tables. 160 */ 161 if (!IS_BSP() && (cpu_stdext_feature & CPUID_STDEXT_SMEP)) 162 cr4 |= CR4_SMEP; 163 load_cr4(cr4); 164 if ((amd_feature & AMDID_NX) != 0) { 165 msr = rdmsr(MSR_EFER) | EFER_NXE; 166 wrmsr(MSR_EFER, msr); 167 pg_nx = PG_NX; 168 } 169 switch (cpu_vendor_id) { 170 case CPU_VENDOR_AMD: 171 init_amd(); 172 break; 173 case CPU_VENDOR_CENTAUR: 174 init_via(); 175 break; 176 } 177 } 178 179 void 180 initializecpucache(void) 181 { 182 183 /* 184 * CPUID with %eax = 1, %ebx returns 185 * Bits 15-8: CLFLUSH line size 186 * (Value * 8 = cache line size in bytes) 187 */ 188 if ((cpu_feature & CPUID_CLFSH) != 0) 189 cpu_clflush_line_size = ((cpu_procinfo >> 8) & 0xff) * 8; 190 /* 191 * XXXKIB: (temporary) hack to work around traps generated 192 * when CLFLUSHing APIC register window under virtualization 193 * environments. These environments tend to disable the 194 * CPUID_SS feature even though the native CPU supports it. 195 */ 196 TUNABLE_INT_FETCH("hw.clflush_disable", &hw_clflush_disable); 197 if (vm_guest != VM_GUEST_NO && hw_clflush_disable == -1) { 198 cpu_feature &= ~CPUID_CLFSH; 199 cpu_stdext_feature &= ~CPUID_STDEXT_CLFLUSHOPT; 200 } 201 202 /* 203 * The kernel's use of CLFLUSH{,OPT} can be disabled manually 204 * by setting the hw.clflush_disable tunable. 205 */ 206 if (hw_clflush_disable == 1) { 207 cpu_feature &= ~CPUID_CLFSH; 208 cpu_stdext_feature &= ~CPUID_STDEXT_CLFLUSHOPT; 209 } 210 } 211