1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) KATO Takenori, 1997, 1998. 5 * 6 * All rights reserved. Unpublished rights reserved under the copyright 7 * laws of Japan. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer as 15 * the first lines of this file unmodified. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include "opt_cpu.h" 36 37 #include <sys/param.h> 38 #include <sys/kernel.h> 39 #include <sys/pcpu.h> 40 #include <sys/systm.h> 41 #include <sys/sysctl.h> 42 43 #include <machine/cputypes.h> 44 #include <machine/md_var.h> 45 #include <machine/specialreg.h> 46 47 #include <vm/vm.h> 48 #include <vm/pmap.h> 49 50 static int hw_instruction_sse; 51 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD, 52 &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU"); 53 static int lower_sharedpage_init; 54 int hw_lower_amd64_sharedpage; 55 SYSCTL_INT(_hw, OID_AUTO, lower_amd64_sharedpage, CTLFLAG_RDTUN, 56 &hw_lower_amd64_sharedpage, 0, 57 "Lower sharedpage to work around Ryzen issue with executing code near the top of user memory"); 58 /* 59 * -1: automatic (default) 60 * 0: keep enable CLFLUSH 61 * 1: force disable CLFLUSH 62 */ 63 static int hw_clflush_disable = -1; 64 65 static void 66 init_amd(void) 67 { 68 uint64_t msr; 69 70 /* 71 * Work around Erratum 721 for Family 10h and 12h processors. 72 * These processors may incorrectly update the stack pointer 73 * after a long series of push and/or near-call instructions, 74 * or a long series of pop and/or near-return instructions. 75 * 76 * http://support.amd.com/us/Processor_TechDocs/41322_10h_Rev_Gd.pdf 77 * http://support.amd.com/us/Processor_TechDocs/44739_12h_Rev_Gd.pdf 78 * 79 * Hypervisors do not provide access to the errata MSR, 80 * causing #GP exception on attempt to apply the errata. The 81 * MSR write shall be done on host and persist globally 82 * anyway, so do not try to do it when under virtualization. 83 */ 84 switch (CPUID_TO_FAMILY(cpu_id)) { 85 case 0x10: 86 case 0x12: 87 if ((cpu_feature2 & CPUID2_HV) == 0) 88 wrmsr(0xc0011029, rdmsr(0xc0011029) | 1); 89 break; 90 } 91 92 /* 93 * BIOS may fail to set InitApicIdCpuIdLo to 1 as it should per BKDG. 94 * So, do it here or otherwise some tools could be confused by 95 * Initial Local APIC ID reported with CPUID Function 1 in EBX. 96 */ 97 if (CPUID_TO_FAMILY(cpu_id) == 0x10) { 98 if ((cpu_feature2 & CPUID2_HV) == 0) { 99 msr = rdmsr(MSR_NB_CFG1); 100 msr |= (uint64_t)1 << 54; 101 wrmsr(MSR_NB_CFG1, msr); 102 } 103 } 104 105 /* 106 * BIOS may configure Family 10h processors to convert WC+ cache type 107 * to CD. That can hurt performance of guest VMs using nested paging. 108 * The relevant MSR bit is not documented in the BKDG, 109 * the fix is borrowed from Linux. 110 */ 111 if (CPUID_TO_FAMILY(cpu_id) == 0x10) { 112 if ((cpu_feature2 & CPUID2_HV) == 0) { 113 msr = rdmsr(0xc001102a); 114 msr &= ~((uint64_t)1 << 24); 115 wrmsr(0xc001102a, msr); 116 } 117 } 118 119 /* 120 * Work around Erratum 793: Specific Combination of Writes to Write 121 * Combined Memory Types and Locked Instructions May Cause Core Hang. 122 * See Revision Guide for AMD Family 16h Models 00h-0Fh Processors, 123 * revision 3.04 or later, publication 51810. 124 */ 125 if (CPUID_TO_FAMILY(cpu_id) == 0x16 && CPUID_TO_MODEL(cpu_id) <= 0xf) { 126 if ((cpu_feature2 & CPUID2_HV) == 0) { 127 msr = rdmsr(0xc0011020); 128 msr |= (uint64_t)1 << 15; 129 wrmsr(0xc0011020, msr); 130 } 131 } 132 133 /* 134 * Work around a problem on Ryzen that is triggered by executing 135 * code near the top of user memory, in our case the signal 136 * trampoline code in the shared page on amd64. 137 * 138 * This function is executed once for the BSP before tunables take 139 * effect so the value determined here can be overridden by the 140 * tunable. This function is then executed again for each AP and 141 * also on resume. Set a flag the first time so that value set by 142 * the tunable is not overwritten. 143 * 144 * The stepping and/or microcode versions should be checked after 145 * this issue is fixed by AMD so that we don't use this mode if not 146 * needed. 147 */ 148 if (lower_sharedpage_init == 0) { 149 lower_sharedpage_init = 1; 150 if (CPUID_TO_FAMILY(cpu_id) == 0x17) { 151 hw_lower_amd64_sharedpage = 1; 152 } 153 } 154 } 155 156 /* 157 * Initialize special VIA features 158 */ 159 static void 160 init_via(void) 161 { 162 u_int regs[4], val; 163 164 /* 165 * Check extended CPUID for PadLock features. 166 * 167 * http://www.via.com.tw/en/downloads/whitepapers/initiatives/padlock/programming_guide.pdf 168 */ 169 do_cpuid(0xc0000000, regs); 170 if (regs[0] >= 0xc0000001) { 171 do_cpuid(0xc0000001, regs); 172 val = regs[3]; 173 } else 174 return; 175 176 /* Enable RNG if present. */ 177 if ((val & VIA_CPUID_HAS_RNG) != 0) { 178 via_feature_rng = VIA_HAS_RNG; 179 wrmsr(0x110B, rdmsr(0x110B) | VIA_CPUID_DO_RNG); 180 } 181 182 /* Enable PadLock if present. */ 183 if ((val & VIA_CPUID_HAS_ACE) != 0) 184 via_feature_xcrypt |= VIA_HAS_AES; 185 if ((val & VIA_CPUID_HAS_ACE2) != 0) 186 via_feature_xcrypt |= VIA_HAS_AESCTR; 187 if ((val & VIA_CPUID_HAS_PHE) != 0) 188 via_feature_xcrypt |= VIA_HAS_SHA; 189 if ((val & VIA_CPUID_HAS_PMM) != 0) 190 via_feature_xcrypt |= VIA_HAS_MM; 191 if (via_feature_xcrypt != 0) 192 wrmsr(0x1107, rdmsr(0x1107) | (1 << 28)); 193 } 194 195 /* 196 * Initialize CPU control registers 197 */ 198 void 199 initializecpu(void) 200 { 201 uint64_t msr; 202 uint32_t cr4; 203 204 cr4 = rcr4(); 205 if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) { 206 cr4 |= CR4_FXSR | CR4_XMM; 207 cpu_fxsr = hw_instruction_sse = 1; 208 } 209 if (cpu_stdext_feature & CPUID_STDEXT_FSGSBASE) 210 cr4 |= CR4_FSGSBASE; 211 212 /* 213 * Postpone enabling the SMEP on the boot CPU until the page 214 * tables are switched from the boot loader identity mapping 215 * to the kernel tables. The boot loader enables the U bit in 216 * its tables. 217 */ 218 if (!IS_BSP() && (cpu_stdext_feature & CPUID_STDEXT_SMEP)) 219 cr4 |= CR4_SMEP; 220 load_cr4(cr4); 221 if (IS_BSP() && (amd_feature & AMDID_NX) != 0) { 222 msr = rdmsr(MSR_EFER) | EFER_NXE; 223 wrmsr(MSR_EFER, msr); 224 pg_nx = PG_NX; 225 } 226 hw_ibrs_recalculate(); 227 switch (cpu_vendor_id) { 228 case CPU_VENDOR_AMD: 229 init_amd(); 230 break; 231 case CPU_VENDOR_CENTAUR: 232 init_via(); 233 break; 234 } 235 } 236 237 void 238 initializecpucache(void) 239 { 240 241 /* 242 * CPUID with %eax = 1, %ebx returns 243 * Bits 15-8: CLFLUSH line size 244 * (Value * 8 = cache line size in bytes) 245 */ 246 if ((cpu_feature & CPUID_CLFSH) != 0) 247 cpu_clflush_line_size = ((cpu_procinfo >> 8) & 0xff) * 8; 248 /* 249 * XXXKIB: (temporary) hack to work around traps generated 250 * when CLFLUSHing APIC register window under virtualization 251 * environments. These environments tend to disable the 252 * CPUID_SS feature even though the native CPU supports it. 253 */ 254 TUNABLE_INT_FETCH("hw.clflush_disable", &hw_clflush_disable); 255 if (vm_guest != VM_GUEST_NO && hw_clflush_disable == -1) { 256 cpu_feature &= ~CPUID_CLFSH; 257 cpu_stdext_feature &= ~CPUID_STDEXT_CLFLUSHOPT; 258 } 259 260 /* 261 * The kernel's use of CLFLUSH{,OPT} can be disabled manually 262 * by setting the hw.clflush_disable tunable. 263 */ 264 if (hw_clflush_disable == 1) { 265 cpu_feature &= ~CPUID_CLFSH; 266 cpu_stdext_feature &= ~CPUID_STDEXT_CLFLUSHOPT; 267 } 268 } 269