1 /*- 2 * Copyright (c) KATO Takenori, 1997, 1998. 3 * 4 * All rights reserved. Unpublished rights reserved under the copyright 5 * laws of Japan. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer as 13 * the first lines of this file unmodified. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "opt_cpu.h" 34 35 #include <sys/param.h> 36 #include <sys/kernel.h> 37 #include <sys/systm.h> 38 #include <sys/sysctl.h> 39 40 #include <machine/cputypes.h> 41 #include <machine/md_var.h> 42 #include <machine/specialreg.h> 43 44 #include <vm/vm.h> 45 #include <vm/pmap.h> 46 47 static int hw_instruction_sse; 48 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD, 49 &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU"); 50 51 int cpu; /* Are we 386, 386sx, 486, etc? */ 52 u_int cpu_feature; /* Feature flags */ 53 u_int cpu_feature2; /* Feature flags */ 54 u_int amd_feature; /* AMD feature flags */ 55 u_int amd_feature2; /* AMD feature flags */ 56 u_int amd_pminfo; /* AMD advanced power management info */ 57 u_int via_feature_rng; /* VIA RNG features */ 58 u_int via_feature_xcrypt; /* VIA ACE features */ 59 u_int cpu_high; /* Highest arg to CPUID */ 60 u_int cpu_exthigh; /* Highest arg to extended CPUID */ 61 u_int cpu_id; /* Stepping ID */ 62 u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */ 63 u_int cpu_procinfo2; /* Multicore info */ 64 char cpu_vendor[20]; /* CPU Origin code */ 65 u_int cpu_vendor_id; /* CPU vendor ID */ 66 u_int cpu_fxsr; /* SSE enabled */ 67 u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */ 68 69 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD, 70 &via_feature_rng, 0, "VIA C3/C7 RNG feature available in CPU"); 71 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD, 72 &via_feature_xcrypt, 0, "VIA C3/C7 xcrypt feature available in CPU"); 73 74 /* 75 * Initialize special VIA C3/C7 features 76 */ 77 static void 78 init_via(void) 79 { 80 u_int regs[4], val; 81 u_int64_t msreg; 82 83 do_cpuid(0xc0000000, regs); 84 val = regs[0]; 85 if (val >= 0xc0000001) { 86 do_cpuid(0xc0000001, regs); 87 val = regs[3]; 88 } else 89 val = 0; 90 91 /* Enable RNG if present and disabled */ 92 if (val & VIA_CPUID_HAS_RNG) { 93 if (!(val & VIA_CPUID_DO_RNG)) { 94 msreg = rdmsr(0x110B); 95 msreg |= 0x40; 96 wrmsr(0x110B, msreg); 97 } 98 via_feature_rng = VIA_HAS_RNG; 99 } 100 /* Enable AES engine if present and disabled */ 101 if (val & VIA_CPUID_HAS_ACE) { 102 if (!(val & VIA_CPUID_DO_ACE)) { 103 msreg = rdmsr(0x1107); 104 msreg |= (0x01 << 28); 105 wrmsr(0x1107, msreg); 106 } 107 via_feature_xcrypt |= VIA_HAS_AES; 108 } 109 /* Enable ACE2 engine if present and disabled */ 110 if (val & VIA_CPUID_HAS_ACE2) { 111 if (!(val & VIA_CPUID_DO_ACE2)) { 112 msreg = rdmsr(0x1107); 113 msreg |= (0x01 << 28); 114 wrmsr(0x1107, msreg); 115 } 116 via_feature_xcrypt |= VIA_HAS_AESCTR; 117 } 118 /* Enable SHA engine if present and disabled */ 119 if (val & VIA_CPUID_HAS_PHE) { 120 if (!(val & VIA_CPUID_DO_PHE)) { 121 msreg = rdmsr(0x1107); 122 msreg |= (0x01 << 28/**/); 123 wrmsr(0x1107, msreg); 124 } 125 via_feature_xcrypt |= VIA_HAS_SHA; 126 } 127 /* Enable MM engine if present and disabled */ 128 if (val & VIA_CPUID_HAS_PMM) { 129 if (!(val & VIA_CPUID_DO_PMM)) { 130 msreg = rdmsr(0x1107); 131 msreg |= (0x01 << 28/**/); 132 wrmsr(0x1107, msreg); 133 } 134 via_feature_xcrypt |= VIA_HAS_MM; 135 } 136 } 137 138 /* 139 * Initialize CPU control registers 140 */ 141 void 142 initializecpu(void) 143 { 144 uint64_t msr; 145 146 if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) { 147 load_cr4(rcr4() | CR4_FXSR | CR4_XMM); 148 cpu_fxsr = hw_instruction_sse = 1; 149 } 150 if ((amd_feature & AMDID_NX) != 0) { 151 msr = rdmsr(MSR_EFER) | EFER_NXE; 152 wrmsr(MSR_EFER, msr); 153 pg_nx = PG_NX; 154 } 155 if (cpu_vendor_id == CPU_VENDOR_CENTAUR && 156 AMD64_CPU_FAMILY(cpu_id) == 0x6 && 157 AMD64_CPU_MODEL(cpu_id) >= 0xf) 158 init_via(); 159 } 160