1 /* 2 * Copyright (c) KATO Takenori, 1997, 1998. 3 * 4 * All rights reserved. Unpublished rights reserved under the copyright 5 * laws of Japan. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer as 13 * the first lines of this file unmodified. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * $Id: initcpu.c,v 1.13 1998/05/16 14:38:10 kato Exp $ 30 */ 31 32 #include "opt_cpu.h" 33 #include "opt_failsafe.h" 34 35 #include <sys/param.h> 36 #include <sys/kernel.h> 37 #include <sys/systm.h> 38 39 #include <machine/cputypes.h> 40 #include <machine/md_var.h> 41 #include <machine/specialreg.h> 42 43 void initializecpu(void); 44 #if defined(I586_CPU) && defined(CPU_WT_ALLOC) 45 void enable_K5_wt_alloc(void); 46 void enable_K6_wt_alloc(void); 47 #endif 48 49 #ifdef I486_CPU 50 static void init_5x86(void); 51 static void init_bluelightning(void); 52 static void init_486dlc(void); 53 static void init_cy486dx(void); 54 #ifdef CPU_I486_ON_386 55 static void init_i486_on_386(void); 56 #endif 57 static void init_6x86(void); 58 #endif /* I486_CPU */ 59 60 #ifdef I686_CPU 61 static void init_6x86MX(void); 62 static void init_ppro(void); 63 #endif 64 65 #ifdef I486_CPU 66 /* 67 * IBM Blue Lightning 68 */ 69 static void 70 init_bluelightning(void) 71 { 72 u_long eflags; 73 74 #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE) 75 need_post_dma_flush = 1; 76 #endif 77 78 eflags = read_eflags(); 79 disable_intr(); 80 81 load_cr0(rcr0() | CR0_CD | CR0_NW); 82 invd(); 83 84 #ifdef CPU_BLUELIGHTNING_FPU_OP_CACHE 85 wrmsr(0x1000, 0x9c92LL); /* FP operand can be cacheable on Cyrix FPU */ 86 #else 87 wrmsr(0x1000, 0x1c92LL); /* Intel FPU */ 88 #endif 89 /* Enables 13MB and 0-640KB cache. */ 90 wrmsr(0x1001, (0xd0LL << 32) | 0x3ff); 91 #ifdef CPU_BLUELIGHTNING_3X 92 wrmsr(0x1002, 0x04000000LL); /* Enables triple-clock mode. */ 93 #else 94 wrmsr(0x1002, 0x03000000LL); /* Enables double-clock mode. */ 95 #endif 96 97 /* Enable caching in CR0. */ 98 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ 99 invd(); 100 write_eflags(eflags); 101 } 102 103 /* 104 * Cyrix 486SLC/DLC/SR/DR series 105 */ 106 static void 107 init_486dlc(void) 108 { 109 u_long eflags; 110 u_char ccr0; 111 112 eflags = read_eflags(); 113 disable_intr(); 114 invd(); 115 116 ccr0 = read_cyrix_reg(CCR0); 117 #ifndef CYRIX_CACHE_WORKS 118 ccr0 |= CCR0_NC1 | CCR0_BARB; 119 write_cyrix_reg(CCR0, ccr0); 120 invd(); 121 #else 122 ccr0 &= ~CCR0_NC0; 123 #ifndef CYRIX_CACHE_REALLY_WORKS 124 ccr0 |= CCR0_NC1 | CCR0_BARB; 125 #else 126 ccr0 |= CCR0_NC1; 127 #endif 128 #ifdef CPU_DIRECT_MAPPED_CACHE 129 ccr0 |= CCR0_CO; /* Direct mapped mode. */ 130 #endif 131 write_cyrix_reg(CCR0, ccr0); 132 133 /* Clear non-cacheable region. */ 134 write_cyrix_reg(NCR1+2, NCR_SIZE_0K); 135 write_cyrix_reg(NCR2+2, NCR_SIZE_0K); 136 write_cyrix_reg(NCR3+2, NCR_SIZE_0K); 137 write_cyrix_reg(NCR4+2, NCR_SIZE_0K); 138 139 write_cyrix_reg(0, 0); /* dummy write */ 140 141 /* Enable caching in CR0. */ 142 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ 143 invd(); 144 #endif /* !CYRIX_CACHE_WORKS */ 145 write_eflags(eflags); 146 } 147 148 149 /* 150 * Cyrix 486S/DX series 151 */ 152 static void 153 init_cy486dx(void) 154 { 155 u_long eflags; 156 u_char ccr2; 157 158 eflags = read_eflags(); 159 disable_intr(); 160 invd(); 161 162 ccr2 = read_cyrix_reg(CCR2); 163 #ifdef CPU_SUSP_HLT 164 ccr2 |= CCR2_SUSP_HLT; 165 #endif 166 write_cyrix_reg(CCR2, ccr2); 167 write_eflags(eflags); 168 } 169 170 171 /* 172 * Cyrix 5x86 173 */ 174 static void 175 init_5x86(void) 176 { 177 u_long eflags; 178 u_char ccr2, ccr3, ccr4, pcr0; 179 180 eflags = read_eflags(); 181 disable_intr(); 182 183 load_cr0(rcr0() | CR0_CD | CR0_NW); 184 wbinvd(); 185 186 (void)read_cyrix_reg(CCR3); /* dummy */ 187 188 /* Initialize CCR2. */ 189 ccr2 = read_cyrix_reg(CCR2); 190 ccr2 |= CCR2_WB; 191 #ifdef CPU_SUSP_HLT 192 ccr2 |= CCR2_SUSP_HLT; 193 #else 194 ccr2 &= ~CCR2_SUSP_HLT; 195 #endif 196 ccr2 |= CCR2_WT1; 197 write_cyrix_reg(CCR2, ccr2); 198 199 /* Initialize CCR4. */ 200 ccr3 = read_cyrix_reg(CCR3); 201 write_cyrix_reg(CCR3, CCR3_MAPEN0); 202 203 ccr4 = read_cyrix_reg(CCR4); 204 ccr4 |= CCR4_DTE; 205 ccr4 |= CCR4_MEM; 206 #ifdef CPU_FASTER_5X86_FPU 207 ccr4 |= CCR4_FASTFPE; 208 #else 209 ccr4 &= ~CCR4_FASTFPE; 210 #endif 211 ccr4 &= ~CCR4_IOMASK; 212 /******************************************************************** 213 * WARNING: The "BIOS Writers Guide" mentions that I/O recovery time 214 * should be 0 for errata fix. 215 ********************************************************************/ 216 #ifdef CPU_IORT 217 ccr4 |= CPU_IORT & CCR4_IOMASK; 218 #endif 219 write_cyrix_reg(CCR4, ccr4); 220 221 /* Initialize PCR0. */ 222 /**************************************************************** 223 * WARNING: RSTK_EN and LOOP_EN could make your system unstable. 224 * BTB_EN might make your system unstable. 225 ****************************************************************/ 226 pcr0 = read_cyrix_reg(PCR0); 227 #ifdef CPU_RSTK_EN 228 pcr0 |= PCR0_RSTK; 229 #else 230 pcr0 &= ~PCR0_RSTK; 231 #endif 232 #ifdef CPU_BTB_EN 233 pcr0 |= PCR0_BTB; 234 #else 235 pcr0 &= ~PCR0_BTB; 236 #endif 237 #ifdef CPU_LOOP_EN 238 pcr0 |= PCR0_LOOP; 239 #else 240 pcr0 &= ~PCR0_LOOP; 241 #endif 242 243 /**************************************************************** 244 * WARNING: if you use a memory mapped I/O device, don't use 245 * DISABLE_5X86_LSSER option, which may reorder memory mapped 246 * I/O access. 247 * IF YOUR MOTHERBOARD HAS PCI BUS, DON'T DISABLE LSSER. 248 ****************************************************************/ 249 #ifdef CPU_DISABLE_5X86_LSSER 250 pcr0 &= ~PCR0_LSSER; 251 #else 252 pcr0 |= PCR0_LSSER; 253 #endif 254 write_cyrix_reg(PCR0, pcr0); 255 256 /* Restore CCR3. */ 257 write_cyrix_reg(CCR3, ccr3); 258 259 (void)read_cyrix_reg(0x80); /* dummy */ 260 261 /* Unlock NW bit in CR0. */ 262 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW); 263 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0, NW = 1 */ 264 /* Lock NW bit in CR0. */ 265 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW); 266 267 write_eflags(eflags); 268 } 269 270 #ifdef CPU_I486_ON_386 271 /* 272 * There are i486 based upgrade products for i386 machines. 273 * In this case, BIOS doesn't enables CPU cache. 274 */ 275 void 276 init_i486_on_386(void) 277 { 278 u_long eflags; 279 280 #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE) 281 need_post_dma_flush = 1; 282 #endif 283 284 eflags = read_eflags(); 285 disable_intr(); 286 287 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0, NW = 0 */ 288 289 write_eflags(eflags); 290 } 291 #endif 292 293 /* 294 * Cyrix 6x86 295 * 296 * XXX - What should I do here? Please let me know. 297 */ 298 static void 299 init_6x86(void) 300 { 301 u_long eflags; 302 u_char ccr3, ccr4; 303 304 eflags = read_eflags(); 305 disable_intr(); 306 307 load_cr0(rcr0() | CR0_CD | CR0_NW); 308 wbinvd(); 309 310 /* Initialize CCR0. */ 311 write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1); 312 313 /* Initialize CCR1. */ 314 #ifdef CPU_CYRIX_NO_LOCK 315 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK); 316 #else 317 #ifdef FAILSAFE 318 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK); 319 #endif 320 #endif 321 322 /* Initialize CCR2. */ 323 #ifdef CPU_SUSP_HLT 324 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT); 325 #else 326 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT); 327 #endif 328 329 ccr3 = read_cyrix_reg(CCR3); 330 write_cyrix_reg(CCR3, CCR3_MAPEN0); 331 332 /* Initialize CCR4. */ 333 ccr4 = read_cyrix_reg(CCR4); 334 ccr4 |= CCR4_DTE; 335 ccr4 &= ~CCR4_IOMASK; 336 #ifdef CPU_IORT 337 write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK)); 338 #else 339 write_cyrix_reg(CCR4, ccr4 | 7); 340 #endif 341 342 /* Initialize CCR5. */ 343 #ifdef CPU_WT_ALLOC 344 write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC); 345 #endif 346 347 /* Restore CCR3. */ 348 write_cyrix_reg(CCR3, ccr3); 349 350 /* Unlock NW bit in CR0. */ 351 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW); 352 353 /* 354 * Earlier revision of the 6x86 CPU could crash the system if 355 * L1 cache is in write-back mode. 356 */ 357 if ((cyrix_did & 0xff00) > 0x1600) 358 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ 359 else { 360 /* Revision 2.6 and lower. */ 361 #ifdef CYRIX_CACHE_REALLY_WORKS 362 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ 363 #else 364 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0 and NW = 1 */ 365 #endif 366 } 367 368 /* Lock NW bit in CR0. */ 369 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW); 370 371 write_eflags(eflags); 372 } 373 #endif /* I486_CPU */ 374 375 #ifdef I686_CPU 376 /* 377 * Cyrix 6x86MX (code-named M2) 378 * 379 * XXX - What should I do here? Please let me know. 380 */ 381 static void 382 init_6x86MX(void) 383 { 384 u_long eflags; 385 u_char ccr3, ccr4; 386 387 eflags = read_eflags(); 388 disable_intr(); 389 390 load_cr0(rcr0() | CR0_CD | CR0_NW); 391 wbinvd(); 392 393 /* Initialize CCR0. */ 394 write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1); 395 396 /* Initialize CCR1. */ 397 #ifdef CPU_CYRIX_NO_LOCK 398 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK); 399 #else 400 #ifdef FAILSAFE 401 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK); 402 #endif 403 #endif 404 405 /* Initialize CCR2. */ 406 #ifdef CPU_SUSP_HLT 407 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT); 408 #else 409 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT); 410 #endif 411 412 ccr3 = read_cyrix_reg(CCR3); 413 write_cyrix_reg(CCR3, CCR3_MAPEN0); 414 415 /* Initialize CCR4. */ 416 ccr4 = read_cyrix_reg(CCR4); 417 ccr4 &= ~CCR4_IOMASK; 418 #ifdef CPU_IORT 419 write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK)); 420 #else 421 write_cyrix_reg(CCR4, ccr4 | 7); 422 #endif 423 424 /* Initialize CCR5. */ 425 #ifdef CPU_WT_ALLOC 426 write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC); 427 #endif 428 429 /* Restore CCR3. */ 430 write_cyrix_reg(CCR3, ccr3); 431 432 /* Unlock NW bit in CR0. */ 433 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW); 434 435 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ 436 437 /* Lock NW bit in CR0. */ 438 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW); 439 440 write_eflags(eflags); 441 } 442 443 static void 444 init_ppro(void) 445 { 446 #ifndef SMP 447 u_int64_t apicbase; 448 449 /* 450 * Local APIC should be diabled in UP kernel. 451 */ 452 apicbase = rdmsr(0x1b); 453 apicbase &= ~0x800LL; 454 wrmsr(0x1b, apicbase); 455 #endif 456 } 457 #endif /* I686_CPU */ 458 459 void 460 initializecpu(void) 461 { 462 463 switch (cpu) { 464 #ifdef I486_CPU 465 case CPU_BLUE: 466 init_bluelightning(); 467 break; 468 case CPU_486DLC: 469 init_486dlc(); 470 break; 471 case CPU_CY486DX: 472 init_cy486dx(); 473 break; 474 case CPU_M1SC: 475 init_5x86(); 476 break; 477 #ifdef CPU_I486_ON_386 478 case CPU_486: 479 init_i486_on_386(); 480 break; 481 #endif 482 case CPU_M1: 483 init_6x86(); 484 break; 485 #endif /* I486_CPU */ 486 #ifdef I686_CPU 487 case CPU_M2: 488 init_6x86MX(); 489 break; 490 case CPU_686: 491 if (strcmp(cpu_vendor, "GenuineIntel") == 0 && 492 (cpu_id & 0xff0) == 0x610) 493 init_ppro(); 494 break; 495 #endif 496 default: 497 break; 498 } 499 500 #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE) 501 /* 502 * OS should flush L1 cahce by itself because no PC-98 supports 503 * non-Intel CPUs. Use wbinvd instruction before DMA transfer 504 * when need_pre_dma_flush = 1, use invd instruction after DMA 505 * transfer when need_post_dma_flush = 1. If your CPU upgrade 506 * product support hardware cache control, you can add 507 * UPGRADE_CPU_HW_CACHE option in your kernel configuration file. 508 * This option elminate unneeded cache flush instruction. 509 */ 510 if (strcmp(cpu_vendor, "CyrixInstead") == 0) { 511 switch (cpu) { 512 #ifdef I486_CPU 513 case CPU_486DLC: 514 need_post_dma_flush = 1; 515 break; 516 case CPU_M1SC: 517 need_pre_dma_flush = 1; 518 break; 519 #endif 520 default: 521 break; 522 } 523 } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) { 524 switch (cpu_id & 0xFF0) { 525 case 0x470: /* Enhanced Am486DX2 WB */ 526 case 0x490: /* Enhanced Am486DX4 WB */ 527 case 0x4F0: /* Am5x86 WB */ 528 need_pre_dma_flush = 1; 529 break; 530 } 531 } else if (strcmp(cpu_vendor, "IBM") == 0) { 532 need_post_dma_flush = 1; 533 } else { 534 #ifdef CPU_I486_ON_386 535 need_pre_dma_flush = 1; 536 #endif 537 } 538 #endif /* PC98 && !UPGRADE_CPU_HW_CACHE */ 539 } 540 541 #if defined(I586_CPU) && defined(CPU_WT_ALLOC) 542 /* 543 * Enable write allocate feature of AMD processors. 544 * Following two functions require the Maxmem variable being set. 545 */ 546 void 547 enable_K5_wt_alloc(void) 548 { 549 u_int64_t msr; 550 551 /* 552 * Write allocate is supported only on models 1, 2, and 3, with 553 * a stepping of 4 or greater. 554 */ 555 if (((cpu_id & 0xf0) > 0) && ((cpu_id & 0x0f) > 3)) { 556 disable_intr(); 557 msr = rdmsr(0x83); /* HWCR */ 558 wrmsr(0x83, msr & !(0x10)); 559 560 /* 561 * We have to tell the chip where the top of memory is, 562 * since video cards could have frame bufferes there, 563 * memory-mapped I/O could be there, etc. 564 */ 565 if(Maxmem > 0) 566 msr = Maxmem / 16; 567 else 568 msr = 0; 569 msr |= AMD_WT_ALLOC_TME | AMD_WT_ALLOC_FRE; 570 #ifdef PC98 571 if (!(inb(0x43b) & 4)) { 572 wrmsr(0x86, 0x0ff00f0); 573 msr |= AMD_WT_ALLOC_PRE; 574 } 575 #else 576 /* 577 * There is no way to know wheter 15-16M hole exists or not. 578 * Therefore, we disable write allocate for this range. 579 */ 580 wrmsr(0x86, 0x0ff00f0); 581 msr |= AMD_WT_ALLOC_PRE; 582 #endif 583 wrmsr(0x85, msr); 584 585 msr=rdmsr(0x83); 586 wrmsr(0x83, msr|0x10); /* enable write allocate */ 587 588 enable_intr(); 589 } 590 } 591 592 void 593 enable_K6_wt_alloc(void) 594 { 595 quad_t size; 596 u_int64_t whcr; 597 u_long eflags; 598 599 eflags = read_eflags(); 600 disable_intr(); 601 wbinvd(); 602 603 #ifdef CPU_DISABLE_CACHE 604 /* 605 * Certain K6-2 box becomes unstable when write allocation is 606 * enabled. 607 */ 608 /* 609 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12), 610 * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported. 611 * All other bits in TR12 have no effect on the processer's operation. 612 * The I/O Trap Restart function (bit 9 of TR12) is always enabled 613 * on the AMD-K6. 614 */ 615 wrmsr(0x0000000e, (u_int64_t)0x0008); 616 #endif 617 /* Don't assume that memory size is aligned with 4M. */ 618 if (Maxmem > 0) 619 size = Maxmem / 256; 620 else 621 size = 0; 622 size = (size + 3) / 4; 623 624 /* Limit is 508M bytes. */ 625 if (size > 127) 626 size = 127; 627 whcr = rdmsr(0xc0000082); 628 whcr &= ~0x00feLL; 629 whcr |= (size << 1); 630 631 #ifdef PC98 632 if (whcr & 0x00feLL) { 633 /* 634 * If bit 2 of port 0x43b is 0, disable wrte allocate for the 635 * 15-16M range. 636 */ 637 if (!(inb(0x43b) & 4)) 638 whcr &= ~0x0001LL; 639 else 640 whcr |= 0x0001LL; 641 } 642 #else 643 /* 644 * There is no way to know wheter 15-16M hole exists or not. 645 * Therefore, we disable write allocate for this range. 646 */ 647 whcr &= 0x00feLL; 648 #endif 649 wrmsr(0x0c0000082, whcr); 650 651 write_eflags(eflags); 652 enable_intr(); 653 } 654 #endif /* I585_CPU && CPU_WT_ALLOC */ 655 656 #include "opt_ddb.h" 657 #ifdef DDB 658 #include <ddb/ddb.h> 659 660 DB_SHOW_COMMAND(cyrixreg, cyrixreg) 661 { 662 u_long eflags; 663 u_int cr0; 664 u_char ccr0, ccr1, ccr2, ccr3, ccr4, ccr5, pcr0; 665 666 cr0 = rcr0(); 667 if (strcmp(cpu_vendor,"CyrixInstead") == 0) { 668 eflags = read_eflags(); 669 disable_intr(); 670 671 672 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) { 673 ccr0 = read_cyrix_reg(CCR0); 674 } 675 ccr1 = read_cyrix_reg(CCR1); 676 ccr2 = read_cyrix_reg(CCR2); 677 ccr3 = read_cyrix_reg(CCR3); 678 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) { 679 write_cyrix_reg(CCR3, CCR3_MAPEN0); 680 ccr4 = read_cyrix_reg(CCR4); 681 if ((cpu == CPU_M1) || (cpu == CPU_M2)) 682 ccr5 = read_cyrix_reg(CCR5); 683 else 684 pcr0 = read_cyrix_reg(PCR0); 685 write_cyrix_reg(CCR3, ccr3); /* Restore CCR3. */ 686 } 687 write_eflags(eflags); 688 689 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) 690 printf("CCR0=%x, ", (u_int)ccr0); 691 692 printf("CCR1=%x, CCR2=%x, CCR3=%x", 693 (u_int)ccr1, (u_int)ccr2, (u_int)ccr3); 694 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) { 695 printf(", CCR4=%x, ", (u_int)ccr4); 696 if (cpu == CPU_M1SC) 697 printf("PCR0=%x\n", pcr0); 698 else 699 printf("CCR5=%x\n", ccr5); 700 } 701 } 702 printf("CR0=%x\n", cr0); 703 } 704 #endif /* DDB */ 705