xref: /freebsd/sys/amd64/amd64/initcpu.c (revision beb2406556f190519f91f573d984503bda34673b)
1cda07865SPeter Wemm /*-
2c49761ddSPedro F. Giffuni  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3c49761ddSPedro F. Giffuni  *
44536af6aSKATO Takenori  * Copyright (c) KATO Takenori, 1997, 1998.
5a8e282d6SKATO Takenori  *
6a8e282d6SKATO Takenori  * All rights reserved.  Unpublished rights reserved under the copyright
7a8e282d6SKATO Takenori  * laws of Japan.
8a8e282d6SKATO Takenori  *
9a8e282d6SKATO Takenori  * Redistribution and use in source and binary forms, with or without
10a8e282d6SKATO Takenori  * modification, are permitted provided that the following conditions
11a8e282d6SKATO Takenori  * are met:
12a8e282d6SKATO Takenori  *
13a8e282d6SKATO Takenori  * 1. Redistributions of source code must retain the above copyright
14a8e282d6SKATO Takenori  *    notice, this list of conditions and the following disclaimer as
15a8e282d6SKATO Takenori  *    the first lines of this file unmodified.
16a8e282d6SKATO Takenori  * 2. Redistributions in binary form must reproduce the above copyright
17a8e282d6SKATO Takenori  *    notice, this list of conditions and the following disclaimer in the
18a8e282d6SKATO Takenori  *    documentation and/or other materials provided with the distribution.
19a8e282d6SKATO Takenori  *
20a8e282d6SKATO Takenori  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21a8e282d6SKATO Takenori  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22a8e282d6SKATO Takenori  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23a8e282d6SKATO Takenori  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24a8e282d6SKATO Takenori  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25a8e282d6SKATO Takenori  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26a8e282d6SKATO Takenori  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27a8e282d6SKATO Takenori  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28a8e282d6SKATO Takenori  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29a8e282d6SKATO Takenori  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30a8e282d6SKATO Takenori  */
31a8e282d6SKATO Takenori 
3256ae44c5SDavid E. O'Brien #include <sys/cdefs.h>
3356ae44c5SDavid E. O'Brien __FBSDID("$FreeBSD$");
3456ae44c5SDavid E. O'Brien 
35a8e282d6SKATO Takenori #include "opt_cpu.h"
36a8e282d6SKATO Takenori 
37a8e282d6SKATO Takenori #include <sys/param.h>
38a8e282d6SKATO Takenori #include <sys/kernel.h>
39cd9e9d1bSKonstantin Belousov #include <sys/pcpu.h>
40a8e282d6SKATO Takenori #include <sys/systm.h>
419d146ac5SPeter Wemm #include <sys/sysctl.h>
42a8e282d6SKATO Takenori 
43a8e282d6SKATO Takenori #include <machine/cputypes.h>
44a8e282d6SKATO Takenori #include <machine/md_var.h>
45a8e282d6SKATO Takenori #include <machine/specialreg.h>
46a8e282d6SKATO Takenori 
47430e272cSPeter Wemm #include <vm/vm.h>
48430e272cSPeter Wemm #include <vm/pmap.h>
4920916c1fSKATO Takenori 
5010deca7eSJohn Baldwin static int	hw_instruction_sse;
519d146ac5SPeter Wemm SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
5210deca7eSJohn Baldwin     &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU");
53cd155b56SDon Lewis static int	lower_sharedpage_init;
54cd155b56SDon Lewis int		hw_lower_amd64_sharedpage;
55cd155b56SDon Lewis SYSCTL_INT(_hw, OID_AUTO, lower_amd64_sharedpage, CTLFLAG_RDTUN,
56cd155b56SDon Lewis     &hw_lower_amd64_sharedpage, 0,
57cd155b56SDon Lewis    "Lower sharedpage to work around Ryzen issue with executing code near the top of user memory");
586f5c96c4SJun Kuriyama /*
596f5c96c4SJun Kuriyama  * -1: automatic (default)
606f5c96c4SJun Kuriyama  *  0: keep enable CLFLUSH
616f5c96c4SJun Kuriyama  *  1: force disable CLFLUSH
626f5c96c4SJun Kuriyama  */
636f5c96c4SJun Kuriyama static int	hw_clflush_disable = -1;
649d146ac5SPeter Wemm 
653ce5dbccSJung-uk Kim static void
663ce5dbccSJung-uk Kim init_amd(void)
673ce5dbccSJung-uk Kim {
68f9ac50acSAndriy Gapon 	uint64_t msr;
693ce5dbccSJung-uk Kim 
703ce5dbccSJung-uk Kim 	/*
713ce5dbccSJung-uk Kim 	 * Work around Erratum 721 for Family 10h and 12h processors.
723ce5dbccSJung-uk Kim 	 * These processors may incorrectly update the stack pointer
733ce5dbccSJung-uk Kim 	 * after a long series of push and/or near-call instructions,
743ce5dbccSJung-uk Kim 	 * or a long series of pop and/or near-return instructions.
753ce5dbccSJung-uk Kim 	 *
763ce5dbccSJung-uk Kim 	 * http://support.amd.com/us/Processor_TechDocs/41322_10h_Rev_Gd.pdf
773ce5dbccSJung-uk Kim 	 * http://support.amd.com/us/Processor_TechDocs/44739_12h_Rev_Gd.pdf
7865211d02SKonstantin Belousov 	 *
7965211d02SKonstantin Belousov 	 * Hypervisors do not provide access to the errata MSR,
8065211d02SKonstantin Belousov 	 * causing #GP exception on attempt to apply the errata.  The
8165211d02SKonstantin Belousov 	 * MSR write shall be done on host and persist globally
8265211d02SKonstantin Belousov 	 * anyway, so do not try to do it when under virtualization.
833ce5dbccSJung-uk Kim 	 */
843ce5dbccSJung-uk Kim 	switch (CPUID_TO_FAMILY(cpu_id)) {
853ce5dbccSJung-uk Kim 	case 0x10:
863ce5dbccSJung-uk Kim 	case 0x12:
8765211d02SKonstantin Belousov 		if ((cpu_feature2 & CPUID2_HV) == 0)
883ce5dbccSJung-uk Kim 			wrmsr(0xc0011029, rdmsr(0xc0011029) | 1);
893ce5dbccSJung-uk Kim 		break;
903ce5dbccSJung-uk Kim 	}
91e5e44520SAndriy Gapon 
92e5e44520SAndriy Gapon 	/*
93e5e44520SAndriy Gapon 	 * BIOS may fail to set InitApicIdCpuIdLo to 1 as it should per BKDG.
94e5e44520SAndriy Gapon 	 * So, do it here or otherwise some tools could be confused by
95e5e44520SAndriy Gapon 	 * Initial Local APIC ID reported with CPUID Function 1 in EBX.
96e5e44520SAndriy Gapon 	 */
97e5e44520SAndriy Gapon 	if (CPUID_TO_FAMILY(cpu_id) == 0x10) {
98e5e44520SAndriy Gapon 		if ((cpu_feature2 & CPUID2_HV) == 0) {
99e5e44520SAndriy Gapon 			msr = rdmsr(MSR_NB_CFG1);
100e5e44520SAndriy Gapon 			msr |= (uint64_t)1 << 54;
101e5e44520SAndriy Gapon 			wrmsr(MSR_NB_CFG1, msr);
102e5e44520SAndriy Gapon 		}
103e5e44520SAndriy Gapon 	}
104a2d87b79SAndriy Gapon 
105a2d87b79SAndriy Gapon 	/*
106a2d87b79SAndriy Gapon 	 * BIOS may configure Family 10h processors to convert WC+ cache type
107a2d87b79SAndriy Gapon 	 * to CD.  That can hurt performance of guest VMs using nested paging.
108a2d87b79SAndriy Gapon 	 * The relevant MSR bit is not documented in the BKDG,
109a2d87b79SAndriy Gapon 	 * the fix is borrowed from Linux.
110a2d87b79SAndriy Gapon 	 */
111a2d87b79SAndriy Gapon 	if (CPUID_TO_FAMILY(cpu_id) == 0x10) {
112a2d87b79SAndriy Gapon 		if ((cpu_feature2 & CPUID2_HV) == 0) {
113a2d87b79SAndriy Gapon 			msr = rdmsr(0xc001102a);
114a2d87b79SAndriy Gapon 			msr &= ~((uint64_t)1 << 24);
115a2d87b79SAndriy Gapon 			wrmsr(0xc001102a, msr);
116a2d87b79SAndriy Gapon 		}
117a2d87b79SAndriy Gapon 	}
118f1382605SAndriy Gapon 
119f1382605SAndriy Gapon 	/*
120f1382605SAndriy Gapon 	 * Work around Erratum 793: Specific Combination of Writes to Write
121f1382605SAndriy Gapon 	 * Combined Memory Types and Locked Instructions May Cause Core Hang.
122f1382605SAndriy Gapon 	 * See Revision Guide for AMD Family 16h Models 00h-0Fh Processors,
123f1382605SAndriy Gapon 	 * revision 3.04 or later, publication 51810.
124f1382605SAndriy Gapon 	 */
125f1382605SAndriy Gapon 	if (CPUID_TO_FAMILY(cpu_id) == 0x16 && CPUID_TO_MODEL(cpu_id) <= 0xf) {
126f1382605SAndriy Gapon 		if ((cpu_feature2 & CPUID2_HV) == 0) {
127f1382605SAndriy Gapon 			msr = rdmsr(0xc0011020);
128f1382605SAndriy Gapon 			msr |= (uint64_t)1 << 15;
129f1382605SAndriy Gapon 			wrmsr(0xc0011020, msr);
130f1382605SAndriy Gapon 		}
131f1382605SAndriy Gapon 	}
132cd155b56SDon Lewis 
133cd155b56SDon Lewis 	/*
134cd155b56SDon Lewis 	 * Work around a problem on Ryzen that is triggered by executing
135cd155b56SDon Lewis 	 * code near the top of user memory, in our case the signal
136cd155b56SDon Lewis 	 * trampoline code in the shared page on amd64.
137cd155b56SDon Lewis 	 *
138cd155b56SDon Lewis 	 * This function is executed once for the BSP before tunables take
139cd155b56SDon Lewis 	 * effect so the value determined here can be overridden by the
140cd155b56SDon Lewis 	 * tunable.  This function is then executed again for each AP and
141cd155b56SDon Lewis 	 * also on resume.  Set a flag the first time so that value set by
142cd155b56SDon Lewis 	 * the tunable is not overwritten.
143cd155b56SDon Lewis 	 *
144cd155b56SDon Lewis 	 * The stepping and/or microcode versions should be checked after
145cd155b56SDon Lewis 	 * this issue is fixed by AMD so that we don't use this mode if not
146cd155b56SDon Lewis 	 * needed.
147cd155b56SDon Lewis 	 */
148cd155b56SDon Lewis 	if (lower_sharedpage_init == 0) {
149cd155b56SDon Lewis 		lower_sharedpage_init = 1;
150cd155b56SDon Lewis 		if (CPUID_TO_FAMILY(cpu_id) == 0x17) {
151cd155b56SDon Lewis 			hw_lower_amd64_sharedpage = 1;
152cd155b56SDon Lewis 		}
153cd155b56SDon Lewis 	}
1543ce5dbccSJung-uk Kim }
1553ce5dbccSJung-uk Kim 
15692df0bdaSJung-uk Kim /*
157cd45fec0SJung-uk Kim  * Initialize special VIA features
15892df0bdaSJung-uk Kim  */
15992df0bdaSJung-uk Kim static void
16092df0bdaSJung-uk Kim init_via(void)
16192df0bdaSJung-uk Kim {
16292df0bdaSJung-uk Kim 	u_int regs[4], val;
16392df0bdaSJung-uk Kim 
164cd45fec0SJung-uk Kim 	/*
165cd45fec0SJung-uk Kim 	 * Check extended CPUID for PadLock features.
166cd45fec0SJung-uk Kim 	 *
167cd45fec0SJung-uk Kim 	 * http://www.via.com.tw/en/downloads/whitepapers/initiatives/padlock/programming_guide.pdf
168cd45fec0SJung-uk Kim 	 */
16992df0bdaSJung-uk Kim 	do_cpuid(0xc0000000, regs);
170cd45fec0SJung-uk Kim 	if (regs[0] >= 0xc0000001) {
17192df0bdaSJung-uk Kim 		do_cpuid(0xc0000001, regs);
17292df0bdaSJung-uk Kim 		val = regs[3];
17392df0bdaSJung-uk Kim 	} else
174cd45fec0SJung-uk Kim 		return;
17592df0bdaSJung-uk Kim 
176cd45fec0SJung-uk Kim 	/* Enable RNG if present. */
177cd45fec0SJung-uk Kim 	if ((val & VIA_CPUID_HAS_RNG) != 0) {
17892df0bdaSJung-uk Kim 		via_feature_rng = VIA_HAS_RNG;
179cd45fec0SJung-uk Kim 		wrmsr(0x110B, rdmsr(0x110B) | VIA_CPUID_DO_RNG);
18092df0bdaSJung-uk Kim 	}
181cd45fec0SJung-uk Kim 
182cd45fec0SJung-uk Kim 	/* Enable PadLock if present. */
183cd45fec0SJung-uk Kim 	if ((val & VIA_CPUID_HAS_ACE) != 0)
18492df0bdaSJung-uk Kim 		via_feature_xcrypt |= VIA_HAS_AES;
185cd45fec0SJung-uk Kim 	if ((val & VIA_CPUID_HAS_ACE2) != 0)
18692df0bdaSJung-uk Kim 		via_feature_xcrypt |= VIA_HAS_AESCTR;
187cd45fec0SJung-uk Kim 	if ((val & VIA_CPUID_HAS_PHE) != 0)
18892df0bdaSJung-uk Kim 		via_feature_xcrypt |= VIA_HAS_SHA;
189cd45fec0SJung-uk Kim 	if ((val & VIA_CPUID_HAS_PMM) != 0)
19092df0bdaSJung-uk Kim 		via_feature_xcrypt |= VIA_HAS_MM;
191cd45fec0SJung-uk Kim 	if (via_feature_xcrypt != 0)
192cd45fec0SJung-uk Kim 		wrmsr(0x1107, rdmsr(0x1107) | (1 << 28));
19392df0bdaSJung-uk Kim }
19492df0bdaSJung-uk Kim 
1959d146ac5SPeter Wemm /*
196430e272cSPeter Wemm  * Initialize CPU control registers
1979d146ac5SPeter Wemm  */
1989d146ac5SPeter Wemm void
199430e272cSPeter Wemm initializecpu(void)
2009d146ac5SPeter Wemm {
201430e272cSPeter Wemm 	uint64_t msr;
202cd9e9d1bSKonstantin Belousov 	uint32_t cr4;
203430e272cSPeter Wemm 
204cd9e9d1bSKonstantin Belousov 	cr4 = rcr4();
2059d146ac5SPeter Wemm 	if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) {
206cd9e9d1bSKonstantin Belousov 		cr4 |= CR4_FXSR | CR4_XMM;
2079d146ac5SPeter Wemm 		cpu_fxsr = hw_instruction_sse = 1;
2089d146ac5SPeter Wemm 	}
209cd9e9d1bSKonstantin Belousov 	if (cpu_stdext_feature & CPUID_STDEXT_FSGSBASE)
210cd9e9d1bSKonstantin Belousov 		cr4 |= CR4_FSGSBASE;
211cd9e9d1bSKonstantin Belousov 
212cd9e9d1bSKonstantin Belousov 	/*
213cd9e9d1bSKonstantin Belousov 	 * Postpone enabling the SMEP on the boot CPU until the page
214cd9e9d1bSKonstantin Belousov 	 * tables are switched from the boot loader identity mapping
215cd9e9d1bSKonstantin Belousov 	 * to the kernel tables.  The boot loader enables the U bit in
216cd9e9d1bSKonstantin Belousov 	 * its tables.
217cd9e9d1bSKonstantin Belousov 	 */
218cd9e9d1bSKonstantin Belousov 	if (!IS_BSP() && (cpu_stdext_feature & CPUID_STDEXT_SMEP))
219cd9e9d1bSKonstantin Belousov 		cr4 |= CR4_SMEP;
220cd9e9d1bSKonstantin Belousov 	load_cr4(cr4);
221*beb24065SJonathan T. Looney 	if (IS_BSP() && (amd_feature & AMDID_NX) != 0) {
222430e272cSPeter Wemm 		msr = rdmsr(MSR_EFER) | EFER_NXE;
223430e272cSPeter Wemm 		wrmsr(MSR_EFER, msr);
224430e272cSPeter Wemm 		pg_nx = PG_NX;
2259d146ac5SPeter Wemm 	}
226319117fdSKonstantin Belousov 	hw_ibrs_recalculate();
2273ce5dbccSJung-uk Kim 	switch (cpu_vendor_id) {
2283ce5dbccSJung-uk Kim 	case CPU_VENDOR_AMD:
2293ce5dbccSJung-uk Kim 		init_amd();
2303ce5dbccSJung-uk Kim 		break;
2313ce5dbccSJung-uk Kim 	case CPU_VENDOR_CENTAUR:
23292df0bdaSJung-uk Kim 		init_via();
2333ce5dbccSJung-uk Kim 		break;
2343ce5dbccSJung-uk Kim 	}
235ec24e8d4SKonstantin Belousov }
236ec24e8d4SKonstantin Belousov 
237ec24e8d4SKonstantin Belousov void
238cd234300SBrooks Davis initializecpucache(void)
239ec24e8d4SKonstantin Belousov {
240206a3368SKonstantin Belousov 
241206a3368SKonstantin Belousov 	/*
242206a3368SKonstantin Belousov 	 * CPUID with %eax = 1, %ebx returns
243206a3368SKonstantin Belousov 	 * Bits 15-8: CLFLUSH line size
244206a3368SKonstantin Belousov 	 * 	(Value * 8 = cache line size in bytes)
245206a3368SKonstantin Belousov 	 */
246206a3368SKonstantin Belousov 	if ((cpu_feature & CPUID_CLFSH) != 0)
247206a3368SKonstantin Belousov 		cpu_clflush_line_size = ((cpu_procinfo >> 8) & 0xff) * 8;
248b02395c6SKonstantin Belousov 	/*
2497134e390SJohn Baldwin 	 * XXXKIB: (temporary) hack to work around traps generated
2507134e390SJohn Baldwin 	 * when CLFLUSHing APIC register window under virtualization
2517134e390SJohn Baldwin 	 * environments.  These environments tend to disable the
2527134e390SJohn Baldwin 	 * CPUID_SS feature even though the native CPU supports it.
253b02395c6SKonstantin Belousov 	 */
2546f5c96c4SJun Kuriyama 	TUNABLE_INT_FETCH("hw.clflush_disable", &hw_clflush_disable);
255af95bbf5SKonstantin Belousov 	if (vm_guest != VM_GUEST_NO && hw_clflush_disable == -1) {
256b02395c6SKonstantin Belousov 		cpu_feature &= ~CPUID_CLFSH;
257af95bbf5SKonstantin Belousov 		cpu_stdext_feature &= ~CPUID_STDEXT_CLFLUSHOPT;
258af95bbf5SKonstantin Belousov 	}
259af95bbf5SKonstantin Belousov 
2606f5c96c4SJun Kuriyama 	/*
261af95bbf5SKonstantin Belousov 	 * The kernel's use of CLFLUSH{,OPT} can be disabled manually
262af95bbf5SKonstantin Belousov 	 * by setting the hw.clflush_disable tunable.
2636f5c96c4SJun Kuriyama 	 */
264af95bbf5SKonstantin Belousov 	if (hw_clflush_disable == 1) {
2656f5c96c4SJun Kuriyama 		cpu_feature &= ~CPUID_CLFSH;
266af95bbf5SKonstantin Belousov 		cpu_stdext_feature &= ~CPUID_STDEXT_CLFLUSHOPT;
267af95bbf5SKonstantin Belousov 	}
2686f5c96c4SJun Kuriyama }
269