xref: /freebsd/sys/amd64/amd64/initcpu.c (revision 20916c1f242edc9099ab3742024b0cb8fa27d129)
1a8e282d6SKATO Takenori /*
2a8e282d6SKATO Takenori  * Copyright (c) KATO Takenori, 1997.
3a8e282d6SKATO Takenori  *
4a8e282d6SKATO Takenori  * All rights reserved.  Unpublished rights reserved under the copyright
5a8e282d6SKATO Takenori  * laws of Japan.
6a8e282d6SKATO Takenori  *
7a8e282d6SKATO Takenori  * Redistribution and use in source and binary forms, with or without
8a8e282d6SKATO Takenori  * modification, are permitted provided that the following conditions
9a8e282d6SKATO Takenori  * are met:
10a8e282d6SKATO Takenori  *
11a8e282d6SKATO Takenori  * 1. Redistributions of source code must retain the above copyright
12a8e282d6SKATO Takenori  *    notice, this list of conditions and the following disclaimer as
13a8e282d6SKATO Takenori  *    the first lines of this file unmodified.
14a8e282d6SKATO Takenori  * 2. Redistributions in binary form must reproduce the above copyright
15a8e282d6SKATO Takenori  *    notice, this list of conditions and the following disclaimer in the
16a8e282d6SKATO Takenori  *    documentation and/or other materials provided with the distribution.
17a8e282d6SKATO Takenori  *
18a8e282d6SKATO Takenori  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19a8e282d6SKATO Takenori  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20a8e282d6SKATO Takenori  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21a8e282d6SKATO Takenori  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22a8e282d6SKATO Takenori  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23a8e282d6SKATO Takenori  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24a8e282d6SKATO Takenori  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25a8e282d6SKATO Takenori  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26a8e282d6SKATO Takenori  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27a8e282d6SKATO Takenori  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28a8e282d6SKATO Takenori  *
2920916c1fSKATO Takenori  *		$Id: initcpu.c,v 1.4 1997/04/26 04:08:45 kato Exp $
30a8e282d6SKATO Takenori  */
31a8e282d6SKATO Takenori 
32a8e282d6SKATO Takenori #include "opt_cpu.h"
33a8e282d6SKATO Takenori 
34a8e282d6SKATO Takenori #include <sys/param.h>
35a8e282d6SKATO Takenori #include <sys/kernel.h>
36a8e282d6SKATO Takenori #include <sys/systm.h>
37a8e282d6SKATO Takenori 
38a8e282d6SKATO Takenori #include <machine/cpu.h>
39a8e282d6SKATO Takenori #include <machine/cputypes.h>
40a8e282d6SKATO Takenori #include <machine/md_var.h>
41a8e282d6SKATO Takenori #include <machine/specialreg.h>
42a8e282d6SKATO Takenori 
43a8e282d6SKATO Takenori void initializecpu(void);
44a8e282d6SKATO Takenori #ifdef I486_CPU
45a8e282d6SKATO Takenori static void init_5x86(void);
46a8e282d6SKATO Takenori static void init_bluelightning(void);
47a8e282d6SKATO Takenori static void init_486dlc(void);
489ca82267SKATO Takenori static void init_cy486dx(void);
49a8e282d6SKATO Takenori #ifdef CPU_I486_ON_386
50a8e282d6SKATO Takenori static void init_i486_on_386(void);
51a8e282d6SKATO Takenori #endif
52a8e282d6SKATO Takenori static void init_6x86(void);
53a8e282d6SKATO Takenori #endif /* I486_CPU */
54a8e282d6SKATO Takenori 
5520916c1fSKATO Takenori #ifdef I586_CPU
5620916c1fSKATO Takenori static void	init_6x86MX(void);
5720916c1fSKATO Takenori #endif
5820916c1fSKATO Takenori 
59a8e282d6SKATO Takenori #ifdef I486_CPU
60a8e282d6SKATO Takenori /*
61a8e282d6SKATO Takenori  * IBM Blue Lightning
62a8e282d6SKATO Takenori  */
63a8e282d6SKATO Takenori static void
64a8e282d6SKATO Takenori init_bluelightning(void)
65a8e282d6SKATO Takenori {
66a8e282d6SKATO Takenori 	u_long	eflags;
67a8e282d6SKATO Takenori 
68a8e282d6SKATO Takenori #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
69a8e282d6SKATO Takenori 	need_post_dma_flush = 1;
70a8e282d6SKATO Takenori #endif
71a8e282d6SKATO Takenori 
72a8e282d6SKATO Takenori 	eflags = read_eflags();
73a8e282d6SKATO Takenori 	disable_intr();
74a8e282d6SKATO Takenori 
75a8e282d6SKATO Takenori 	load_cr0(rcr0() | CR0_CD | CR0_NW);
76a8e282d6SKATO Takenori 	invd();
77a8e282d6SKATO Takenori 
78a8e282d6SKATO Takenori #ifdef CPU_BLUELIGHTNING_FPU_OP_CACHE
79a8e282d6SKATO Takenori 	wrmsr(0x1000, 0x9c92LL);	/* FP operand can be cacheable on Cyrix FPU */
80a8e282d6SKATO Takenori #else
81a8e282d6SKATO Takenori 	wrmsr(0x1000, 0x1c92LL);	/* Intel FPU */
82a8e282d6SKATO Takenori #endif
83a8e282d6SKATO Takenori 	/* Enables 13MB and 0-640KB cache. */
84a8e282d6SKATO Takenori 	wrmsr(0x1001, (0xd0LL << 32) | 0x3ff);
85a8e282d6SKATO Takenori #ifdef CPU_BLUELIGHTNING_3X
86a8e282d6SKATO Takenori 	wrmsr(0x1002, 0x04000000LL);	/* Enables triple-clock mode. */
87a8e282d6SKATO Takenori #else
88a8e282d6SKATO Takenori 	wrmsr(0x1002, 0x03000000LL);	/* Enables double-clock mode. */
89a8e282d6SKATO Takenori #endif
90a8e282d6SKATO Takenori 
91a8e282d6SKATO Takenori 	/* Enable caching in CR0. */
92a8e282d6SKATO Takenori 	load_cr0(rcr0() & ~(CR0_CD | CR0_NW));	/* CD = 0 and NW = 0 */
93a8e282d6SKATO Takenori 	invd();
94a8e282d6SKATO Takenori 	write_eflags(eflags);
95a8e282d6SKATO Takenori }
96a8e282d6SKATO Takenori 
97a8e282d6SKATO Takenori /*
989ca82267SKATO Takenori  * Cyrix 486SLC/DLC/SR/DR series
99a8e282d6SKATO Takenori  */
100a8e282d6SKATO Takenori static void
101a8e282d6SKATO Takenori init_486dlc(void)
102a8e282d6SKATO Takenori {
103a8e282d6SKATO Takenori 	u_long	eflags;
104a8e282d6SKATO Takenori 	u_char	ccr0;
105a8e282d6SKATO Takenori 
106a8e282d6SKATO Takenori 	eflags = read_eflags();
107a8e282d6SKATO Takenori 	disable_intr();
108a8e282d6SKATO Takenori 	invd();
109a8e282d6SKATO Takenori 
110a8e282d6SKATO Takenori 	ccr0 = read_cyrix_reg(CCR0);
111a8e282d6SKATO Takenori #ifndef CYRIX_CACHE_WORKS
112a8e282d6SKATO Takenori 	ccr0 |= CCR0_NC1 | CCR0_BARB;
113a8e282d6SKATO Takenori 	write_cyrix_reg(CCR0, ccr0);
114a8e282d6SKATO Takenori 	invd();
115a8e282d6SKATO Takenori #else
116a8e282d6SKATO Takenori 	ccr0 &= ~CCR0_NC0;
117a8e282d6SKATO Takenori #ifndef CYRIX_CACHE_REALLY_WORKS
118a8e282d6SKATO Takenori 	ccr0 |= CCR0_NC1 | CCR0_BARB;
119a8e282d6SKATO Takenori #else
120a8e282d6SKATO Takenori 	ccr0 |= CCR0_NC1;
121a8e282d6SKATO Takenori #endif
122a8e282d6SKATO Takenori 	write_cyrix_reg(CCR0, ccr0);
123a8e282d6SKATO Takenori 
124a8e282d6SKATO Takenori 	/* Clear non-cacheable region. */
125a8e282d6SKATO Takenori 	write_cyrix_reg(NCR1+2, NCR_SIZE_0K);
126a8e282d6SKATO Takenori 	write_cyrix_reg(NCR2+2, NCR_SIZE_0K);
127a8e282d6SKATO Takenori 	write_cyrix_reg(NCR3+2, NCR_SIZE_0K);
128a8e282d6SKATO Takenori 	write_cyrix_reg(NCR4+2, NCR_SIZE_0K);
129a8e282d6SKATO Takenori 
130a8e282d6SKATO Takenori 	write_cyrix_reg(0, 0);	/* dummy write */
131a8e282d6SKATO Takenori 
132a8e282d6SKATO Takenori 	/* Enable caching in CR0. */
133a8e282d6SKATO Takenori 	load_cr0(rcr0() & ~(CR0_CD | CR0_NW));	/* CD = 0 and NW = 0 */
134a8e282d6SKATO Takenori 	invd();
135a8e282d6SKATO Takenori #endif /* !CYRIX_CACHE_WORKS */
136a8e282d6SKATO Takenori 	write_eflags(eflags);
137a8e282d6SKATO Takenori }
138a8e282d6SKATO Takenori 
139a8e282d6SKATO Takenori 
140a8e282d6SKATO Takenori /*
1419ca82267SKATO Takenori  * Cyrix 486S/DX series
1429ca82267SKATO Takenori  */
1439ca82267SKATO Takenori static void
1449ca82267SKATO Takenori init_cy486dx(void)
1459ca82267SKATO Takenori {
1469ca82267SKATO Takenori 	u_long	eflags;
1479ca82267SKATO Takenori 	u_char	ccr2;
1489ca82267SKATO Takenori 
1499ca82267SKATO Takenori 	eflags = read_eflags();
1509ca82267SKATO Takenori 	disable_intr();
1519ca82267SKATO Takenori 	invd();
1529ca82267SKATO Takenori 
1539ca82267SKATO Takenori 	ccr2 = read_cyrix_reg(CCR2);
1549ca82267SKATO Takenori #ifdef SUSP_HLT
1559ca82267SKATO Takenori 	ccr2 |= CCR2_SUSP_HTL;
1569ca82267SKATO Takenori #endif
1579ca82267SKATO Takenori 	write_cyrix_reg(CCR2, ccr2);
1589ca82267SKATO Takenori 	write_eflags(eflags);
1599ca82267SKATO Takenori }
1609ca82267SKATO Takenori 
1619ca82267SKATO Takenori 
1629ca82267SKATO Takenori /*
163a8e282d6SKATO Takenori  * Cyrix 5x86
164a8e282d6SKATO Takenori  */
165a8e282d6SKATO Takenori static void
166a8e282d6SKATO Takenori init_5x86(void)
167a8e282d6SKATO Takenori {
168a8e282d6SKATO Takenori 	u_long	eflags;
169a8e282d6SKATO Takenori 	u_char	ccr2, ccr3, ccr4, pcr0;
170a8e282d6SKATO Takenori 
171a8e282d6SKATO Takenori 	eflags = read_eflags();
172a8e282d6SKATO Takenori 	disable_intr();
173a8e282d6SKATO Takenori 
174a8e282d6SKATO Takenori 	load_cr0(rcr0() | CR0_CD | CR0_NW);
175a8e282d6SKATO Takenori 	wbinvd();
176a8e282d6SKATO Takenori 
177a8e282d6SKATO Takenori 	(void)read_cyrix_reg(CCR3);		/* dummy */
178a8e282d6SKATO Takenori 
179a8e282d6SKATO Takenori 	/* Initialize CCR2. */
180a8e282d6SKATO Takenori 	ccr2 = read_cyrix_reg(CCR2);
181a8e282d6SKATO Takenori 	ccr2 |= CCR2_WB;
182a8e282d6SKATO Takenori #ifdef CPU_SUSP_HLT
183a8e282d6SKATO Takenori 	ccr2 |= CCR2_SUSP_HLT;
184a8e282d6SKATO Takenori #else
185a8e282d6SKATO Takenori 	ccr2 &= ~CCR2_SUSP_HLT;
186a8e282d6SKATO Takenori #endif
187a8e282d6SKATO Takenori 	ccr2 |= CCR2_WT1;
188a8e282d6SKATO Takenori 	write_cyrix_reg(CCR2, ccr2);
189a8e282d6SKATO Takenori 
190a8e282d6SKATO Takenori 	/* Initialize CCR4. */
191a8e282d6SKATO Takenori 	ccr3 = read_cyrix_reg(CCR3);
192a8e282d6SKATO Takenori 	write_cyrix_reg(CCR3, CCR3_MAPEN0);
193a8e282d6SKATO Takenori 
194a8e282d6SKATO Takenori 	ccr4 = read_cyrix_reg(CCR4);
195a8e282d6SKATO Takenori 	ccr4 |= CCR4_DTE;
196a8e282d6SKATO Takenori 	ccr4 |= CCR4_MEM;
197a8e282d6SKATO Takenori #ifdef CPU_FASTER_5X86_FPU
198a8e282d6SKATO Takenori 	ccr4 |= CCR4_FASTFPE;
199a8e282d6SKATO Takenori #else
200a8e282d6SKATO Takenori 	ccr4 &= ~CCR4_FASTFPE;
201a8e282d6SKATO Takenori #endif
202a8e282d6SKATO Takenori 	ccr4 &= ~CCR4_IOMASK;
203a8e282d6SKATO Takenori 	/********************************************************************
204a8e282d6SKATO Takenori 	 * WARNING: The "BIOS Writers Guide" mentions that I/O recovery time
205a8e282d6SKATO Takenori 	 * should be 0 for errata fix.
206a8e282d6SKATO Takenori 	 ********************************************************************/
207a8e282d6SKATO Takenori #ifdef CPU_IORT
208a8e282d6SKATO Takenori 	ccr4 |= CPU_IORT & CCR4_IOMASK;
209a8e282d6SKATO Takenori #endif
210a8e282d6SKATO Takenori 	write_cyrix_reg(CCR4, ccr4);
211a8e282d6SKATO Takenori 
212a8e282d6SKATO Takenori 	/* Initialize PCR0. */
213a8e282d6SKATO Takenori 	/****************************************************************
214a8e282d6SKATO Takenori 	 * WARNING: RSTK_EN and LOOP_EN could make your system unstable.
215a8e282d6SKATO Takenori 	 * BTB_EN might make your system unstable.
216a8e282d6SKATO Takenori 	 ****************************************************************/
217a8e282d6SKATO Takenori 	pcr0 = read_cyrix_reg(PCR0);
218a8e282d6SKATO Takenori #ifdef CPU_RSTK_EN
219a8e282d6SKATO Takenori 	pcr0 |= PCR0_RSTK;
220a8e282d6SKATO Takenori #else
221a8e282d6SKATO Takenori 	pcr0 &= ~PCR0_RSTK;
222a8e282d6SKATO Takenori #endif
223a8e282d6SKATO Takenori #ifdef CPU_BTB_EN
224a8e282d6SKATO Takenori 	pcr0 |= PCR0_BTB;
225a8e282d6SKATO Takenori #else
226a8e282d6SKATO Takenori 	pcr0 &= ~PCR0_BTB;
227a8e282d6SKATO Takenori #endif
228a8e282d6SKATO Takenori #ifdef CPU_LOOP_EN
229a8e282d6SKATO Takenori 	pcr0 |= PCR0_LOOP;
230a8e282d6SKATO Takenori #else
231a8e282d6SKATO Takenori 	pcr0 &= ~PCR0_LOOP;
232a8e282d6SKATO Takenori #endif
233a8e282d6SKATO Takenori 
234a8e282d6SKATO Takenori 	/****************************************************************
235a8e282d6SKATO Takenori 	 * WARNING: if you use a memory mapped I/O device, don't use
236a8e282d6SKATO Takenori 	 * DISABLE_5X86_LSSER option, which may reorder memory mapped
237a8e282d6SKATO Takenori 	 * I/O access.
238a8e282d6SKATO Takenori 	 * IF YOUR MOTHERBOARD HAS PCI BUS, DON'T DISABLE LSSER.
239a8e282d6SKATO Takenori 	 ****************************************************************/
240a8e282d6SKATO Takenori #ifdef CPU_DISABLE_5X86_LSSER
241a8e282d6SKATO Takenori 	pcr0 &= ~PCR0_LSSER;
242a8e282d6SKATO Takenori #else
243a8e282d6SKATO Takenori 	pcr0 |= PCR0_LSSER;
244a8e282d6SKATO Takenori #endif
245a8e282d6SKATO Takenori 	write_cyrix_reg(PCR0, pcr0);
246a8e282d6SKATO Takenori 
247a8e282d6SKATO Takenori 	/* Restore CCR3. */
248a8e282d6SKATO Takenori 	write_cyrix_reg(CCR3, ccr3);
249a8e282d6SKATO Takenori 
250a8e282d6SKATO Takenori 	(void)read_cyrix_reg(0x80);		/* dummy */
251a8e282d6SKATO Takenori 
252a8e282d6SKATO Takenori 	/* Unlock NW bit in CR0. */
253a8e282d6SKATO Takenori 	write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
254a8e282d6SKATO Takenori 	load_cr0((rcr0() & ~CR0_CD) | CR0_NW);	/* CD = 0, NW = 1 */
255a8e282d6SKATO Takenori 	/* Lock NW bit in CR0. */
256a8e282d6SKATO Takenori 	write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
257a8e282d6SKATO Takenori 
258a8e282d6SKATO Takenori 	write_eflags(eflags);
259a8e282d6SKATO Takenori }
260a8e282d6SKATO Takenori 
261a8e282d6SKATO Takenori #ifdef CPU_I486_ON_386
262a8e282d6SKATO Takenori /*
263a8e282d6SKATO Takenori  * There are i486 based upgrade products for i386 machines.
264a8e282d6SKATO Takenori  * In this case, BIOS doesn't enables CPU cache.
265a8e282d6SKATO Takenori  */
266a8e282d6SKATO Takenori void
267a8e282d6SKATO Takenori init_i486_on_386(void)
268a8e282d6SKATO Takenori {
269a8e282d6SKATO Takenori 	u_long	eflags;
270a8e282d6SKATO Takenori 
271a8e282d6SKATO Takenori #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
272a8e282d6SKATO Takenori 	need_post_dma_flush = 1;
273a8e282d6SKATO Takenori #endif
274a8e282d6SKATO Takenori 
275a8e282d6SKATO Takenori 	eflags = read_eflags();
276a8e282d6SKATO Takenori 	disable_intr();
277a8e282d6SKATO Takenori 
278a8e282d6SKATO Takenori 	load_cr0(rcr0() & ~(CR0_CD | CR0_NW));	/* CD = 0, NW = 0 */
279a8e282d6SKATO Takenori 
2805fa4a058SKATO Takenori 	write_eflags(eflags);
281a8e282d6SKATO Takenori }
282a8e282d6SKATO Takenori #endif
283a8e282d6SKATO Takenori 
284a8e282d6SKATO Takenori /*
285a8e282d6SKATO Takenori  * Cyrix 6x86
286a8e282d6SKATO Takenori  *
287a8e282d6SKATO Takenori  * XXX - What should I do here?  Please let me know.
288a8e282d6SKATO Takenori  */
289a8e282d6SKATO Takenori static void
290a8e282d6SKATO Takenori init_6x86(void)
291a8e282d6SKATO Takenori {
292a8e282d6SKATO Takenori 	u_long	eflags;
293a8e282d6SKATO Takenori 	u_char	ccr3, ccr4;
294a8e282d6SKATO Takenori 
295a8e282d6SKATO Takenori 	eflags = read_eflags();
296a8e282d6SKATO Takenori 	disable_intr();
297a8e282d6SKATO Takenori 
298a8e282d6SKATO Takenori 	load_cr0(rcr0() | CR0_CD | CR0_NW);
299a8e282d6SKATO Takenori 	wbinvd();
300a8e282d6SKATO Takenori 
301a8e282d6SKATO Takenori 	/* Initialize CCR0. */
302a8e282d6SKATO Takenori 	write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
303a8e282d6SKATO Takenori 
304a8e282d6SKATO Takenori 	/* Initialize CCR2. */
305a8e282d6SKATO Takenori #ifdef CPU_SUSP_HLT
306a8e282d6SKATO Takenori 	write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
307a8e282d6SKATO Takenori #else
308a8e282d6SKATO Takenori 	write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
309a8e282d6SKATO Takenori #endif
310a8e282d6SKATO Takenori 
311a8e282d6SKATO Takenori 	ccr3 = read_cyrix_reg(CCR3);
312a8e282d6SKATO Takenori 	write_cyrix_reg(CCR3, CCR3_MAPEN0);
313a8e282d6SKATO Takenori 
314a8e282d6SKATO Takenori 	/* Initialize CCR4. */
315a8e282d6SKATO Takenori 	ccr4 = read_cyrix_reg(CCR4);
316a8e282d6SKATO Takenori 	ccr4 |= CCR4_DTE;
317a8e282d6SKATO Takenori 	ccr4 &= ~CCR4_IOMASK;
318a8e282d6SKATO Takenori #ifdef CPU_IORT
319a8e282d6SKATO Takenori 	write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
320a8e282d6SKATO Takenori #else
321a8e282d6SKATO Takenori 	write_cyrix_reg(CCR4, ccr4 | 7);
322a8e282d6SKATO Takenori #endif
323a8e282d6SKATO Takenori 
324a8e282d6SKATO Takenori 	/* Restore CCR3. */
325a8e282d6SKATO Takenori 	write_cyrix_reg(CCR3, ccr3);
326a8e282d6SKATO Takenori 
327a8e282d6SKATO Takenori 	/* Unlock NW bit in CR0. */
328a8e282d6SKATO Takenori 	write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
329a8e282d6SKATO Takenori 
330a8e282d6SKATO Takenori 	/*
331a8e282d6SKATO Takenori 	 * Earlier revision of the 6x86 CPU could crash the system if
332a8e282d6SKATO Takenori 	 * L1 cache is in write-back mode.
333a8e282d6SKATO Takenori 	 */
334a8e282d6SKATO Takenori 	if ((cyrix_did & 0xff00) > 0x1600)
335a8e282d6SKATO Takenori 		load_cr0(rcr0() & ~(CR0_CD | CR0_NW));	/* CD = 0 and NW = 0 */
336a8e282d6SKATO Takenori 	else {
337a8e282d6SKATO Takenori 		/* Revision 2.6 and lower. */
338a8e282d6SKATO Takenori #ifdef CYRIX_CACHE_REALLY_WORKS
339a8e282d6SKATO Takenori 		load_cr0(rcr0() & ~(CR0_CD | CR0_NW));	/* CD = 0 and NW = 0 */
340a8e282d6SKATO Takenori #else
341a8e282d6SKATO Takenori 		load_cr0((rcr0() & ~CR0_CD) | CR0_NW);	/* CD = 0 and NW = 1 */
342a8e282d6SKATO Takenori #endif
343a8e282d6SKATO Takenori 	}
344a8e282d6SKATO Takenori 
345a8e282d6SKATO Takenori 	/* Lock NW bit in CR0. */
346a8e282d6SKATO Takenori 	write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
347a8e282d6SKATO Takenori 
348a8e282d6SKATO Takenori 	write_eflags(eflags);
349a8e282d6SKATO Takenori }
350a8e282d6SKATO Takenori #endif /* I486_CPU */
351a8e282d6SKATO Takenori 
35220916c1fSKATO Takenori #ifdef I586_CPU
35320916c1fSKATO Takenori /*
35420916c1fSKATO Takenori  * Cyrix 6x86MX (code-named M2)
35520916c1fSKATO Takenori  *
35620916c1fSKATO Takenori  * XXX - What should I do here?  Please let me know.
35720916c1fSKATO Takenori  */
35820916c1fSKATO Takenori static void
35920916c1fSKATO Takenori init_6x86MX(void)
36020916c1fSKATO Takenori {
36120916c1fSKATO Takenori 	u_long	eflags;
36220916c1fSKATO Takenori 	u_char	ccr3, ccr4;
36320916c1fSKATO Takenori 
36420916c1fSKATO Takenori 	eflags = read_eflags();
36520916c1fSKATO Takenori 	disable_intr();
36620916c1fSKATO Takenori 
36720916c1fSKATO Takenori 	load_cr0(rcr0() | CR0_CD | CR0_NW);
36820916c1fSKATO Takenori 	wbinvd();
36920916c1fSKATO Takenori 
37020916c1fSKATO Takenori 	/* Initialize CCR0. */
37120916c1fSKATO Takenori 	write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
37220916c1fSKATO Takenori 
37320916c1fSKATO Takenori 	/* Initialize CCR2. */
37420916c1fSKATO Takenori #ifdef CPU_SUSP_HLT
37520916c1fSKATO Takenori 	write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
37620916c1fSKATO Takenori #else
37720916c1fSKATO Takenori 	write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
37820916c1fSKATO Takenori #endif
37920916c1fSKATO Takenori 
38020916c1fSKATO Takenori 	ccr3 = read_cyrix_reg(CCR3);
38120916c1fSKATO Takenori 	write_cyrix_reg(CCR3, CCR3_MAPEN0);
38220916c1fSKATO Takenori 
38320916c1fSKATO Takenori 	/* Initialize CCR4. */
38420916c1fSKATO Takenori 	ccr4 = read_cyrix_reg(CCR4);
38520916c1fSKATO Takenori 	ccr4 &= ~CCR4_IOMASK;
38620916c1fSKATO Takenori #ifdef CPU_IORT
38720916c1fSKATO Takenori 	write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
38820916c1fSKATO Takenori #else
38920916c1fSKATO Takenori 	write_cyrix_reg(CCR4, ccr4 | 7);
39020916c1fSKATO Takenori #endif
39120916c1fSKATO Takenori 
39220916c1fSKATO Takenori 	/* Restore CCR3. */
39320916c1fSKATO Takenori 	write_cyrix_reg(CCR3, ccr3);
39420916c1fSKATO Takenori 
39520916c1fSKATO Takenori 	/* Unlock NW bit in CR0. */
39620916c1fSKATO Takenori 	write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
39720916c1fSKATO Takenori 
39820916c1fSKATO Takenori 	load_cr0(rcr0() & ~(CR0_CD | CR0_NW));	/* CD = 0 and NW = 0 */
39920916c1fSKATO Takenori 
40020916c1fSKATO Takenori 	/* Lock NW bit in CR0. */
40120916c1fSKATO Takenori 	write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
40220916c1fSKATO Takenori 
40320916c1fSKATO Takenori 	write_eflags(eflags);
40420916c1fSKATO Takenori }
40520916c1fSKATO Takenori #endif /* I586_CPU */
40620916c1fSKATO Takenori 
407a8e282d6SKATO Takenori void
408a8e282d6SKATO Takenori initializecpu(void)
409a8e282d6SKATO Takenori {
410a8e282d6SKATO Takenori 
411a8e282d6SKATO Takenori 	switch (cpu) {
412a8e282d6SKATO Takenori #ifdef I486_CPU
413a8e282d6SKATO Takenori 	case CPU_BLUE:
414a8e282d6SKATO Takenori 		init_bluelightning();
415a8e282d6SKATO Takenori 		break;
416a8e282d6SKATO Takenori 	case CPU_486DLC:
417a8e282d6SKATO Takenori 		init_486dlc();
418a8e282d6SKATO Takenori 		break;
4199ca82267SKATO Takenori 	case CPU_CY486DX:
4209ca82267SKATO Takenori 		init_cy486dx();
4219ca82267SKATO Takenori 		break;
422a8e282d6SKATO Takenori 	case CPU_M1SC:
423a8e282d6SKATO Takenori 		init_5x86();
424a8e282d6SKATO Takenori 		break;
425a8e282d6SKATO Takenori #ifdef CPU_I486_ON_386
426a8e282d6SKATO Takenori 	case CPU_486:
427a8e282d6SKATO Takenori 		init_i486_on_386();
428a8e282d6SKATO Takenori 		break;
429a8e282d6SKATO Takenori #endif
430a8e282d6SKATO Takenori 	case CPU_M1:
431a8e282d6SKATO Takenori 		init_6x86();
432a8e282d6SKATO Takenori 		break;
433a8e282d6SKATO Takenori #endif /* I486_CPU */
43420916c1fSKATO Takenori #ifdef I586_CPU
43520916c1fSKATO Takenori 	case CPU_M2:
43620916c1fSKATO Takenori 		init_6x86MX();
43720916c1fSKATO Takenori 		break;
43820916c1fSKATO Takenori #endif
439a8e282d6SKATO Takenori 	default:
440a8e282d6SKATO Takenori 		break;
441a8e282d6SKATO Takenori 	}
442a8e282d6SKATO Takenori 
443a8e282d6SKATO Takenori #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
444a8e282d6SKATO Takenori 	/*
445a8e282d6SKATO Takenori 	 * OS should flush L1 cahce by itself because no PC-98 supports
446a8e282d6SKATO Takenori 	 * non-Intel CPUs.  Use wbinvd instruction before DMA transfer
447a8e282d6SKATO Takenori 	 * when need_pre_dma_flush = 1, use invd instruction after DMA
448a8e282d6SKATO Takenori 	 * transfer when need_post_dma_flush = 1.  If your CPU upgrade
449a8e282d6SKATO Takenori 	 * product support hardware cache control, you can add
450a8e282d6SKATO Takenori 	 * UPGRADE_CPU_HW_CACHE option in your kernel configuration file.
451a8e282d6SKATO Takenori 	 * This option elminate unneeded cache flush instruction.
452a8e282d6SKATO Takenori 	 */
453a8e282d6SKATO Takenori 	if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
454a8e282d6SKATO Takenori 		switch (cpu) {
455a8e282d6SKATO Takenori #ifdef I486_CPU
456a8e282d6SKATO Takenori 		case CPU_486DLC:
457a8e282d6SKATO Takenori 			need_post_dma_flush = 1;
458a8e282d6SKATO Takenori 			break;
459a8e282d6SKATO Takenori 		case CPU_M1SC:
460a8e282d6SKATO Takenori 			need_pre_dma_flush = 1;
461a8e282d6SKATO Takenori 			break;
462a8e282d6SKATO Takenori #endif
463a8e282d6SKATO Takenori 		default:
464a8e282d6SKATO Takenori 			break;
465a8e282d6SKATO Takenori 		}
466a8e282d6SKATO Takenori 	} else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
467a8e282d6SKATO Takenori 		switch (cpu_id & 0xFF0) {
468a8e282d6SKATO Takenori 		case 0x470:		/* Enhanced Am486DX2 WB */
469a8e282d6SKATO Takenori 		case 0x490:		/* Enhanced Am486DX4 WB */
470a8e282d6SKATO Takenori 		case 0x4F0:		/* Am5x86 WB */
471a8e282d6SKATO Takenori 			need_pre_dma_flush = 1;
472a8e282d6SKATO Takenori 			break;
473a8e282d6SKATO Takenori 		}
474a8e282d6SKATO Takenori 	} else if (strcmp(cpu_vendor, "IBM") == 0) {
475a8e282d6SKATO Takenori 		need_post_dma_flush = 1;
476a8e282d6SKATO Takenori 	} else {
477a8e282d6SKATO Takenori #ifdef CPU_I486_ON_386
478a8e282d6SKATO Takenori 		need_pre_dma_flush = 1;
479a8e282d6SKATO Takenori #endif
480a8e282d6SKATO Takenori 	}
481a8e282d6SKATO Takenori #endif /* PC98 && !UPGRADE_CPU_HW_CACHE */
482a8e282d6SKATO Takenori }
483a8e282d6SKATO Takenori 
484a8e282d6SKATO Takenori #include "opt_ddb.h"
485a8e282d6SKATO Takenori #ifdef DDB
486a8e282d6SKATO Takenori #include <ddb/ddb.h>
487a8e282d6SKATO Takenori 
488a8e282d6SKATO Takenori DB_SHOW_COMMAND(cyrixreg, cyrixreg)
489a8e282d6SKATO Takenori {
490a8e282d6SKATO Takenori 	u_long	eflags;
491a8e282d6SKATO Takenori 	u_int	cr0;
492a8e282d6SKATO Takenori 	u_char	ccr0, ccr1, ccr2, ccr3, ccr4, ccr5, pcr0;
493a8e282d6SKATO Takenori 
494a8e282d6SKATO Takenori 	cr0 = rcr0();
495a8e282d6SKATO Takenori 	if (strcmp(cpu_vendor,"CyrixInstead") == 0) {
496a8e282d6SKATO Takenori 		eflags = read_eflags();
497a8e282d6SKATO Takenori 		disable_intr();
498a8e282d6SKATO Takenori 
499a8e282d6SKATO Takenori 
5009ca82267SKATO Takenori 		if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) {
501a8e282d6SKATO Takenori 			ccr0 = read_cyrix_reg(CCR0);
502a8e282d6SKATO Takenori 		}
503a8e282d6SKATO Takenori 		ccr1 = read_cyrix_reg(CCR1);
504a8e282d6SKATO Takenori 		ccr2 = read_cyrix_reg(CCR2);
505a8e282d6SKATO Takenori 		ccr3 = read_cyrix_reg(CCR3);
506a8e282d6SKATO Takenori 		if ((cpu == CPU_M1SC) || (cpu == CPU_M1)) {
507a8e282d6SKATO Takenori 			write_cyrix_reg(CCR3, CCR3_MAPEN0);
508a8e282d6SKATO Takenori 			ccr4 = read_cyrix_reg(CCR4);
509a8e282d6SKATO Takenori 			if (cpu == CPU_M1)
510a8e282d6SKATO Takenori 				ccr5 = read_cyrix_reg(CCR5);
511a8e282d6SKATO Takenori 			else
512a8e282d6SKATO Takenori 				pcr0 = read_cyrix_reg(PCR0);
513a8e282d6SKATO Takenori 			write_cyrix_reg(CCR3, ccr3);		/* Restore CCR3. */
514a8e282d6SKATO Takenori 		}
515a8e282d6SKATO Takenori 		write_eflags(eflags);
516a8e282d6SKATO Takenori 
5179ca82267SKATO Takenori 		if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX))
518a8e282d6SKATO Takenori 			printf("CCR0=%x, ", (u_int)ccr0);
519a8e282d6SKATO Takenori 
520a8e282d6SKATO Takenori 		printf("CCR1=%x, CCR2=%x, CCR3=%x",
521a8e282d6SKATO Takenori 			(u_int)ccr1, (u_int)ccr2, (u_int)ccr3);
522a8e282d6SKATO Takenori 		if ((cpu == CPU_M1SC) || (cpu == CPU_M1)) {
523a8e282d6SKATO Takenori 			printf(", CCR4=%x, ", (u_int)ccr4);
524a8e282d6SKATO Takenori 			if (cpu == CPU_M1)
525a8e282d6SKATO Takenori 				printf("CCR5=%x\n", ccr5);
526a8e282d6SKATO Takenori 			else
527a8e282d6SKATO Takenori 				printf("PCR0=%x\n", pcr0);
528a8e282d6SKATO Takenori 		}
529a8e282d6SKATO Takenori 	}
530a8e282d6SKATO Takenori 	printf("CR0=%x\n", cr0);
531a8e282d6SKATO Takenori }
532a8e282d6SKATO Takenori #endif /* DDB */
533