1 /*- 2 * Copyright (c) 1990 William Jolitz. 3 * Copyright (c) 1991 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by the University of 17 * California, Berkeley and its contributors. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 35 * $Id: npx.c,v 1.28 1996/01/04 19:51:14 wollman Exp $ 36 */ 37 38 #include "npx.h" 39 #if NNPX > 0 40 41 #include "opt_math_emulate.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/sysctl.h> 47 #include <sys/conf.h> 48 #include <sys/file.h> 49 #include <sys/proc.h> 50 #include <sys/devconf.h> 51 #include <sys/ioctl.h> 52 #include <sys/syslog.h> 53 #include <sys/signalvar.h> 54 55 #include <machine/cpu.h> 56 #include <machine/pcb.h> 57 #include <machine/trap.h> 58 #include <machine/clock.h> 59 #include <machine/specialreg.h> 60 61 #include <i386/isa/icu.h> 62 #include <i386/isa/isa_device.h> 63 #include <i386/isa/isa.h> 64 65 /* 66 * 387 and 287 Numeric Coprocessor Extension (NPX) Driver. 67 */ 68 69 #ifdef __GNUC__ 70 71 #define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr))) 72 #define fnclex() __asm("fnclex") 73 #define fninit() __asm("fninit") 74 #define fnop() __asm("fnop") 75 #define fnsave(addr) __asm("fnsave %0" : "=m" (*(addr))) 76 #define fnstcw(addr) __asm("fnstcw %0" : "=m" (*(addr))) 77 #define fnstsw(addr) __asm("fnstsw %0" : "=m" (*(addr))) 78 #define fp_divide_by_0() __asm("fldz; fld1; fdiv %st,%st(1); fnop") 79 #define frstor(addr) __asm("frstor %0" : : "m" (*(addr))) 80 #define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \ 81 : : "n" (CR0_TS) : "ax") 82 #define stop_emulating() __asm("clts") 83 84 #else /* not __GNUC__ */ 85 86 void fldcw __P((caddr_t addr)); 87 void fnclex __P((void)); 88 void fninit __P((void)); 89 void fnop __P((void)); 90 void fnsave __P((caddr_t addr)); 91 void fnstcw __P((caddr_t addr)); 92 void fnstsw __P((caddr_t addr)); 93 void fp_divide_by_0 __P((void)); 94 void frstor __P((caddr_t addr)); 95 void start_emulating __P((void)); 96 void stop_emulating __P((void)); 97 98 #endif /* __GNUC__ */ 99 100 typedef u_char bool_t; 101 102 static int npxattach __P((struct isa_device *dvp)); 103 static int npxprobe __P((struct isa_device *dvp)); 104 static int npxprobe1 __P((struct isa_device *dvp)); 105 106 struct isa_driver npxdriver = { 107 npxprobe, npxattach, "npx", 108 }; 109 110 int hw_float; /* XXX currently just alias for npx_exists */ 111 112 SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint, 113 CTLFLAG_RD, &hw_float, 0, 114 "Floatingpoint instructions executed in hardware"); 115 116 static u_int npx0_imask = SWI_CLOCK_MASK; 117 struct proc *npxproc; 118 119 static bool_t npx_ex16; 120 static bool_t npx_exists; 121 static struct gate_descriptor npx_idt_probeintr; 122 static int npx_intrno; 123 static volatile u_int npx_intrs_while_probing; 124 static bool_t npx_irq13; 125 static volatile u_int npx_traps_while_probing; 126 127 /* 128 * Special interrupt handlers. Someday intr0-intr15 will be used to count 129 * interrupts. We'll still need a special exception 16 handler. The busy 130 * latch stuff in probeintr() can be moved to npxprobe(). 131 */ 132 inthand_t probeintr; 133 asm 134 (" 135 .text 136 _probeintr: 137 ss 138 incl _npx_intrs_while_probing 139 pushl %eax 140 movb $0x20,%al # EOI (asm in strings loses cpp features) 141 outb %al,$0xa0 # IO_ICU2 142 outb %al,$0x20 # IO_ICU1 143 movb $0,%al 144 outb %al,$0xf0 # clear BUSY# latch 145 popl %eax 146 iret 147 "); 148 149 inthand_t probetrap; 150 asm 151 (" 152 .text 153 _probetrap: 154 ss 155 incl _npx_traps_while_probing 156 fnclex 157 iret 158 "); 159 160 static struct kern_devconf kdc_npx[NNPX] = { { 161 0, 0, 0, /* filled in by dev_attach */ 162 "npx", 0, { MDDT_ISA, 0 }, 163 isa_generic_externalize, 0, 0, ISA_EXTERNALLEN, 164 &kdc_isa0, /* parent */ 165 0, /* parentdata */ 166 DC_UNCONFIGURED, /* state */ 167 "Floating-point unit", 168 DC_CLS_MISC /* class */ 169 } }; 170 171 static inline void 172 npx_registerdev(struct isa_device *id) 173 { 174 int unit; 175 176 unit = id->id_unit; 177 if (unit != 0) 178 kdc_npx[unit] = kdc_npx[0]; 179 kdc_npx[unit].kdc_unit = unit; 180 kdc_npx[unit].kdc_isa = id; 181 dev_attach(&kdc_npx[unit]); 182 } 183 184 /* 185 * Probe routine. Initialize cr0 to give correct behaviour for [f]wait 186 * whether the device exists or not (XXX should be elsewhere). Set flags 187 * to tell npxattach() what to do. Modify device struct if npx doesn't 188 * need to use interrupts. Return 1 if device exists. 189 */ 190 static int 191 npxprobe(dvp) 192 struct isa_device *dvp; 193 { 194 int result; 195 u_long save_eflags; 196 u_char save_icu1_mask; 197 u_char save_icu2_mask; 198 struct gate_descriptor save_idt_npxintr; 199 struct gate_descriptor save_idt_npxtrap; 200 /* 201 * This routine is now just a wrapper for npxprobe1(), to install 202 * special npx interrupt and trap handlers, to enable npx interrupts 203 * and to disable other interrupts. Someday isa_configure() will 204 * install suitable handlers and run with interrupts enabled so we 205 * won't need to do so much here. 206 */ 207 npx_registerdev(dvp); 208 npx_intrno = NRSVIDT + ffs(dvp->id_irq) - 1; 209 save_eflags = read_eflags(); 210 disable_intr(); 211 save_icu1_mask = inb(IO_ICU1 + 1); 212 save_icu2_mask = inb(IO_ICU2 + 1); 213 save_idt_npxintr = idt[npx_intrno]; 214 save_idt_npxtrap = idt[16]; 215 outb(IO_ICU1 + 1, ~(IRQ_SLAVE | dvp->id_irq)); 216 outb(IO_ICU2 + 1, ~(dvp->id_irq >> 8)); 217 setidt(16, probetrap, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 218 setidt(npx_intrno, probeintr, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 219 npx_idt_probeintr = idt[npx_intrno]; 220 enable_intr(); 221 result = npxprobe1(dvp); 222 disable_intr(); 223 outb(IO_ICU1 + 1, save_icu1_mask); 224 outb(IO_ICU2 + 1, save_icu2_mask); 225 idt[npx_intrno] = save_idt_npxintr; 226 idt[16] = save_idt_npxtrap; 227 write_eflags(save_eflags); 228 return (result); 229 } 230 231 static int 232 npxprobe1(dvp) 233 struct isa_device *dvp; 234 { 235 u_short control; 236 u_short status; 237 238 /* 239 * Partially reset the coprocessor, if any. Some BIOS's don't reset 240 * it after a warm boot. 241 */ 242 outb(0xf1, 0); /* full reset on some systems, NOP on others */ 243 outb(0xf0, 0); /* clear BUSY# latch */ 244 /* 245 * Prepare to trap all ESC (i.e., NPX) instructions and all WAIT 246 * instructions. We must set the CR0_MP bit and use the CR0_TS 247 * bit to control the trap, because setting the CR0_EM bit does 248 * not cause WAIT instructions to trap. It's important to trap 249 * WAIT instructions - otherwise the "wait" variants of no-wait 250 * control instructions would degenerate to the "no-wait" variants 251 * after FP context switches but work correctly otherwise. It's 252 * particularly important to trap WAITs when there is no NPX - 253 * otherwise the "wait" variants would always degenerate. 254 * 255 * Try setting CR0_NE to get correct error reporting on 486DX's. 256 * Setting it should fail or do nothing on lesser processors. 257 */ 258 load_cr0(rcr0() | CR0_MP | CR0_NE); 259 /* 260 * But don't trap while we're probing. 261 */ 262 stop_emulating(); 263 /* 264 * Finish resetting the coprocessor, if any. If there is an error 265 * pending, then we may get a bogus IRQ13, but probeintr() will handle 266 * it OK. Bogus halts have never been observed, but we enabled 267 * IRQ13 and cleared the BUSY# latch early to handle them anyway. 268 */ 269 fninit(); 270 /* 271 * Don't use fwait here because it might hang. 272 * Don't use fnop here because it usually hangs if there is no FPU. 273 */ 274 DELAY(1000); /* wait for any IRQ13 */ 275 #ifdef DIAGNOSTIC 276 if (npx_intrs_while_probing != 0) 277 printf("fninit caused %u bogus npx interrupt(s)\n", 278 npx_intrs_while_probing); 279 if (npx_traps_while_probing != 0) 280 printf("fninit caused %u bogus npx trap(s)\n", 281 npx_traps_while_probing); 282 #endif 283 /* 284 * Check for a status of mostly zero. 285 */ 286 status = 0x5a5a; 287 fnstsw(&status); 288 if ((status & 0xb8ff) == 0) { 289 /* 290 * Good, now check for a proper control word. 291 */ 292 control = 0x5a5a; 293 fnstcw(&control); 294 if ((control & 0x1f3f) == 0x033f) { 295 hw_float = npx_exists = 1; 296 /* 297 * We have an npx, now divide by 0 to see if exception 298 * 16 works. 299 */ 300 control &= ~(1 << 2); /* enable divide by 0 trap */ 301 fldcw(&control); 302 npx_traps_while_probing = npx_intrs_while_probing = 0; 303 fp_divide_by_0(); 304 if (npx_traps_while_probing != 0) { 305 /* 306 * Good, exception 16 works. 307 */ 308 npx_ex16 = 1; 309 dvp->id_irq = 0; /* zap the interrupt */ 310 /* 311 * special return value to flag that we do not 312 * actually use any I/O registers 313 */ 314 return (-1); 315 } 316 if (npx_intrs_while_probing != 0) { 317 /* 318 * Bad, we are stuck with IRQ13. 319 */ 320 npx_irq13 = 1; 321 /* 322 * npxattach would be too late to set npx0_imask. 323 */ 324 npx0_imask |= dvp->id_irq; 325 return (IO_NPXSIZE); 326 } 327 /* 328 * Worse, even IRQ13 is broken. Use emulator. 329 */ 330 } 331 } 332 /* 333 * Probe failed, but we want to get to npxattach to initialize the 334 * emulator and say that it has been installed. XXX handle devices 335 * that aren't really devices better. 336 */ 337 dvp->id_irq = 0; 338 /* 339 * special return value to flag that we do not 340 * actually use any I/O registers 341 */ 342 return (-1); 343 } 344 345 /* 346 * Attach routine - announce which it is, and wire into system 347 */ 348 int 349 npxattach(dvp) 350 struct isa_device *dvp; 351 { 352 if (npx_ex16) 353 printf("npx%d: INT 16 interface\n", dvp->id_unit); 354 else if (npx_irq13) 355 ; /* higher level has printed "irq 13" */ 356 #if defined(MATH_EMULATE) || defined(GPL_MATH_EMULATE) 357 else if (npx_exists) { 358 printf("npx%d: error reporting broken; using 387 emulator\n", 359 dvp->id_unit); 360 npx_exists = 0; 361 } else 362 printf("npx%d: 387 emulator\n",dvp->id_unit); 363 #else 364 else 365 printf("npx%d: no 387 emulator in kernel!\n", dvp->id_unit); 366 #endif 367 npxinit(__INITIAL_NPXCW__); 368 if (npx_exists) { 369 kdc_npx[dvp->id_unit].kdc_state = DC_BUSY; 370 } 371 return (1); /* XXX unused */ 372 } 373 374 /* 375 * Initialize floating point unit. 376 */ 377 void 378 npxinit(control) 379 u_short control; 380 { 381 struct save87 dummy; 382 383 if (!npx_exists) 384 return; 385 /* 386 * fninit has the same h/w bugs as fnsave. Use the detoxified 387 * fnsave to throw away any junk in the fpu. npxsave() initializes 388 * the fpu and sets npxproc = NULL as important side effects. 389 */ 390 npxsave(&dummy); 391 stop_emulating(); 392 fldcw(&control); 393 if (curpcb != NULL) 394 fnsave(&curpcb->pcb_savefpu); 395 start_emulating(); 396 } 397 398 /* 399 * Free coprocessor (if we have it). 400 */ 401 void 402 npxexit(p) 403 struct proc *p; 404 { 405 406 if (p == npxproc) 407 npxsave(&curpcb->pcb_savefpu); 408 if (npx_exists) { 409 u_int masked_exceptions; 410 411 masked_exceptions = curpcb->pcb_savefpu.sv_env.en_cw 412 & curpcb->pcb_savefpu.sv_env.en_sw & 0x7f; 413 /* 414 * Overflow, divde by 0, and invalid operand would have 415 * caused a trap in 1.1.5. 416 */ 417 if (masked_exceptions & 0x0d) 418 log(LOG_ERR, 419 "pid %d (%s) exited with masked floating point exceptions 0x%02x\n", 420 p->p_pid, p->p_comm, masked_exceptions); 421 } 422 } 423 424 /* 425 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE. 426 * 427 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now 428 * depend on longjmp() restoring a usable state. Restoring the state 429 * or examining it might fail if we didn't clear exceptions. 430 * 431 * XXX there is no standard way to tell SIGFPE handlers about the error 432 * state. The old interface: 433 * 434 * void handler(int sig, int code, struct sigcontext *scp); 435 * 436 * is broken because it is non-ANSI and because the FP state is not in 437 * struct sigcontext. 438 * 439 * XXX the FP state is not preserved across signal handlers. So signal 440 * handlers cannot afford to do FP unless they preserve the state or 441 * longjmp() out. Both preserving the state and longjmp()ing may be 442 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable 443 * solution for signals other than SIGFPE. 444 */ 445 void 446 npxintr(unit) 447 int unit; 448 { 449 int code; 450 struct intrframe *frame; 451 452 if (npxproc == NULL || !npx_exists) { 453 printf("npxintr: npxproc = %p, curproc = %p, npx_exists = %d\n", 454 npxproc, curproc, npx_exists); 455 panic("npxintr from nowhere"); 456 } 457 if (npxproc != curproc) { 458 printf("npxintr: npxproc = %p, curproc = %p, npx_exists = %d\n", 459 npxproc, curproc, npx_exists); 460 panic("npxintr from non-current process"); 461 } 462 463 outb(0xf0, 0); 464 fnstsw(&curpcb->pcb_savefpu.sv_ex_sw); 465 fnclex(); 466 fnop(); 467 468 /* 469 * Pass exception to process. 470 */ 471 frame = (struct intrframe *)&unit; /* XXX */ 472 if (ISPL(frame->if_cs) == SEL_UPL) { 473 /* 474 * Interrupt is essentially a trap, so we can afford to call 475 * the SIGFPE handler (if any) as soon as the interrupt 476 * returns. 477 * 478 * XXX little or nothing is gained from this, and plenty is 479 * lost - the interrupt frame has to contain the trap frame 480 * (this is otherwise only necessary for the rescheduling trap 481 * in doreti, and the frame for that could easily be set up 482 * just before it is used). 483 */ 484 curproc->p_md.md_regs = &frame->if_es; 485 #ifdef notyet 486 /* 487 * Encode the appropriate code for detailed information on 488 * this exception. 489 */ 490 code = XXX_ENCODE(curpcb->pcb_savefpu.sv_ex_sw); 491 #else 492 code = 0; /* XXX */ 493 #endif 494 trapsignal(curproc, SIGFPE, code); 495 } else { 496 /* 497 * Nested interrupt. These losers occur when: 498 * o an IRQ13 is bogusly generated at a bogus time, e.g.: 499 * o immediately after an fnsave or frstor of an 500 * error state. 501 * o a couple of 386 instructions after 502 * "fstpl _memvar" causes a stack overflow. 503 * These are especially nasty when combined with a 504 * trace trap. 505 * o an IRQ13 occurs at the same time as another higher- 506 * priority interrupt. 507 * 508 * Treat them like a true async interrupt. 509 */ 510 psignal(curproc, SIGFPE); 511 } 512 } 513 514 /* 515 * Implement device not available (DNA) exception 516 * 517 * It would be better to switch FP context here (if curproc != npxproc) 518 * and not necessarily for every context switch, but it is too hard to 519 * access foreign pcb's. 520 */ 521 int 522 npxdna() 523 { 524 if (!npx_exists) 525 return (0); 526 if (npxproc != NULL) { 527 printf("npxdna: npxproc = %p, curproc = %p\n", 528 npxproc, curproc); 529 panic("npxdna"); 530 } 531 stop_emulating(); 532 /* 533 * Record new context early in case frstor causes an IRQ13. 534 */ 535 npxproc = curproc; 536 curpcb->pcb_savefpu.sv_ex_sw = 0; 537 /* 538 * The following frstor may cause an IRQ13 when the state being 539 * restored has a pending error. The error will appear to have been 540 * triggered by the current (npx) user instruction even when that 541 * instruction is a no-wait instruction that should not trigger an 542 * error (e.g., fnclex). On at least one 486 system all of the 543 * no-wait instructions are broken the same as frstor, so our 544 * treatment does not amplify the breakage. On at least one 545 * 386/Cyrix 387 system, fnclex works correctly while frstor and 546 * fnsave are broken, so our treatment breaks fnclex if it is the 547 * first FPU instruction after a context switch. 548 */ 549 frstor(&curpcb->pcb_savefpu); 550 551 return (1); 552 } 553 554 /* 555 * Wrapper for fnsave instruction to handle h/w bugs. If there is an error 556 * pending, then fnsave generates a bogus IRQ13 on some systems. Force 557 * any IRQ13 to be handled immediately, and then ignore it. This routine is 558 * often called at splhigh so it must not use many system services. In 559 * particular, it's much easier to install a special handler than to 560 * guarantee that it's safe to use npxintr() and its supporting code. 561 */ 562 void 563 npxsave(addr) 564 struct save87 *addr; 565 { 566 u_char icu1_mask; 567 u_char icu2_mask; 568 u_char old_icu1_mask; 569 u_char old_icu2_mask; 570 struct gate_descriptor save_idt_npxintr; 571 572 disable_intr(); 573 old_icu1_mask = inb(IO_ICU1 + 1); 574 old_icu2_mask = inb(IO_ICU2 + 1); 575 save_idt_npxintr = idt[npx_intrno]; 576 outb(IO_ICU1 + 1, old_icu1_mask & ~(IRQ_SLAVE | npx0_imask)); 577 outb(IO_ICU2 + 1, old_icu2_mask & ~(npx0_imask >> 8)); 578 idt[npx_intrno] = npx_idt_probeintr; 579 enable_intr(); 580 stop_emulating(); 581 fnsave(addr); 582 fnop(); 583 start_emulating(); 584 npxproc = NULL; 585 disable_intr(); 586 icu1_mask = inb(IO_ICU1 + 1); /* masks may have changed */ 587 icu2_mask = inb(IO_ICU2 + 1); 588 outb(IO_ICU1 + 1, 589 (icu1_mask & ~npx0_imask) | (old_icu1_mask & npx0_imask)); 590 outb(IO_ICU2 + 1, 591 (icu2_mask & ~(npx0_imask >> 8)) 592 | (old_icu2_mask & (npx0_imask >> 8))); 593 idt[npx_intrno] = save_idt_npxintr; 594 enable_intr(); /* back to usual state */ 595 } 596 597 #endif /* NNPX > 0 */ 598