1 /*- 2 * Copyright (c) 1990 William Jolitz. 3 * Copyright (c) 1991 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by the University of 17 * California, Berkeley and its contributors. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 35 * $FreeBSD$ 36 */ 37 38 #include "opt_debug_npx.h" 39 #include "opt_math_emulate.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/bus.h> 44 #include <sys/ipl.h> 45 #include <sys/kernel.h> 46 #include <sys/malloc.h> 47 #include <sys/module.h> 48 #include <sys/sysctl.h> 49 #include <sys/proc.h> 50 #include <sys/mutex.h> 51 #include <machine/bus.h> 52 #include <sys/rman.h> 53 #ifdef NPX_DEBUG 54 #include <sys/syslog.h> 55 #endif 56 #include <sys/signalvar.h> 57 58 #ifndef SMP 59 #include <machine/asmacros.h> 60 #endif 61 #include <machine/cputypes.h> 62 #include <machine/frame.h> 63 #include <machine/md_var.h> 64 #include <machine/pcb.h> 65 #include <machine/psl.h> 66 #ifndef SMP 67 #include <machine/clock.h> 68 #endif 69 #include <machine/resource.h> 70 #include <machine/specialreg.h> 71 #include <machine/segments.h> 72 73 #ifndef SMP 74 #include <i386/isa/icu.h> 75 #include <i386/isa/intr_machdep.h> 76 #include <i386/isa/isa.h> 77 #endif 78 #include <isa/isavar.h> 79 80 /* 81 * 387 and 287 Numeric Coprocessor Extension (NPX) Driver. 82 */ 83 84 /* Configuration flags. */ 85 #define NPX_DISABLE_I586_OPTIMIZED_BCOPY (1 << 0) 86 #define NPX_DISABLE_I586_OPTIMIZED_BZERO (1 << 1) 87 #define NPX_DISABLE_I586_OPTIMIZED_COPYIO (1 << 2) 88 #define NPX_PREFER_EMULATOR (1 << 3) 89 90 #ifdef __GNUC__ 91 92 #define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr))) 93 #define fnclex() __asm("fnclex") 94 #define fninit() __asm("fninit") 95 #define fnop() __asm("fnop") 96 #define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr))) 97 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 98 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr))) 99 #define fp_divide_by_0() __asm("fldz; fld1; fdiv %st,%st(1); fnop") 100 #define frstor(addr) __asm("frstor %0" : : "m" (*(addr))) 101 #define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \ 102 : : "n" (CR0_TS) : "ax") 103 #define stop_emulating() __asm("clts") 104 105 #else /* not __GNUC__ */ 106 107 void fldcw __P((caddr_t addr)); 108 void fnclex __P((void)); 109 void fninit __P((void)); 110 void fnop __P((void)); 111 void fnsave __P((caddr_t addr)); 112 void fnstcw __P((caddr_t addr)); 113 void fnstsw __P((caddr_t addr)); 114 void fp_divide_by_0 __P((void)); 115 void frstor __P((caddr_t addr)); 116 void start_emulating __P((void)); 117 void stop_emulating __P((void)); 118 119 #endif /* __GNUC__ */ 120 121 typedef u_char bool_t; 122 123 static int npx_attach __P((device_t dev)); 124 void npx_intr __P((void *)); 125 static void npx_identify __P((driver_t *driver, device_t parent)); 126 static int npx_probe __P((device_t dev)); 127 static int npx_probe1 __P((device_t dev)); 128 #ifdef I586_CPU 129 static long timezero __P((const char *funcname, 130 void (*func)(void *buf, size_t len))); 131 #endif /* I586_CPU */ 132 133 int hw_float; /* XXX currently just alias for npx_exists */ 134 135 SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint, 136 CTLFLAG_RD, &hw_float, 0, 137 "Floatingpoint instructions executed in hardware"); 138 139 #ifndef SMP 140 static u_int npx0_imask = 0; 141 static struct gate_descriptor npx_idt_probeintr; 142 static int npx_intrno; 143 static volatile u_int npx_intrs_while_probing; 144 static volatile u_int npx_traps_while_probing; 145 #endif 146 147 static bool_t npx_ex16; 148 static bool_t npx_exists; 149 static bool_t npx_irq13; 150 static int npx_irq; /* irq number */ 151 152 #ifndef SMP 153 /* 154 * Special interrupt handlers. Someday intr0-intr15 will be used to count 155 * interrupts. We'll still need a special exception 16 handler. The busy 156 * latch stuff in probeintr() can be moved to npxprobe(). 157 */ 158 inthand_t probeintr; 159 __asm(" \n\ 160 .text \n\ 161 .p2align 2,0x90 \n\ 162 .type " __XSTRING(CNAME(probeintr)) ",@function \n\ 163 " __XSTRING(CNAME(probeintr)) ": \n\ 164 ss \n\ 165 incl " __XSTRING(CNAME(npx_intrs_while_probing)) " \n\ 166 pushl %eax \n\ 167 movb $0x20,%al # EOI (asm in strings loses cpp features) \n\ 168 outb %al,$0xa0 # IO_ICU2 \n\ 169 outb %al,$0x20 # IO_ICU1 \n\ 170 movb $0,%al \n\ 171 outb %al,$0xf0 # clear BUSY# latch \n\ 172 popl %eax \n\ 173 iret \n\ 174 "); 175 176 inthand_t probetrap; 177 __asm(" \n\ 178 .text \n\ 179 .p2align 2,0x90 \n\ 180 .type " __XSTRING(CNAME(probetrap)) ",@function \n\ 181 " __XSTRING(CNAME(probetrap)) ": \n\ 182 ss \n\ 183 incl " __XSTRING(CNAME(npx_traps_while_probing)) " \n\ 184 fnclex \n\ 185 iret \n\ 186 "); 187 #endif /* SMP */ 188 189 /* 190 * Identify routine. Create a connection point on our parent for probing. 191 */ 192 static void 193 npx_identify(driver, parent) 194 driver_t *driver; 195 device_t parent; 196 { 197 device_t child; 198 199 child = BUS_ADD_CHILD(parent, 0, "npx", 0); 200 if (child == NULL) 201 panic("npx_identify"); 202 } 203 204 /* 205 * Probe routine. Initialize cr0 to give correct behaviour for [f]wait 206 * whether the device exists or not (XXX should be elsewhere). Set flags 207 * to tell npxattach() what to do. Modify device struct if npx doesn't 208 * need to use interrupts. Return 1 if device exists. 209 */ 210 static int 211 npx_probe(dev) 212 device_t dev; 213 { 214 #ifdef SMP 215 216 if (resource_int_value("npx", 0, "irq", &npx_irq) != 0) 217 npx_irq = 13; 218 return npx_probe1(dev); 219 220 #else /* SMP */ 221 222 int result; 223 u_long save_eflags; 224 u_char save_icu1_mask; 225 u_char save_icu2_mask; 226 struct gate_descriptor save_idt_npxintr; 227 struct gate_descriptor save_idt_npxtrap; 228 /* 229 * This routine is now just a wrapper for npxprobe1(), to install 230 * special npx interrupt and trap handlers, to enable npx interrupts 231 * and to disable other interrupts. Someday isa_configure() will 232 * install suitable handlers and run with interrupts enabled so we 233 * won't need to do so much here. 234 */ 235 if (resource_int_value("npx", 0, "irq", &npx_irq) != 0) 236 npx_irq = 13; 237 npx_intrno = NRSVIDT + npx_irq; 238 save_eflags = read_eflags(); 239 disable_intr(); 240 save_icu1_mask = inb(IO_ICU1 + 1); 241 save_icu2_mask = inb(IO_ICU2 + 1); 242 save_idt_npxintr = idt[npx_intrno]; 243 save_idt_npxtrap = idt[16]; 244 outb(IO_ICU1 + 1, ~IRQ_SLAVE); 245 outb(IO_ICU2 + 1, ~(1 << (npx_irq - 8))); 246 setidt(16, probetrap, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 247 setidt(npx_intrno, probeintr, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 248 npx_idt_probeintr = idt[npx_intrno]; 249 250 /* 251 * XXX This looks highly bogus, but it appears that npc_probe1 252 * needs interrupts enabled. Does this make any difference 253 * here? 254 */ 255 enable_intr(); 256 result = npx_probe1(dev); 257 disable_intr(); 258 outb(IO_ICU1 + 1, save_icu1_mask); 259 outb(IO_ICU2 + 1, save_icu2_mask); 260 idt[npx_intrno] = save_idt_npxintr; 261 idt[16] = save_idt_npxtrap; 262 write_eflags(save_eflags); 263 return (result); 264 265 #endif /* SMP */ 266 } 267 268 static int 269 npx_probe1(dev) 270 device_t dev; 271 { 272 #ifndef SMP 273 u_short control; 274 u_short status; 275 #endif 276 277 /* 278 * Partially reset the coprocessor, if any. Some BIOS's don't reset 279 * it after a warm boot. 280 */ 281 outb(0xf1, 0); /* full reset on some systems, NOP on others */ 282 outb(0xf0, 0); /* clear BUSY# latch */ 283 /* 284 * Prepare to trap all ESC (i.e., NPX) instructions and all WAIT 285 * instructions. We must set the CR0_MP bit and use the CR0_TS 286 * bit to control the trap, because setting the CR0_EM bit does 287 * not cause WAIT instructions to trap. It's important to trap 288 * WAIT instructions - otherwise the "wait" variants of no-wait 289 * control instructions would degenerate to the "no-wait" variants 290 * after FP context switches but work correctly otherwise. It's 291 * particularly important to trap WAITs when there is no NPX - 292 * otherwise the "wait" variants would always degenerate. 293 * 294 * Try setting CR0_NE to get correct error reporting on 486DX's. 295 * Setting it should fail or do nothing on lesser processors. 296 */ 297 load_cr0(rcr0() | CR0_MP | CR0_NE); 298 /* 299 * But don't trap while we're probing. 300 */ 301 stop_emulating(); 302 /* 303 * Finish resetting the coprocessor, if any. If there is an error 304 * pending, then we may get a bogus IRQ13, but probeintr() will handle 305 * it OK. Bogus halts have never been observed, but we enabled 306 * IRQ13 and cleared the BUSY# latch early to handle them anyway. 307 */ 308 fninit(); 309 310 #ifdef SMP 311 /* 312 * Exception 16 MUST work for SMP. 313 */ 314 npx_irq13 = 0; 315 npx_ex16 = hw_float = npx_exists = 1; 316 device_set_desc(dev, "math processor"); 317 return (0); 318 319 #else /* !SMP */ 320 device_set_desc(dev, "math processor"); 321 322 /* 323 * Don't use fwait here because it might hang. 324 * Don't use fnop here because it usually hangs if there is no FPU. 325 */ 326 DELAY(1000); /* wait for any IRQ13 */ 327 #ifdef DIAGNOSTIC 328 if (npx_intrs_while_probing != 0) 329 printf("fninit caused %u bogus npx interrupt(s)\n", 330 npx_intrs_while_probing); 331 if (npx_traps_while_probing != 0) 332 printf("fninit caused %u bogus npx trap(s)\n", 333 npx_traps_while_probing); 334 #endif 335 /* 336 * Check for a status of mostly zero. 337 */ 338 status = 0x5a5a; 339 fnstsw(&status); 340 if ((status & 0xb8ff) == 0) { 341 /* 342 * Good, now check for a proper control word. 343 */ 344 control = 0x5a5a; 345 fnstcw(&control); 346 if ((control & 0x1f3f) == 0x033f) { 347 hw_float = npx_exists = 1; 348 /* 349 * We have an npx, now divide by 0 to see if exception 350 * 16 works. 351 */ 352 control &= ~(1 << 2); /* enable divide by 0 trap */ 353 fldcw(&control); 354 npx_traps_while_probing = npx_intrs_while_probing = 0; 355 fp_divide_by_0(); 356 if (npx_traps_while_probing != 0) { 357 /* 358 * Good, exception 16 works. 359 */ 360 npx_ex16 = 1; 361 return (0); 362 } 363 if (npx_intrs_while_probing != 0) { 364 int rid; 365 struct resource *r; 366 void *intr; 367 /* 368 * Bad, we are stuck with IRQ13. 369 */ 370 npx_irq13 = 1; 371 /* 372 * npxattach would be too late to set npx0_imask 373 */ 374 npx0_imask |= (1 << npx_irq); 375 376 /* 377 * We allocate these resources permanently, 378 * so there is no need to keep track of them. 379 */ 380 rid = 0; 381 r = bus_alloc_resource(dev, SYS_RES_IOPORT, 382 &rid, IO_NPX, IO_NPX, 383 IO_NPXSIZE, RF_ACTIVE); 384 if (r == 0) 385 panic("npx: can't get ports"); 386 rid = 0; 387 r = bus_alloc_resource(dev, SYS_RES_IRQ, 388 &rid, npx_irq, npx_irq, 389 1, RF_ACTIVE); 390 if (r == 0) 391 panic("npx: can't get IRQ"); 392 BUS_SETUP_INTR(device_get_parent(dev), 393 dev, r, 394 INTR_TYPE_MISC | INTR_MPSAFE, 395 npx_intr, 0, &intr); 396 if (intr == 0) 397 panic("npx: can't create intr"); 398 399 return (0); 400 } 401 /* 402 * Worse, even IRQ13 is broken. Use emulator. 403 */ 404 } 405 } 406 /* 407 * Probe failed, but we want to get to npxattach to initialize the 408 * emulator and say that it has been installed. XXX handle devices 409 * that aren't really devices better. 410 */ 411 return (0); 412 #endif /* SMP */ 413 } 414 415 /* 416 * Attach routine - announce which it is, and wire into system 417 */ 418 int 419 npx_attach(dev) 420 device_t dev; 421 { 422 int flags; 423 424 if (resource_int_value("npx", 0, "flags", &flags) != 0) 425 flags = 0; 426 427 if (flags) 428 device_printf(dev, "flags 0x%x ", flags); 429 if (npx_irq13) { 430 device_printf(dev, "using IRQ 13 interface\n"); 431 } else { 432 #if defined(MATH_EMULATE) || defined(GPL_MATH_EMULATE) 433 if (npx_ex16) { 434 if (!(flags & NPX_PREFER_EMULATOR)) 435 device_printf(dev, "INT 16 interface\n"); 436 else { 437 device_printf(dev, "FPU exists, but flags request " 438 "emulator\n"); 439 hw_float = npx_exists = 0; 440 } 441 } else if (npx_exists) { 442 device_printf(dev, "error reporting broken; using 387 emulator\n"); 443 hw_float = npx_exists = 0; 444 } else 445 device_printf(dev, "387 emulator\n"); 446 #else 447 if (npx_ex16) { 448 device_printf(dev, "INT 16 interface\n"); 449 if (flags & NPX_PREFER_EMULATOR) { 450 device_printf(dev, "emulator requested, but none compiled " 451 "into kernel, using FPU\n"); 452 } 453 } else 454 device_printf(dev, "no 387 emulator in kernel and no FPU!\n"); 455 #endif 456 } 457 npxinit(__INITIAL_NPXCW__); 458 459 #ifdef I586_CPU 460 if (cpu_class == CPUCLASS_586 && npx_ex16 && npx_exists && 461 timezero("i586_bzero()", i586_bzero) < 462 timezero("bzero()", bzero) * 4 / 5) { 463 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY)) { 464 bcopy_vector = i586_bcopy; 465 ovbcopy_vector = i586_bcopy; 466 } 467 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BZERO)) 468 bzero = i586_bzero; 469 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_COPYIO)) { 470 copyin_vector = i586_copyin; 471 copyout_vector = i586_copyout; 472 } 473 } 474 #endif 475 476 return (0); /* XXX unused */ 477 } 478 479 /* 480 * Initialize floating point unit. 481 */ 482 void 483 npxinit(control) 484 u_short control; 485 { 486 struct save87 dummy; 487 488 if (!npx_exists) 489 return; 490 /* 491 * fninit has the same h/w bugs as fnsave. Use the detoxified 492 * fnsave to throw away any junk in the fpu. npxsave() initializes 493 * the fpu and sets npxproc = NULL as important side effects. 494 */ 495 npxsave(&dummy); 496 stop_emulating(); 497 fldcw(&control); 498 if (PCPU_GET(curpcb) != NULL) 499 fnsave(&PCPU_GET(curpcb)->pcb_savefpu); 500 start_emulating(); 501 } 502 503 /* 504 * Free coprocessor (if we have it). 505 */ 506 void 507 npxexit(p) 508 struct proc *p; 509 { 510 511 if (p == PCPU_GET(npxproc)) 512 npxsave(&PCPU_GET(curpcb)->pcb_savefpu); 513 #ifdef NPX_DEBUG 514 if (npx_exists) { 515 u_int masked_exceptions; 516 517 masked_exceptions = PCPU_GET(curpcb)->pcb_savefpu.sv_env.en_cw 518 & PCPU_GET(curpcb)->pcb_savefpu.sv_env.en_sw & 0x7f; 519 /* 520 * Log exceptions that would have trapped with the old 521 * control word (overflow, divide by 0, and invalid operand). 522 */ 523 if (masked_exceptions & 0x0d) 524 log(LOG_ERR, 525 "pid %d (%s) exited with masked floating point exceptions 0x%02x\n", 526 p->p_pid, p->p_comm, masked_exceptions); 527 } 528 #endif 529 } 530 531 /* 532 * The following mechanism is used to ensure that the FPE_... value 533 * that is passed as a trapcode to the signal handler of the user 534 * process does not have more than one bit set. 535 * 536 * Multiple bits may be set if the user process modifies the control 537 * word while a status word bit is already set. While this is a sign 538 * of bad coding, we have no choise than to narrow them down to one 539 * bit, since we must not send a trapcode that is not exactly one of 540 * the FPE_ macros. 541 * 542 * The mechanism has a static table with 127 entries. Each combination 543 * of the 7 FPU status word exception bits directly translates to a 544 * position in this table, where a single FPE_... value is stored. 545 * This FPE_... value stored there is considered the "most important" 546 * of the exception bits and will be sent as the signal code. The 547 * precedence of the bits is based upon Intel Document "Numerical 548 * Applications", Chapter "Special Computational Situations". 549 * 550 * The macro to choose one of these values does these steps: 1) Throw 551 * away status word bits that cannot be masked. 2) Throw away the bits 552 * currently masked in the control word, assuming the user isn't 553 * interested in them anymore. 3) Reinsert status word bit 7 (stack 554 * fault) if it is set, which cannot be masked but must be presered. 555 * 4) Use the remaining bits to point into the trapcode table. 556 * 557 * The 6 maskable bits in order of their preference, as stated in the 558 * above referenced Intel manual: 559 * 1 Invalid operation (FP_X_INV) 560 * 1a Stack underflow 561 * 1b Stack overflow 562 * 1c Operand of unsupported format 563 * 1d SNaN operand. 564 * 2 QNaN operand (not an exception, irrelavant here) 565 * 3 Any other invalid-operation not mentioned above or zero divide 566 * (FP_X_INV, FP_X_DZ) 567 * 4 Denormal operand (FP_X_DNML) 568 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 569 * 6 Inexact result (FP_X_IMP) 570 */ 571 static char fpetable[128] = { 572 0, 573 FPE_FLTINV, /* 1 - INV */ 574 FPE_FLTUND, /* 2 - DNML */ 575 FPE_FLTINV, /* 3 - INV | DNML */ 576 FPE_FLTDIV, /* 4 - DZ */ 577 FPE_FLTINV, /* 5 - INV | DZ */ 578 FPE_FLTDIV, /* 6 - DNML | DZ */ 579 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 580 FPE_FLTOVF, /* 8 - OFL */ 581 FPE_FLTINV, /* 9 - INV | OFL */ 582 FPE_FLTUND, /* A - DNML | OFL */ 583 FPE_FLTINV, /* B - INV | DNML | OFL */ 584 FPE_FLTDIV, /* C - DZ | OFL */ 585 FPE_FLTINV, /* D - INV | DZ | OFL */ 586 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 587 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 588 FPE_FLTUND, /* 10 - UFL */ 589 FPE_FLTINV, /* 11 - INV | UFL */ 590 FPE_FLTUND, /* 12 - DNML | UFL */ 591 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 592 FPE_FLTDIV, /* 14 - DZ | UFL */ 593 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 594 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 595 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 596 FPE_FLTOVF, /* 18 - OFL | UFL */ 597 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 598 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 599 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 600 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 601 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 602 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 603 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 604 FPE_FLTRES, /* 20 - IMP */ 605 FPE_FLTINV, /* 21 - INV | IMP */ 606 FPE_FLTUND, /* 22 - DNML | IMP */ 607 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 608 FPE_FLTDIV, /* 24 - DZ | IMP */ 609 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 610 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 611 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 612 FPE_FLTOVF, /* 28 - OFL | IMP */ 613 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 614 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 615 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 616 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 617 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 618 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 619 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 620 FPE_FLTUND, /* 30 - UFL | IMP */ 621 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 622 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 623 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 624 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 625 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 626 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 627 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 628 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 629 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 630 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 631 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 632 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 633 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 634 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 635 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 636 FPE_FLTSUB, /* 40 - STK */ 637 FPE_FLTSUB, /* 41 - INV | STK */ 638 FPE_FLTUND, /* 42 - DNML | STK */ 639 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 640 FPE_FLTDIV, /* 44 - DZ | STK */ 641 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 642 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 643 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 644 FPE_FLTOVF, /* 48 - OFL | STK */ 645 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 646 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 647 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 648 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 649 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 650 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 651 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 652 FPE_FLTUND, /* 50 - UFL | STK */ 653 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 654 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 655 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 656 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 657 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 658 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 659 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 660 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 661 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 662 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 663 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 664 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 665 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 666 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 667 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 668 FPE_FLTRES, /* 60 - IMP | STK */ 669 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 670 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 671 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 672 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 673 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 674 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 675 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 676 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 677 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 678 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 679 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 680 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 681 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 682 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 683 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 684 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 685 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 686 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 687 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 688 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 689 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 690 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 691 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 692 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 693 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 694 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 695 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 696 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 697 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 698 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 699 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 700 }; 701 702 /* 703 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE. 704 * 705 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now 706 * depend on longjmp() restoring a usable state. Restoring the state 707 * or examining it might fail if we didn't clear exceptions. 708 * 709 * The error code chosen will be one of the FPE_... macros. It will be 710 * sent as the second argument to old BSD-style signal handlers and as 711 * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers. 712 * 713 * XXX the FP state is not preserved across signal handlers. So signal 714 * handlers cannot afford to do FP unless they preserve the state or 715 * longjmp() out. Both preserving the state and longjmp()ing may be 716 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable 717 * solution for signals other than SIGFPE. 718 */ 719 void 720 npx_intr(dummy) 721 void *dummy; 722 { 723 int code; 724 u_short control; 725 struct intrframe *frame; 726 727 mtx_lock(&Giant); 728 if (PCPU_GET(npxproc) == NULL || !npx_exists) { 729 printf("npxintr: npxproc = %p, curproc = %p, npx_exists = %d\n", 730 PCPU_GET(npxproc), curproc, npx_exists); 731 panic("npxintr from nowhere"); 732 } 733 if (PCPU_GET(npxproc) != curproc) { 734 printf("npxintr: npxproc = %p, curproc = %p, npx_exists = %d\n", 735 PCPU_GET(npxproc), curproc, npx_exists); 736 panic("npxintr from non-current process"); 737 } 738 739 outb(0xf0, 0); 740 fnstsw(&PCPU_GET(curpcb)->pcb_savefpu.sv_ex_sw); 741 fnstcw(&control); 742 fnclex(); 743 744 /* 745 * Pass exception to process. 746 */ 747 frame = (struct intrframe *)&dummy; /* XXX */ 748 if ((ISPL(frame->if_cs) == SEL_UPL) || (frame->if_eflags & PSL_VM)) { 749 /* 750 * Interrupt is essentially a trap, so we can afford to call 751 * the SIGFPE handler (if any) as soon as the interrupt 752 * returns. 753 * 754 * XXX little or nothing is gained from this, and plenty is 755 * lost - the interrupt frame has to contain the trap frame 756 * (this is otherwise only necessary for the rescheduling trap 757 * in doreti, and the frame for that could easily be set up 758 * just before it is used). 759 */ 760 curproc->p_md.md_regs = INTR_TO_TRAPFRAME(frame); 761 /* 762 * Encode the appropriate code for detailed information on 763 * this exception. 764 */ 765 code = 766 fpetable[(PCPU_GET(curpcb)->pcb_savefpu.sv_ex_sw & ~control & 0x3f) | 767 (PCPU_GET(curpcb)->pcb_savefpu.sv_ex_sw & 0x40)]; 768 trapsignal(curproc, SIGFPE, code); 769 } else { 770 /* 771 * Nested interrupt. These losers occur when: 772 * o an IRQ13 is bogusly generated at a bogus time, e.g.: 773 * o immediately after an fnsave or frstor of an 774 * error state. 775 * o a couple of 386 instructions after 776 * "fstpl _memvar" causes a stack overflow. 777 * These are especially nasty when combined with a 778 * trace trap. 779 * o an IRQ13 occurs at the same time as another higher- 780 * priority interrupt. 781 * 782 * Treat them like a true async interrupt. 783 */ 784 psignal(curproc, SIGFPE); 785 } 786 mtx_unlock(&Giant); 787 } 788 789 /* 790 * Implement device not available (DNA) exception 791 * 792 * It would be better to switch FP context here (if curproc != npxproc) 793 * and not necessarily for every context switch, but it is too hard to 794 * access foreign pcb's. 795 */ 796 int 797 npxdna() 798 { 799 int s; 800 801 if (!npx_exists) 802 return (0); 803 if (PCPU_GET(npxproc) != NULL) { 804 printf("npxdna: npxproc = %p, curproc = %p\n", 805 PCPU_GET(npxproc), curproc); 806 panic("npxdna"); 807 } 808 s = save_intr(); 809 disable_intr(); 810 stop_emulating(); 811 /* 812 * Record new context early in case frstor causes an IRQ13. 813 */ 814 PCPU_SET(npxproc, CURPROC); 815 PCPU_GET(curpcb)->pcb_savefpu.sv_ex_sw = 0; 816 /* 817 * The following frstor may cause an IRQ13 when the state being 818 * restored has a pending error. The error will appear to have been 819 * triggered by the current (npx) user instruction even when that 820 * instruction is a no-wait instruction that should not trigger an 821 * error (e.g., fnclex). On at least one 486 system all of the 822 * no-wait instructions are broken the same as frstor, so our 823 * treatment does not amplify the breakage. On at least one 824 * 386/Cyrix 387 system, fnclex works correctly while frstor and 825 * fnsave are broken, so our treatment breaks fnclex if it is the 826 * first FPU instruction after a context switch. 827 */ 828 frstor(&PCPU_GET(curpcb)->pcb_savefpu); 829 restore_intr(s); 830 831 return (1); 832 } 833 834 /* 835 * Wrapper for fnsave instruction to handle h/w bugs. If there is an error 836 * pending, then fnsave generates a bogus IRQ13 on some systems. Force 837 * any IRQ13 to be handled immediately, and then ignore it. This routine is 838 * often called at splhigh so it must not use many system services. In 839 * particular, it's much easier to install a special handler than to 840 * guarantee that it's safe to use npxintr() and its supporting code. 841 */ 842 void 843 npxsave(addr) 844 struct save87 *addr; 845 { 846 #ifdef SMP 847 848 stop_emulating(); 849 fnsave(addr); 850 /* fnop(); */ 851 start_emulating(); 852 PCPU_SET(npxproc, NULL); 853 854 #else /* SMP */ 855 856 int intrstate; 857 u_char icu1_mask; 858 u_char icu2_mask; 859 u_char old_icu1_mask; 860 u_char old_icu2_mask; 861 struct gate_descriptor save_idt_npxintr; 862 863 intrstate = save_intr(); 864 disable_intr(); 865 old_icu1_mask = inb(IO_ICU1 + 1); 866 old_icu2_mask = inb(IO_ICU2 + 1); 867 save_idt_npxintr = idt[npx_intrno]; 868 outb(IO_ICU1 + 1, old_icu1_mask & ~(IRQ_SLAVE | npx0_imask)); 869 outb(IO_ICU2 + 1, old_icu2_mask & ~(npx0_imask >> 8)); 870 idt[npx_intrno] = npx_idt_probeintr; 871 write_eflags(intrstate); 872 stop_emulating(); 873 fnsave(addr); 874 fnop(); 875 start_emulating(); 876 PCPU_SET(npxproc, NULL); 877 disable_intr(); 878 icu1_mask = inb(IO_ICU1 + 1); /* masks may have changed */ 879 icu2_mask = inb(IO_ICU2 + 1); 880 outb(IO_ICU1 + 1, 881 (icu1_mask & ~npx0_imask) | (old_icu1_mask & npx0_imask)); 882 outb(IO_ICU2 + 1, 883 (icu2_mask & ~(npx0_imask >> 8)) 884 | (old_icu2_mask & (npx0_imask >> 8))); 885 idt[npx_intrno] = save_idt_npxintr; 886 restore_intr(intrstate); /* back to previous state */ 887 888 #endif /* SMP */ 889 } 890 891 #ifdef I586_CPU 892 static long 893 timezero(funcname, func) 894 const char *funcname; 895 void (*func) __P((void *buf, size_t len)); 896 897 { 898 void *buf; 899 #define BUFSIZE 1000000 900 long usec; 901 struct timeval finish, start; 902 903 buf = malloc(BUFSIZE, M_TEMP, M_NOWAIT); 904 if (buf == NULL) 905 return (BUFSIZE); 906 microtime(&start); 907 (*func)(buf, BUFSIZE); 908 microtime(&finish); 909 usec = 1000000 * (finish.tv_sec - start.tv_sec) + 910 finish.tv_usec - start.tv_usec; 911 if (usec <= 0) 912 usec = 1; 913 if (bootverbose) 914 printf("%s bandwidth = %ld bytes/sec\n", 915 funcname, (long)(BUFSIZE * (int64_t)1000000 / usec)); 916 free(buf, M_TEMP); 917 return (usec); 918 } 919 #endif /* I586_CPU */ 920 921 static device_method_t npx_methods[] = { 922 /* Device interface */ 923 DEVMETHOD(device_identify, npx_identify), 924 DEVMETHOD(device_probe, npx_probe), 925 DEVMETHOD(device_attach, npx_attach), 926 DEVMETHOD(device_detach, bus_generic_detach), 927 DEVMETHOD(device_shutdown, bus_generic_shutdown), 928 DEVMETHOD(device_suspend, bus_generic_suspend), 929 DEVMETHOD(device_resume, bus_generic_resume), 930 931 { 0, 0 } 932 }; 933 934 static driver_t npx_driver = { 935 "npx", 936 npx_methods, 937 1, /* no softc */ 938 }; 939 940 static devclass_t npx_devclass; 941 942 /* 943 * We prefer to attach to the root nexus so that the usual case (exception 16) 944 * doesn't describe the processor as being `on isa'. 945 */ 946 DRIVER_MODULE(npx, nexus, npx_driver, npx_devclass, 0, 0); 947 948 /* 949 * This sucks up the legacy ISA support assignments from PNPBIOS. 950 */ 951 static struct isa_pnp_id npxisa_ids[] = { 952 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */ 953 { 0 } 954 }; 955 956 static int 957 npxisa_probe(device_t dev) 958 { 959 int result; 960 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, npxisa_ids)) <= 0) { 961 device_quiet(dev); 962 } 963 return(result); 964 } 965 966 static int 967 npxisa_attach(device_t dev) 968 { 969 return (0); 970 } 971 972 static device_method_t npxisa_methods[] = { 973 /* Device interface */ 974 DEVMETHOD(device_probe, npxisa_probe), 975 DEVMETHOD(device_attach, npxisa_attach), 976 DEVMETHOD(device_detach, bus_generic_detach), 977 DEVMETHOD(device_shutdown, bus_generic_shutdown), 978 DEVMETHOD(device_suspend, bus_generic_suspend), 979 DEVMETHOD(device_resume, bus_generic_resume), 980 981 { 0, 0 } 982 }; 983 984 static driver_t npxisa_driver = { 985 "npxisa", 986 npxisa_methods, 987 1, /* no softc */ 988 }; 989 990 static devclass_t npxisa_devclass; 991 992 DRIVER_MODULE(npxisa, isa, npxisa_driver, npxisa_devclass, 0, 0); 993 994