1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 1990 William Jolitz. 5 * Copyright (c) 1991 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of the University nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 33 */ 34 35 #include <sys/cdefs.h> 36 __FBSDID("$FreeBSD$"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/bus.h> 41 #include <sys/domainset.h> 42 #include <sys/kernel.h> 43 #include <sys/lock.h> 44 #include <sys/malloc.h> 45 #include <sys/module.h> 46 #include <sys/mutex.h> 47 #include <sys/mutex.h> 48 #include <sys/proc.h> 49 #include <sys/sysctl.h> 50 #include <machine/bus.h> 51 #include <sys/rman.h> 52 #include <sys/signalvar.h> 53 #include <vm/uma.h> 54 55 #include <machine/cputypes.h> 56 #include <machine/frame.h> 57 #include <machine/intr_machdep.h> 58 #include <machine/md_var.h> 59 #include <machine/pcb.h> 60 #include <machine/psl.h> 61 #include <machine/resource.h> 62 #include <machine/specialreg.h> 63 #include <machine/segments.h> 64 #include <machine/ucontext.h> 65 #include <x86/ifunc.h> 66 67 /* 68 * Floating point support. 69 */ 70 71 #if defined(__GNUCLIKE_ASM) && !defined(lint) 72 73 #define fldcw(cw) __asm __volatile("fldcw %0" : : "m" (cw)) 74 #define fnclex() __asm __volatile("fnclex") 75 #define fninit() __asm __volatile("fninit") 76 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 77 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=am" (*(addr))) 78 #define fxrstor(addr) __asm __volatile("fxrstor %0" : : "m" (*(addr))) 79 #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 80 #define ldmxcsr(csr) __asm __volatile("ldmxcsr %0" : : "m" (csr)) 81 #define stmxcsr(addr) __asm __volatile("stmxcsr %0" : : "m" (*(addr))) 82 83 static __inline void 84 xrstor(char *addr, uint64_t mask) 85 { 86 uint32_t low, hi; 87 88 low = mask; 89 hi = mask >> 32; 90 __asm __volatile("xrstor %0" : : "m" (*addr), "a" (low), "d" (hi)); 91 } 92 93 static __inline void 94 xsave(char *addr, uint64_t mask) 95 { 96 uint32_t low, hi; 97 98 low = mask; 99 hi = mask >> 32; 100 __asm __volatile("xsave %0" : "=m" (*addr) : "a" (low), "d" (hi) : 101 "memory"); 102 } 103 104 static __inline void 105 xsaveopt(char *addr, uint64_t mask) 106 { 107 uint32_t low, hi; 108 109 low = mask; 110 hi = mask >> 32; 111 __asm __volatile("xsaveopt %0" : "=m" (*addr) : "a" (low), "d" (hi) : 112 "memory"); 113 } 114 115 #else /* !(__GNUCLIKE_ASM && !lint) */ 116 117 void fldcw(u_short cw); 118 void fnclex(void); 119 void fninit(void); 120 void fnstcw(caddr_t addr); 121 void fnstsw(caddr_t addr); 122 void fxsave(caddr_t addr); 123 void fxrstor(caddr_t addr); 124 void ldmxcsr(u_int csr); 125 void stmxcsr(u_int *csr); 126 void xrstor(char *addr, uint64_t mask); 127 void xsave(char *addr, uint64_t mask); 128 void xsaveopt(char *addr, uint64_t mask); 129 130 #endif /* __GNUCLIKE_ASM && !lint */ 131 132 #define start_emulating() load_cr0(rcr0() | CR0_TS) 133 #define stop_emulating() clts() 134 135 CTASSERT(sizeof(struct savefpu) == 512); 136 CTASSERT(sizeof(struct xstate_hdr) == 64); 137 CTASSERT(sizeof(struct savefpu_ymm) == 832); 138 139 /* 140 * This requirement is to make it easier for asm code to calculate 141 * offset of the fpu save area from the pcb address. FPU save area 142 * must be 64-byte aligned. 143 */ 144 CTASSERT(sizeof(struct pcb) % XSAVE_AREA_ALIGN == 0); 145 146 /* 147 * Ensure the copy of XCR0 saved in a core is contained in the padding 148 * area. 149 */ 150 CTASSERT(X86_XSTATE_XCR0_OFFSET >= offsetof(struct savefpu, sv_pad) && 151 X86_XSTATE_XCR0_OFFSET + sizeof(uint64_t) <= sizeof(struct savefpu)); 152 153 static void fpu_clean_state(void); 154 155 SYSCTL_INT(_hw, HW_FLOATINGPT, floatingpoint, CTLFLAG_RD, 156 SYSCTL_NULL_INT_PTR, 1, "Floating point instructions executed in hardware"); 157 158 int use_xsave; /* non-static for cpu_switch.S */ 159 uint64_t xsave_mask; /* the same */ 160 static uma_zone_t fpu_save_area_zone; 161 static struct savefpu *fpu_initialstate; 162 163 static struct xsave_area_elm_descr { 164 u_int offset; 165 u_int size; 166 } *xsave_area_desc; 167 168 static void 169 fpusave_xsaveopt(void *addr) 170 { 171 172 xsaveopt((char *)addr, xsave_mask); 173 } 174 175 static void 176 fpusave_xsave(void *addr) 177 { 178 179 xsave((char *)addr, xsave_mask); 180 } 181 182 static void 183 fpurestore_xrstor(void *addr) 184 { 185 186 xrstor((char *)addr, xsave_mask); 187 } 188 189 static void 190 fpusave_fxsave(void *addr) 191 { 192 193 fxsave((char *)addr); 194 } 195 196 static void 197 fpurestore_fxrstor(void *addr) 198 { 199 200 fxrstor((char *)addr); 201 } 202 203 static void 204 init_xsave(void) 205 { 206 207 if (use_xsave) 208 return; 209 if ((cpu_feature2 & CPUID2_XSAVE) == 0) 210 return; 211 use_xsave = 1; 212 TUNABLE_INT_FETCH("hw.use_xsave", &use_xsave); 213 } 214 215 DEFINE_IFUNC(, void, fpusave, (void *)) 216 { 217 218 init_xsave(); 219 if (use_xsave) 220 return ((cpu_stdext_feature & CPUID_EXTSTATE_XSAVEOPT) != 0 ? 221 fpusave_xsaveopt : fpusave_xsave); 222 return (fpusave_fxsave); 223 } 224 225 DEFINE_IFUNC(, void, fpurestore, (void *)) 226 { 227 228 init_xsave(); 229 return (use_xsave ? fpurestore_xrstor : fpurestore_fxrstor); 230 } 231 232 void 233 fpususpend(void *addr) 234 { 235 u_long cr0; 236 237 cr0 = rcr0(); 238 stop_emulating(); 239 fpusave(addr); 240 load_cr0(cr0); 241 } 242 243 void 244 fpuresume(void *addr) 245 { 246 u_long cr0; 247 248 cr0 = rcr0(); 249 stop_emulating(); 250 fninit(); 251 if (use_xsave) 252 load_xcr(XCR0, xsave_mask); 253 fpurestore(addr); 254 load_cr0(cr0); 255 } 256 257 /* 258 * Enable XSAVE if supported and allowed by user. 259 * Calculate the xsave_mask. 260 */ 261 static void 262 fpuinit_bsp1(void) 263 { 264 u_int cp[4]; 265 uint64_t xsave_mask_user; 266 bool old_wp; 267 268 if (!use_xsave) 269 return; 270 cpuid_count(0xd, 0x0, cp); 271 xsave_mask = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE; 272 if ((cp[0] & xsave_mask) != xsave_mask) 273 panic("CPU0 does not support X87 or SSE: %x", cp[0]); 274 xsave_mask = ((uint64_t)cp[3] << 32) | cp[0]; 275 xsave_mask_user = xsave_mask; 276 TUNABLE_ULONG_FETCH("hw.xsave_mask", &xsave_mask_user); 277 xsave_mask_user |= XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE; 278 xsave_mask &= xsave_mask_user; 279 if ((xsave_mask & XFEATURE_AVX512) != XFEATURE_AVX512) 280 xsave_mask &= ~XFEATURE_AVX512; 281 if ((xsave_mask & XFEATURE_MPX) != XFEATURE_MPX) 282 xsave_mask &= ~XFEATURE_MPX; 283 284 cpuid_count(0xd, 0x1, cp); 285 if ((cp[0] & CPUID_EXTSTATE_XSAVEOPT) != 0) { 286 /* 287 * Patch the XSAVE instruction in the cpu_switch code 288 * to XSAVEOPT. We assume that XSAVE encoding used 289 * REX byte, and set the bit 4 of the r/m byte. 290 * 291 * It seems that some BIOSes give control to the OS 292 * with CR0.WP already set, making the kernel text 293 * read-only before cpu_startup(). 294 */ 295 old_wp = disable_wp(); 296 ctx_switch_xsave[3] |= 0x10; 297 restore_wp(old_wp); 298 } 299 } 300 301 /* 302 * Calculate the fpu save area size. 303 */ 304 static void 305 fpuinit_bsp2(void) 306 { 307 u_int cp[4]; 308 309 if (use_xsave) { 310 cpuid_count(0xd, 0x0, cp); 311 cpu_max_ext_state_size = cp[1]; 312 313 /* 314 * Reload the cpu_feature2, since we enabled OSXSAVE. 315 */ 316 do_cpuid(1, cp); 317 cpu_feature2 = cp[2]; 318 } else 319 cpu_max_ext_state_size = sizeof(struct savefpu); 320 } 321 322 /* 323 * Initialize the floating point unit. 324 */ 325 void 326 fpuinit(void) 327 { 328 register_t saveintr; 329 u_int mxcsr; 330 u_short control; 331 332 if (IS_BSP()) 333 fpuinit_bsp1(); 334 335 if (use_xsave) { 336 load_cr4(rcr4() | CR4_XSAVE); 337 load_xcr(XCR0, xsave_mask); 338 } 339 340 /* 341 * XCR0 shall be set up before CPU can report the save area size. 342 */ 343 if (IS_BSP()) 344 fpuinit_bsp2(); 345 346 /* 347 * It is too early for critical_enter() to work on AP. 348 */ 349 saveintr = intr_disable(); 350 stop_emulating(); 351 fninit(); 352 control = __INITIAL_FPUCW__; 353 fldcw(control); 354 mxcsr = __INITIAL_MXCSR__; 355 ldmxcsr(mxcsr); 356 start_emulating(); 357 intr_restore(saveintr); 358 } 359 360 /* 361 * On the boot CPU we generate a clean state that is used to 362 * initialize the floating point unit when it is first used by a 363 * process. 364 */ 365 static void 366 fpuinitstate(void *arg __unused) 367 { 368 uint64_t *xstate_bv; 369 register_t saveintr; 370 int cp[4], i, max_ext_n; 371 372 /* Do potentially blocking operations before disabling interrupts. */ 373 fpu_save_area_zone = uma_zcreate("FPU_save_area", 374 cpu_max_ext_state_size, NULL, NULL, NULL, NULL, 375 XSAVE_AREA_ALIGN - 1, 0); 376 fpu_initialstate = uma_zalloc(fpu_save_area_zone, M_WAITOK | M_ZERO); 377 if (use_xsave) { 378 max_ext_n = flsl(xsave_mask); 379 xsave_area_desc = malloc(max_ext_n * sizeof(struct 380 xsave_area_elm_descr), M_DEVBUF, M_WAITOK | M_ZERO); 381 } 382 383 saveintr = intr_disable(); 384 stop_emulating(); 385 386 fpusave_fxsave(fpu_initialstate); 387 if (fpu_initialstate->sv_env.en_mxcsr_mask) 388 cpu_mxcsr_mask = fpu_initialstate->sv_env.en_mxcsr_mask; 389 else 390 cpu_mxcsr_mask = 0xFFBF; 391 392 /* 393 * The fninit instruction does not modify XMM registers or x87 394 * registers (MM/ST). The fpusave call dumped the garbage 395 * contained in the registers after reset to the initial state 396 * saved. Clear XMM and x87 registers file image to make the 397 * startup program state and signal handler XMM/x87 register 398 * content predictable. 399 */ 400 bzero(fpu_initialstate->sv_fp, sizeof(fpu_initialstate->sv_fp)); 401 bzero(fpu_initialstate->sv_xmm, sizeof(fpu_initialstate->sv_xmm)); 402 403 /* 404 * Create a table describing the layout of the CPU Extended 405 * Save Area. 406 */ 407 if (use_xsave) { 408 xstate_bv = (uint64_t *)((char *)(fpu_initialstate + 1) + 409 offsetof(struct xstate_hdr, xstate_bv)); 410 *xstate_bv = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE; 411 412 /* x87 state */ 413 xsave_area_desc[0].offset = 0; 414 xsave_area_desc[0].size = 160; 415 /* XMM */ 416 xsave_area_desc[1].offset = 160; 417 xsave_area_desc[1].size = 288 - 160; 418 419 for (i = 2; i < max_ext_n; i++) { 420 cpuid_count(0xd, i, cp); 421 xsave_area_desc[i].offset = cp[1]; 422 xsave_area_desc[i].size = cp[0]; 423 } 424 } 425 426 start_emulating(); 427 intr_restore(saveintr); 428 } 429 /* EFIRT needs this to be initialized before we can enter our EFI environment */ 430 SYSINIT(fpuinitstate, SI_SUB_DRIVERS, SI_ORDER_FIRST, fpuinitstate, NULL); 431 432 /* 433 * Free coprocessor (if we have it). 434 */ 435 void 436 fpuexit(struct thread *td) 437 { 438 439 critical_enter(); 440 if (curthread == PCPU_GET(fpcurthread)) { 441 stop_emulating(); 442 fpusave(curpcb->pcb_save); 443 start_emulating(); 444 PCPU_SET(fpcurthread, NULL); 445 } 446 critical_exit(); 447 } 448 449 int 450 fpuformat(void) 451 { 452 453 return (_MC_FPFMT_XMM); 454 } 455 456 /* 457 * The following mechanism is used to ensure that the FPE_... value 458 * that is passed as a trapcode to the signal handler of the user 459 * process does not have more than one bit set. 460 * 461 * Multiple bits may be set if the user process modifies the control 462 * word while a status word bit is already set. While this is a sign 463 * of bad coding, we have no choise than to narrow them down to one 464 * bit, since we must not send a trapcode that is not exactly one of 465 * the FPE_ macros. 466 * 467 * The mechanism has a static table with 127 entries. Each combination 468 * of the 7 FPU status word exception bits directly translates to a 469 * position in this table, where a single FPE_... value is stored. 470 * This FPE_... value stored there is considered the "most important" 471 * of the exception bits and will be sent as the signal code. The 472 * precedence of the bits is based upon Intel Document "Numerical 473 * Applications", Chapter "Special Computational Situations". 474 * 475 * The macro to choose one of these values does these steps: 1) Throw 476 * away status word bits that cannot be masked. 2) Throw away the bits 477 * currently masked in the control word, assuming the user isn't 478 * interested in them anymore. 3) Reinsert status word bit 7 (stack 479 * fault) if it is set, which cannot be masked but must be presered. 480 * 4) Use the remaining bits to point into the trapcode table. 481 * 482 * The 6 maskable bits in order of their preference, as stated in the 483 * above referenced Intel manual: 484 * 1 Invalid operation (FP_X_INV) 485 * 1a Stack underflow 486 * 1b Stack overflow 487 * 1c Operand of unsupported format 488 * 1d SNaN operand. 489 * 2 QNaN operand (not an exception, irrelavant here) 490 * 3 Any other invalid-operation not mentioned above or zero divide 491 * (FP_X_INV, FP_X_DZ) 492 * 4 Denormal operand (FP_X_DNML) 493 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 494 * 6 Inexact result (FP_X_IMP) 495 */ 496 static char fpetable[128] = { 497 0, 498 FPE_FLTINV, /* 1 - INV */ 499 FPE_FLTUND, /* 2 - DNML */ 500 FPE_FLTINV, /* 3 - INV | DNML */ 501 FPE_FLTDIV, /* 4 - DZ */ 502 FPE_FLTINV, /* 5 - INV | DZ */ 503 FPE_FLTDIV, /* 6 - DNML | DZ */ 504 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 505 FPE_FLTOVF, /* 8 - OFL */ 506 FPE_FLTINV, /* 9 - INV | OFL */ 507 FPE_FLTUND, /* A - DNML | OFL */ 508 FPE_FLTINV, /* B - INV | DNML | OFL */ 509 FPE_FLTDIV, /* C - DZ | OFL */ 510 FPE_FLTINV, /* D - INV | DZ | OFL */ 511 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 512 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 513 FPE_FLTUND, /* 10 - UFL */ 514 FPE_FLTINV, /* 11 - INV | UFL */ 515 FPE_FLTUND, /* 12 - DNML | UFL */ 516 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 517 FPE_FLTDIV, /* 14 - DZ | UFL */ 518 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 519 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 520 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 521 FPE_FLTOVF, /* 18 - OFL | UFL */ 522 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 523 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 524 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 525 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 526 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 527 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 528 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 529 FPE_FLTRES, /* 20 - IMP */ 530 FPE_FLTINV, /* 21 - INV | IMP */ 531 FPE_FLTUND, /* 22 - DNML | IMP */ 532 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 533 FPE_FLTDIV, /* 24 - DZ | IMP */ 534 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 535 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 536 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 537 FPE_FLTOVF, /* 28 - OFL | IMP */ 538 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 539 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 540 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 541 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 542 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 543 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 544 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 545 FPE_FLTUND, /* 30 - UFL | IMP */ 546 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 547 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 548 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 549 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 550 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 551 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 552 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 553 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 554 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 555 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 556 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 557 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 558 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 559 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 560 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 561 FPE_FLTSUB, /* 40 - STK */ 562 FPE_FLTSUB, /* 41 - INV | STK */ 563 FPE_FLTUND, /* 42 - DNML | STK */ 564 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 565 FPE_FLTDIV, /* 44 - DZ | STK */ 566 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 567 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 568 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 569 FPE_FLTOVF, /* 48 - OFL | STK */ 570 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 571 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 572 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 573 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 574 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 575 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 576 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 577 FPE_FLTUND, /* 50 - UFL | STK */ 578 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 579 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 580 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 581 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 582 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 583 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 584 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 585 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 586 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 587 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 588 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 589 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 590 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 591 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 592 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 593 FPE_FLTRES, /* 60 - IMP | STK */ 594 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 595 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 596 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 597 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 598 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 599 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 600 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 601 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 602 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 603 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 604 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 605 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 606 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 607 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 608 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 609 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 610 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 611 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 612 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 613 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 614 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 615 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 616 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 617 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 618 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 619 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 620 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 621 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 622 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 623 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 624 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 625 }; 626 627 /* 628 * Read the FP status and control words, then generate si_code value 629 * for SIGFPE. The error code chosen will be one of the 630 * FPE_... macros. It will be sent as the second argument to old 631 * BSD-style signal handlers and as "siginfo_t->si_code" (second 632 * argument) to SA_SIGINFO signal handlers. 633 * 634 * Some time ago, we cleared the x87 exceptions with FNCLEX there. 635 * Clearing exceptions was necessary mainly to avoid IRQ13 bugs. The 636 * usermode code which understands the FPU hardware enough to enable 637 * the exceptions, can also handle clearing the exception state in the 638 * handler. The only consequence of not clearing the exception is the 639 * rethrow of the SIGFPE on return from the signal handler and 640 * reexecution of the corresponding instruction. 641 * 642 * For XMM traps, the exceptions were never cleared. 643 */ 644 int 645 fputrap_x87(void) 646 { 647 struct savefpu *pcb_save; 648 u_short control, status; 649 650 critical_enter(); 651 652 /* 653 * Interrupt handling (for another interrupt) may have pushed the 654 * state to memory. Fetch the relevant parts of the state from 655 * wherever they are. 656 */ 657 if (PCPU_GET(fpcurthread) != curthread) { 658 pcb_save = curpcb->pcb_save; 659 control = pcb_save->sv_env.en_cw; 660 status = pcb_save->sv_env.en_sw; 661 } else { 662 fnstcw(&control); 663 fnstsw(&status); 664 } 665 666 critical_exit(); 667 return (fpetable[status & ((~control & 0x3f) | 0x40)]); 668 } 669 670 int 671 fputrap_sse(void) 672 { 673 u_int mxcsr; 674 675 critical_enter(); 676 if (PCPU_GET(fpcurthread) != curthread) 677 mxcsr = curpcb->pcb_save->sv_env.en_mxcsr; 678 else 679 stmxcsr(&mxcsr); 680 critical_exit(); 681 return (fpetable[(mxcsr & (~mxcsr >> 7)) & 0x3f]); 682 } 683 684 static void 685 restore_fpu_curthread(struct thread *td) 686 { 687 struct pcb *pcb; 688 689 /* 690 * Record new context early in case frstor causes a trap. 691 */ 692 PCPU_SET(fpcurthread, td); 693 694 stop_emulating(); 695 fpu_clean_state(); 696 pcb = td->td_pcb; 697 698 if ((pcb->pcb_flags & PCB_FPUINITDONE) == 0) { 699 /* 700 * This is the first time this thread has used the FPU or 701 * the PCB doesn't contain a clean FPU state. Explicitly 702 * load an initial state. 703 * 704 * We prefer to restore the state from the actual save 705 * area in PCB instead of directly loading from 706 * fpu_initialstate, to ignite the XSAVEOPT 707 * tracking engine. 708 */ 709 bcopy(fpu_initialstate, pcb->pcb_save, 710 cpu_max_ext_state_size); 711 fpurestore(pcb->pcb_save); 712 if (pcb->pcb_initial_fpucw != __INITIAL_FPUCW__) 713 fldcw(pcb->pcb_initial_fpucw); 714 if (PCB_USER_FPU(pcb)) 715 set_pcb_flags(pcb, PCB_FPUINITDONE | 716 PCB_USERFPUINITDONE); 717 else 718 set_pcb_flags(pcb, PCB_FPUINITDONE); 719 } else 720 fpurestore(pcb->pcb_save); 721 } 722 723 /* 724 * Device Not Available (DNA, #NM) exception handler. 725 * 726 * It would be better to switch FP context here (if curthread != 727 * fpcurthread) and not necessarily for every context switch, but it 728 * is too hard to access foreign pcb's. 729 */ 730 void 731 fpudna(void) 732 { 733 struct thread *td; 734 735 td = curthread; 736 /* 737 * This handler is entered with interrupts enabled, so context 738 * switches may occur before critical_enter() is executed. If 739 * a context switch occurs, then when we regain control, our 740 * state will have been completely restored. The CPU may 741 * change underneath us, but the only part of our context that 742 * lives in the CPU is CR0.TS and that will be "restored" by 743 * setting it on the new CPU. 744 */ 745 critical_enter(); 746 747 KASSERT((curpcb->pcb_flags & PCB_FPUNOSAVE) == 0, 748 ("fpudna while in fpu_kern_enter(FPU_KERN_NOCTX)")); 749 if (__predict_false(PCPU_GET(fpcurthread) == td)) { 750 /* 751 * Some virtual machines seems to set %cr0.TS at 752 * arbitrary moments. Silently clear the TS bit 753 * regardless of the eager/lazy FPU context switch 754 * mode. 755 */ 756 stop_emulating(); 757 } else { 758 if (__predict_false(PCPU_GET(fpcurthread) != NULL)) { 759 panic( 760 "fpudna: fpcurthread = %p (%d), curthread = %p (%d)\n", 761 PCPU_GET(fpcurthread), 762 PCPU_GET(fpcurthread)->td_tid, td, td->td_tid); 763 } 764 restore_fpu_curthread(td); 765 } 766 critical_exit(); 767 } 768 769 void fpu_activate_sw(struct thread *td); /* Called from the context switch */ 770 void 771 fpu_activate_sw(struct thread *td) 772 { 773 774 if ((td->td_pflags & TDP_KTHREAD) != 0 || !PCB_USER_FPU(td->td_pcb)) { 775 PCPU_SET(fpcurthread, NULL); 776 start_emulating(); 777 } else if (PCPU_GET(fpcurthread) != td) { 778 restore_fpu_curthread(td); 779 } 780 } 781 782 void 783 fpudrop(void) 784 { 785 struct thread *td; 786 787 td = PCPU_GET(fpcurthread); 788 KASSERT(td == curthread, ("fpudrop: fpcurthread != curthread")); 789 CRITICAL_ASSERT(td); 790 PCPU_SET(fpcurthread, NULL); 791 clear_pcb_flags(td->td_pcb, PCB_FPUINITDONE); 792 start_emulating(); 793 } 794 795 /* 796 * Get the user state of the FPU into pcb->pcb_user_save without 797 * dropping ownership (if possible). It returns the FPU ownership 798 * status. 799 */ 800 int 801 fpugetregs(struct thread *td) 802 { 803 struct pcb *pcb; 804 uint64_t *xstate_bv, bit; 805 char *sa; 806 int max_ext_n, i, owned; 807 808 pcb = td->td_pcb; 809 critical_enter(); 810 if ((pcb->pcb_flags & PCB_USERFPUINITDONE) == 0) { 811 bcopy(fpu_initialstate, get_pcb_user_save_pcb(pcb), 812 cpu_max_ext_state_size); 813 get_pcb_user_save_pcb(pcb)->sv_env.en_cw = 814 pcb->pcb_initial_fpucw; 815 fpuuserinited(td); 816 critical_exit(); 817 return (_MC_FPOWNED_PCB); 818 } 819 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) { 820 fpusave(get_pcb_user_save_pcb(pcb)); 821 owned = _MC_FPOWNED_FPU; 822 } else { 823 owned = _MC_FPOWNED_PCB; 824 } 825 if (use_xsave) { 826 /* 827 * Handle partially saved state. 828 */ 829 sa = (char *)get_pcb_user_save_pcb(pcb); 830 xstate_bv = (uint64_t *)(sa + sizeof(struct savefpu) + 831 offsetof(struct xstate_hdr, xstate_bv)); 832 max_ext_n = flsl(xsave_mask); 833 for (i = 0; i < max_ext_n; i++) { 834 bit = 1ULL << i; 835 if ((xsave_mask & bit) == 0 || (*xstate_bv & bit) != 0) 836 continue; 837 bcopy((char *)fpu_initialstate + 838 xsave_area_desc[i].offset, 839 sa + xsave_area_desc[i].offset, 840 xsave_area_desc[i].size); 841 *xstate_bv |= bit; 842 } 843 } 844 critical_exit(); 845 return (owned); 846 } 847 848 void 849 fpuuserinited(struct thread *td) 850 { 851 struct pcb *pcb; 852 853 CRITICAL_ASSERT(td); 854 pcb = td->td_pcb; 855 if (PCB_USER_FPU(pcb)) 856 set_pcb_flags(pcb, 857 PCB_FPUINITDONE | PCB_USERFPUINITDONE); 858 else 859 set_pcb_flags(pcb, PCB_FPUINITDONE); 860 } 861 862 int 863 fpusetxstate(struct thread *td, char *xfpustate, size_t xfpustate_size) 864 { 865 struct xstate_hdr *hdr, *ehdr; 866 size_t len, max_len; 867 uint64_t bv; 868 869 /* XXXKIB should we clear all extended state in xstate_bv instead ? */ 870 if (xfpustate == NULL) 871 return (0); 872 if (!use_xsave) 873 return (EOPNOTSUPP); 874 875 len = xfpustate_size; 876 if (len < sizeof(struct xstate_hdr)) 877 return (EINVAL); 878 max_len = cpu_max_ext_state_size - sizeof(struct savefpu); 879 if (len > max_len) 880 return (EINVAL); 881 882 ehdr = (struct xstate_hdr *)xfpustate; 883 bv = ehdr->xstate_bv; 884 885 /* 886 * Avoid #gp. 887 */ 888 if (bv & ~xsave_mask) 889 return (EINVAL); 890 891 hdr = (struct xstate_hdr *)(get_pcb_user_save_td(td) + 1); 892 893 hdr->xstate_bv = bv; 894 bcopy(xfpustate + sizeof(struct xstate_hdr), 895 (char *)(hdr + 1), len - sizeof(struct xstate_hdr)); 896 897 return (0); 898 } 899 900 /* 901 * Set the state of the FPU. 902 */ 903 int 904 fpusetregs(struct thread *td, struct savefpu *addr, char *xfpustate, 905 size_t xfpustate_size) 906 { 907 struct pcb *pcb; 908 int error; 909 910 addr->sv_env.en_mxcsr &= cpu_mxcsr_mask; 911 pcb = td->td_pcb; 912 error = 0; 913 critical_enter(); 914 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) { 915 error = fpusetxstate(td, xfpustate, xfpustate_size); 916 if (error == 0) { 917 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr)); 918 fpurestore(get_pcb_user_save_td(td)); 919 set_pcb_flags(pcb, PCB_FPUINITDONE | 920 PCB_USERFPUINITDONE); 921 } 922 } else { 923 error = fpusetxstate(td, xfpustate, xfpustate_size); 924 if (error == 0) { 925 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr)); 926 fpuuserinited(td); 927 } 928 } 929 critical_exit(); 930 return (error); 931 } 932 933 /* 934 * On AuthenticAMD processors, the fxrstor instruction does not restore 935 * the x87's stored last instruction pointer, last data pointer, and last 936 * opcode values, except in the rare case in which the exception summary 937 * (ES) bit in the x87 status word is set to 1. 938 * 939 * In order to avoid leaking this information across processes, we clean 940 * these values by performing a dummy load before executing fxrstor(). 941 */ 942 static void 943 fpu_clean_state(void) 944 { 945 static float dummy_variable = 0.0; 946 u_short status; 947 948 /* 949 * Clear the ES bit in the x87 status word if it is currently 950 * set, in order to avoid causing a fault in the upcoming load. 951 */ 952 fnstsw(&status); 953 if (status & 0x80) 954 fnclex(); 955 956 /* 957 * Load the dummy variable into the x87 stack. This mangles 958 * the x87 stack, but we don't care since we're about to call 959 * fxrstor() anyway. 960 */ 961 __asm __volatile("ffree %%st(7); flds %0" : : "m" (dummy_variable)); 962 } 963 964 /* 965 * This really sucks. We want the acpi version only, but it requires 966 * the isa_if.h file in order to get the definitions. 967 */ 968 #include "opt_isa.h" 969 #ifdef DEV_ISA 970 #include <isa/isavar.h> 971 /* 972 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI. 973 */ 974 static struct isa_pnp_id fpupnp_ids[] = { 975 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */ 976 { 0 } 977 }; 978 979 static int 980 fpupnp_probe(device_t dev) 981 { 982 int result; 983 984 result = ISA_PNP_PROBE(device_get_parent(dev), dev, fpupnp_ids); 985 if (result <= 0) 986 device_quiet(dev); 987 return (result); 988 } 989 990 static int 991 fpupnp_attach(device_t dev) 992 { 993 994 return (0); 995 } 996 997 static device_method_t fpupnp_methods[] = { 998 /* Device interface */ 999 DEVMETHOD(device_probe, fpupnp_probe), 1000 DEVMETHOD(device_attach, fpupnp_attach), 1001 DEVMETHOD(device_detach, bus_generic_detach), 1002 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1003 DEVMETHOD(device_suspend, bus_generic_suspend), 1004 DEVMETHOD(device_resume, bus_generic_resume), 1005 { 0, 0 } 1006 }; 1007 1008 static driver_t fpupnp_driver = { 1009 "fpupnp", 1010 fpupnp_methods, 1011 1, /* no softc */ 1012 }; 1013 1014 static devclass_t fpupnp_devclass; 1015 1016 DRIVER_MODULE(fpupnp, acpi, fpupnp_driver, fpupnp_devclass, 0, 0); 1017 ISA_PNP_INFO(fpupnp_ids); 1018 #endif /* DEV_ISA */ 1019 1020 static MALLOC_DEFINE(M_FPUKERN_CTX, "fpukern_ctx", 1021 "Kernel contexts for FPU state"); 1022 1023 #define FPU_KERN_CTX_FPUINITDONE 0x01 1024 #define FPU_KERN_CTX_DUMMY 0x02 /* avoided save for the kern thread */ 1025 #define FPU_KERN_CTX_INUSE 0x04 1026 1027 struct fpu_kern_ctx { 1028 struct savefpu *prev; 1029 uint32_t flags; 1030 char hwstate1[]; 1031 }; 1032 1033 static inline size_t __pure2 1034 fpu_kern_alloc_sz(u_int max_est) 1035 { 1036 return (sizeof(struct fpu_kern_ctx) + XSAVE_AREA_ALIGN + max_est); 1037 } 1038 1039 static inline int __pure2 1040 fpu_kern_malloc_flags(u_int fpflags) 1041 { 1042 return (((fpflags & FPU_KERN_NOWAIT) ? M_NOWAIT : M_WAITOK) | M_ZERO); 1043 } 1044 1045 struct fpu_kern_ctx * 1046 fpu_kern_alloc_ctx_domain(int domain, u_int flags) 1047 { 1048 return (malloc_domainset(fpu_kern_alloc_sz(cpu_max_ext_state_size), 1049 M_FPUKERN_CTX, DOMAINSET_PREF(domain), 1050 fpu_kern_malloc_flags(flags))); 1051 } 1052 1053 struct fpu_kern_ctx * 1054 fpu_kern_alloc_ctx(u_int flags) 1055 { 1056 return (malloc(fpu_kern_alloc_sz(cpu_max_ext_state_size), 1057 M_FPUKERN_CTX, fpu_kern_malloc_flags(flags))); 1058 } 1059 1060 void 1061 fpu_kern_free_ctx(struct fpu_kern_ctx *ctx) 1062 { 1063 1064 KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) == 0, ("free'ing inuse ctx")); 1065 /* XXXKIB clear the memory ? */ 1066 free(ctx, M_FPUKERN_CTX); 1067 } 1068 1069 static struct savefpu * 1070 fpu_kern_ctx_savefpu(struct fpu_kern_ctx *ctx) 1071 { 1072 vm_offset_t p; 1073 1074 p = (vm_offset_t)&ctx->hwstate1; 1075 p = roundup2(p, XSAVE_AREA_ALIGN); 1076 return ((struct savefpu *)p); 1077 } 1078 1079 void 1080 fpu_kern_enter(struct thread *td, struct fpu_kern_ctx *ctx, u_int flags) 1081 { 1082 struct pcb *pcb; 1083 1084 pcb = td->td_pcb; 1085 KASSERT((flags & FPU_KERN_NOCTX) != 0 || ctx != NULL, 1086 ("ctx is required when !FPU_KERN_NOCTX")); 1087 KASSERT(ctx == NULL || (ctx->flags & FPU_KERN_CTX_INUSE) == 0, 1088 ("using inuse ctx")); 1089 KASSERT((pcb->pcb_flags & PCB_FPUNOSAVE) == 0, 1090 ("recursive fpu_kern_enter while in PCB_FPUNOSAVE state")); 1091 1092 if ((flags & FPU_KERN_NOCTX) != 0) { 1093 critical_enter(); 1094 stop_emulating(); 1095 if (curthread == PCPU_GET(fpcurthread)) { 1096 fpusave(curpcb->pcb_save); 1097 PCPU_SET(fpcurthread, NULL); 1098 } else { 1099 KASSERT(PCPU_GET(fpcurthread) == NULL, 1100 ("invalid fpcurthread")); 1101 } 1102 1103 /* 1104 * This breaks XSAVEOPT tracker, but 1105 * PCB_FPUNOSAVE state is supposed to never need to 1106 * save FPU context at all. 1107 */ 1108 fpurestore(fpu_initialstate); 1109 set_pcb_flags(pcb, PCB_KERNFPU | PCB_FPUNOSAVE | 1110 PCB_FPUINITDONE); 1111 return; 1112 } 1113 if ((flags & FPU_KERN_KTHR) != 0 && is_fpu_kern_thread(0)) { 1114 ctx->flags = FPU_KERN_CTX_DUMMY | FPU_KERN_CTX_INUSE; 1115 return; 1116 } 1117 critical_enter(); 1118 KASSERT(!PCB_USER_FPU(pcb) || pcb->pcb_save == 1119 get_pcb_user_save_pcb(pcb), ("mangled pcb_save")); 1120 ctx->flags = FPU_KERN_CTX_INUSE; 1121 if ((pcb->pcb_flags & PCB_FPUINITDONE) != 0) 1122 ctx->flags |= FPU_KERN_CTX_FPUINITDONE; 1123 fpuexit(td); 1124 ctx->prev = pcb->pcb_save; 1125 pcb->pcb_save = fpu_kern_ctx_savefpu(ctx); 1126 set_pcb_flags(pcb, PCB_KERNFPU); 1127 clear_pcb_flags(pcb, PCB_FPUINITDONE); 1128 critical_exit(); 1129 } 1130 1131 int 1132 fpu_kern_leave(struct thread *td, struct fpu_kern_ctx *ctx) 1133 { 1134 struct pcb *pcb; 1135 1136 pcb = td->td_pcb; 1137 1138 if ((pcb->pcb_flags & PCB_FPUNOSAVE) != 0) { 1139 KASSERT(ctx == NULL, ("non-null ctx after FPU_KERN_NOCTX")); 1140 KASSERT(PCPU_GET(fpcurthread) == NULL, 1141 ("non-NULL fpcurthread for PCB_FPUNOSAVE")); 1142 CRITICAL_ASSERT(td); 1143 1144 clear_pcb_flags(pcb, PCB_FPUNOSAVE | PCB_FPUINITDONE); 1145 start_emulating(); 1146 } else { 1147 KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) != 0, 1148 ("leaving not inuse ctx")); 1149 ctx->flags &= ~FPU_KERN_CTX_INUSE; 1150 1151 if (is_fpu_kern_thread(0) && 1152 (ctx->flags & FPU_KERN_CTX_DUMMY) != 0) 1153 return (0); 1154 KASSERT((ctx->flags & FPU_KERN_CTX_DUMMY) == 0, 1155 ("dummy ctx")); 1156 critical_enter(); 1157 if (curthread == PCPU_GET(fpcurthread)) 1158 fpudrop(); 1159 pcb->pcb_save = ctx->prev; 1160 } 1161 1162 if (pcb->pcb_save == get_pcb_user_save_pcb(pcb)) { 1163 if ((pcb->pcb_flags & PCB_USERFPUINITDONE) != 0) { 1164 set_pcb_flags(pcb, PCB_FPUINITDONE); 1165 clear_pcb_flags(pcb, PCB_KERNFPU); 1166 } else 1167 clear_pcb_flags(pcb, PCB_FPUINITDONE | PCB_KERNFPU); 1168 } else { 1169 if ((ctx->flags & FPU_KERN_CTX_FPUINITDONE) != 0) 1170 set_pcb_flags(pcb, PCB_FPUINITDONE); 1171 else 1172 clear_pcb_flags(pcb, PCB_FPUINITDONE); 1173 KASSERT(!PCB_USER_FPU(pcb), ("unpaired fpu_kern_leave")); 1174 } 1175 critical_exit(); 1176 return (0); 1177 } 1178 1179 int 1180 fpu_kern_thread(u_int flags) 1181 { 1182 1183 KASSERT((curthread->td_pflags & TDP_KTHREAD) != 0, 1184 ("Only kthread may use fpu_kern_thread")); 1185 KASSERT(curpcb->pcb_save == get_pcb_user_save_pcb(curpcb), 1186 ("mangled pcb_save")); 1187 KASSERT(PCB_USER_FPU(curpcb), ("recursive call")); 1188 1189 set_pcb_flags(curpcb, PCB_KERNFPU); 1190 return (0); 1191 } 1192 1193 int 1194 is_fpu_kern_thread(u_int flags) 1195 { 1196 1197 if ((curthread->td_pflags & TDP_KTHREAD) == 0) 1198 return (0); 1199 return ((curpcb->pcb_flags & PCB_KERNFPU) != 0); 1200 } 1201 1202 /* 1203 * FPU save area alloc/free/init utility routines 1204 */ 1205 struct savefpu * 1206 fpu_save_area_alloc(void) 1207 { 1208 1209 return (uma_zalloc(fpu_save_area_zone, M_WAITOK)); 1210 } 1211 1212 void 1213 fpu_save_area_free(struct savefpu *fsa) 1214 { 1215 1216 uma_zfree(fpu_save_area_zone, fsa); 1217 } 1218 1219 void 1220 fpu_save_area_reset(struct savefpu *fsa) 1221 { 1222 1223 bcopy(fpu_initialstate, fsa, cpu_max_ext_state_size); 1224 } 1225