xref: /freebsd/sys/amd64/amd64/fpu.c (revision a223d3ed90bfe313ce5987d468a25a915d7d1254)
1 /*-
2  * Copyright (c) 1990 William Jolitz.
3  * Copyright (c) 1991 The Regents of the University of California.
4  * All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  * 4. Neither the name of the University nor the names of its contributors
15  *    may be used to endorse or promote products derived from this software
16  *    without specific prior written permission.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28  * SUCH DAMAGE.
29  *
30  *	from: @(#)npx.c	7.2 (Berkeley) 5/12/91
31  */
32 
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
35 
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/bus.h>
39 #include <sys/kernel.h>
40 #include <sys/lock.h>
41 #include <sys/malloc.h>
42 #include <sys/module.h>
43 #include <sys/mutex.h>
44 #include <sys/mutex.h>
45 #include <sys/proc.h>
46 #include <sys/sysctl.h>
47 #include <machine/bus.h>
48 #include <sys/rman.h>
49 #include <sys/signalvar.h>
50 #include <vm/uma.h>
51 
52 #include <machine/cputypes.h>
53 #include <machine/frame.h>
54 #include <machine/intr_machdep.h>
55 #include <machine/md_var.h>
56 #include <machine/pcb.h>
57 #include <machine/psl.h>
58 #include <machine/resource.h>
59 #include <machine/specialreg.h>
60 #include <machine/segments.h>
61 #include <machine/ucontext.h>
62 
63 /*
64  * Floating point support.
65  */
66 
67 #if defined(__GNUCLIKE_ASM) && !defined(lint)
68 
69 #define	fldcw(cw)		__asm __volatile("fldcw %0" : : "m" (cw))
70 #define	fnclex()		__asm __volatile("fnclex")
71 #define	fninit()		__asm __volatile("fninit")
72 #define	fnstcw(addr)		__asm __volatile("fnstcw %0" : "=m" (*(addr)))
73 #define	fnstsw(addr)		__asm __volatile("fnstsw %0" : "=am" (*(addr)))
74 #define	fxrstor(addr)		__asm __volatile("fxrstor %0" : : "m" (*(addr)))
75 #define	fxsave(addr)		__asm __volatile("fxsave %0" : "=m" (*(addr)))
76 #define	ldmxcsr(csr)		__asm __volatile("ldmxcsr %0" : : "m" (csr))
77 #define	stmxcsr(addr)		__asm __volatile("stmxcsr %0" : : "m" (*(addr)))
78 
79 static __inline void
80 xrstor(char *addr, uint64_t mask)
81 {
82 	uint32_t low, hi;
83 
84 	low = mask;
85 	hi = mask >> 32;
86 	__asm __volatile("xrstor %0" : : "m" (*addr), "a" (low), "d" (hi));
87 }
88 
89 static __inline void
90 xsave(char *addr, uint64_t mask)
91 {
92 	uint32_t low, hi;
93 
94 	low = mask;
95 	hi = mask >> 32;
96 	__asm __volatile("xsave %0" : "=m" (*addr) : "a" (low), "d" (hi) :
97 	    "memory");
98 }
99 
100 #else	/* !(__GNUCLIKE_ASM && !lint) */
101 
102 void	fldcw(u_short cw);
103 void	fnclex(void);
104 void	fninit(void);
105 void	fnstcw(caddr_t addr);
106 void	fnstsw(caddr_t addr);
107 void	fxsave(caddr_t addr);
108 void	fxrstor(caddr_t addr);
109 void	ldmxcsr(u_int csr);
110 void	stmxcsr(u_int *csr);
111 void	xrstor(char *addr, uint64_t mask);
112 void	xsave(char *addr, uint64_t mask);
113 
114 #endif	/* __GNUCLIKE_ASM && !lint */
115 
116 #define	start_emulating()	load_cr0(rcr0() | CR0_TS)
117 #define	stop_emulating()	clts()
118 
119 CTASSERT(sizeof(struct savefpu) == 512);
120 CTASSERT(sizeof(struct xstate_hdr) == 64);
121 CTASSERT(sizeof(struct savefpu_ymm) == 832);
122 
123 /*
124  * This requirement is to make it easier for asm code to calculate
125  * offset of the fpu save area from the pcb address. FPU save area
126  * must be 64-byte aligned.
127  */
128 CTASSERT(sizeof(struct pcb) % XSAVE_AREA_ALIGN == 0);
129 
130 static	void	fpu_clean_state(void);
131 
132 SYSCTL_INT(_hw, HW_FLOATINGPT, floatingpoint, CTLFLAG_RD,
133     NULL, 1, "Floating point instructions executed in hardware");
134 
135 int use_xsave;			/* non-static for cpu_switch.S */
136 uint64_t xsave_mask;		/* the same */
137 static	uma_zone_t fpu_save_area_zone;
138 static	struct savefpu *fpu_initialstate;
139 
140 struct xsave_area_elm_descr {
141 	u_int	offset;
142 	u_int	size;
143 } *xsave_area_desc;
144 
145 void
146 fpusave(void *addr)
147 {
148 
149 	if (use_xsave)
150 		xsave((char *)addr, xsave_mask);
151 	else
152 		fxsave((char *)addr);
153 }
154 
155 void
156 fpurestore(void *addr)
157 {
158 
159 	if (use_xsave)
160 		xrstor((char *)addr, xsave_mask);
161 	else
162 		fxrstor((char *)addr);
163 }
164 
165 void
166 fpususpend(void *addr)
167 {
168 	u_long cr0;
169 
170 	cr0 = rcr0();
171 	stop_emulating();
172 	fpusave(addr);
173 	load_cr0(cr0);
174 }
175 
176 /*
177  * Enable XSAVE if supported and allowed by user.
178  * Calculate the xsave_mask.
179  */
180 static void
181 fpuinit_bsp1(void)
182 {
183 	u_int cp[4];
184 	uint64_t xsave_mask_user;
185 
186 	if ((cpu_feature2 & CPUID2_XSAVE) != 0) {
187 		use_xsave = 1;
188 		TUNABLE_INT_FETCH("hw.use_xsave", &use_xsave);
189 	}
190 	if (!use_xsave)
191 		return;
192 
193 	cpuid_count(0xd, 0x0, cp);
194 	xsave_mask = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE;
195 	if ((cp[0] & xsave_mask) != xsave_mask)
196 		panic("CPU0 does not support X87 or SSE: %x", cp[0]);
197 	xsave_mask = ((uint64_t)cp[3] << 32) | cp[0];
198 	xsave_mask_user = xsave_mask;
199 	TUNABLE_ULONG_FETCH("hw.xsave_mask", &xsave_mask_user);
200 	xsave_mask_user |= XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE;
201 	xsave_mask &= xsave_mask_user;
202 	if ((xsave_mask & XFEATURE_AVX512) != XFEATURE_AVX512)
203 		xsave_mask &= ~XFEATURE_AVX512;
204 	if ((xsave_mask & XFEATURE_MPX) != XFEATURE_MPX)
205 		xsave_mask &= ~XFEATURE_MPX;
206 
207 	cpuid_count(0xd, 0x1, cp);
208 	if ((cp[0] & CPUID_EXTSTATE_XSAVEOPT) != 0) {
209 		/*
210 		 * Patch the XSAVE instruction in the cpu_switch code
211 		 * to XSAVEOPT.  We assume that XSAVE encoding used
212 		 * REX byte, and set the bit 4 of the r/m byte.
213 		 */
214 		ctx_switch_xsave[3] |= 0x10;
215 	}
216 }
217 
218 /*
219  * Calculate the fpu save area size.
220  */
221 static void
222 fpuinit_bsp2(void)
223 {
224 	u_int cp[4];
225 
226 	if (use_xsave) {
227 		cpuid_count(0xd, 0x0, cp);
228 		cpu_max_ext_state_size = cp[1];
229 
230 		/*
231 		 * Reload the cpu_feature2, since we enabled OSXSAVE.
232 		 */
233 		do_cpuid(1, cp);
234 		cpu_feature2 = cp[2];
235 	} else
236 		cpu_max_ext_state_size = sizeof(struct savefpu);
237 }
238 
239 /*
240  * Initialize the floating point unit.
241  */
242 void
243 fpuinit(void)
244 {
245 	register_t saveintr;
246 	u_int mxcsr;
247 	u_short control;
248 
249 	if (IS_BSP())
250 		fpuinit_bsp1();
251 
252 	if (use_xsave) {
253 		load_cr4(rcr4() | CR4_XSAVE);
254 		load_xcr(XCR0, xsave_mask);
255 	}
256 
257 	/*
258 	 * XCR0 shall be set up before CPU can report the save area size.
259 	 */
260 	if (IS_BSP())
261 		fpuinit_bsp2();
262 
263 	/*
264 	 * It is too early for critical_enter() to work on AP.
265 	 */
266 	saveintr = intr_disable();
267 	stop_emulating();
268 	fninit();
269 	control = __INITIAL_FPUCW__;
270 	fldcw(control);
271 	mxcsr = __INITIAL_MXCSR__;
272 	ldmxcsr(mxcsr);
273 	start_emulating();
274 	intr_restore(saveintr);
275 }
276 
277 /*
278  * On the boot CPU we generate a clean state that is used to
279  * initialize the floating point unit when it is first used by a
280  * process.
281  */
282 static void
283 fpuinitstate(void *arg __unused)
284 {
285 	register_t saveintr;
286 	int cp[4], i, max_ext_n;
287 
288 	fpu_initialstate = malloc(cpu_max_ext_state_size, M_DEVBUF,
289 	    M_WAITOK | M_ZERO);
290 	saveintr = intr_disable();
291 	stop_emulating();
292 
293 	fpusave(fpu_initialstate);
294 	if (fpu_initialstate->sv_env.en_mxcsr_mask)
295 		cpu_mxcsr_mask = fpu_initialstate->sv_env.en_mxcsr_mask;
296 	else
297 		cpu_mxcsr_mask = 0xFFBF;
298 
299 	/*
300 	 * The fninit instruction does not modify XMM registers.  The
301 	 * fpusave call dumped the garbage contained in the registers
302 	 * after reset to the initial state saved.  Clear XMM
303 	 * registers file image to make the startup program state and
304 	 * signal handler XMM register content predictable.
305 	 */
306 	bzero(&fpu_initialstate->sv_xmm[0], sizeof(struct xmmacc));
307 
308 	/*
309 	 * Create a table describing the layout of the CPU Extended
310 	 * Save Area.
311 	 */
312 	if (use_xsave) {
313 		max_ext_n = flsl(xsave_mask);
314 		xsave_area_desc = malloc(max_ext_n * sizeof(struct
315 		    xsave_area_elm_descr), M_DEVBUF, M_WAITOK | M_ZERO);
316 		/* x87 state */
317 		xsave_area_desc[0].offset = 0;
318 		xsave_area_desc[0].size = 160;
319 		/* XMM */
320 		xsave_area_desc[1].offset = 160;
321 		xsave_area_desc[1].size = 288 - 160;
322 
323 		for (i = 2; i < max_ext_n; i++) {
324 			cpuid_count(0xd, i, cp);
325 			xsave_area_desc[i].offset = cp[1];
326 			xsave_area_desc[i].size = cp[0];
327 		}
328 	}
329 
330 	fpu_save_area_zone = uma_zcreate("FPU_save_area",
331 	    cpu_max_ext_state_size, NULL, NULL, NULL, NULL,
332 	    XSAVE_AREA_ALIGN - 1, 0);
333 
334 	start_emulating();
335 	intr_restore(saveintr);
336 }
337 SYSINIT(fpuinitstate, SI_SUB_DRIVERS, SI_ORDER_ANY, fpuinitstate, NULL);
338 
339 /*
340  * Free coprocessor (if we have it).
341  */
342 void
343 fpuexit(struct thread *td)
344 {
345 
346 	critical_enter();
347 	if (curthread == PCPU_GET(fpcurthread)) {
348 		stop_emulating();
349 		fpusave(curpcb->pcb_save);
350 		start_emulating();
351 		PCPU_SET(fpcurthread, 0);
352 	}
353 	critical_exit();
354 }
355 
356 int
357 fpuformat()
358 {
359 
360 	return (_MC_FPFMT_XMM);
361 }
362 
363 /*
364  * The following mechanism is used to ensure that the FPE_... value
365  * that is passed as a trapcode to the signal handler of the user
366  * process does not have more than one bit set.
367  *
368  * Multiple bits may be set if the user process modifies the control
369  * word while a status word bit is already set.  While this is a sign
370  * of bad coding, we have no choise than to narrow them down to one
371  * bit, since we must not send a trapcode that is not exactly one of
372  * the FPE_ macros.
373  *
374  * The mechanism has a static table with 127 entries.  Each combination
375  * of the 7 FPU status word exception bits directly translates to a
376  * position in this table, where a single FPE_... value is stored.
377  * This FPE_... value stored there is considered the "most important"
378  * of the exception bits and will be sent as the signal code.  The
379  * precedence of the bits is based upon Intel Document "Numerical
380  * Applications", Chapter "Special Computational Situations".
381  *
382  * The macro to choose one of these values does these steps: 1) Throw
383  * away status word bits that cannot be masked.  2) Throw away the bits
384  * currently masked in the control word, assuming the user isn't
385  * interested in them anymore.  3) Reinsert status word bit 7 (stack
386  * fault) if it is set, which cannot be masked but must be presered.
387  * 4) Use the remaining bits to point into the trapcode table.
388  *
389  * The 6 maskable bits in order of their preference, as stated in the
390  * above referenced Intel manual:
391  * 1  Invalid operation (FP_X_INV)
392  * 1a   Stack underflow
393  * 1b   Stack overflow
394  * 1c   Operand of unsupported format
395  * 1d   SNaN operand.
396  * 2  QNaN operand (not an exception, irrelavant here)
397  * 3  Any other invalid-operation not mentioned above or zero divide
398  *      (FP_X_INV, FP_X_DZ)
399  * 4  Denormal operand (FP_X_DNML)
400  * 5  Numeric over/underflow (FP_X_OFL, FP_X_UFL)
401  * 6  Inexact result (FP_X_IMP)
402  */
403 static char fpetable[128] = {
404 	0,
405 	FPE_FLTINV,	/*  1 - INV */
406 	FPE_FLTUND,	/*  2 - DNML */
407 	FPE_FLTINV,	/*  3 - INV | DNML */
408 	FPE_FLTDIV,	/*  4 - DZ */
409 	FPE_FLTINV,	/*  5 - INV | DZ */
410 	FPE_FLTDIV,	/*  6 - DNML | DZ */
411 	FPE_FLTINV,	/*  7 - INV | DNML | DZ */
412 	FPE_FLTOVF,	/*  8 - OFL */
413 	FPE_FLTINV,	/*  9 - INV | OFL */
414 	FPE_FLTUND,	/*  A - DNML | OFL */
415 	FPE_FLTINV,	/*  B - INV | DNML | OFL */
416 	FPE_FLTDIV,	/*  C - DZ | OFL */
417 	FPE_FLTINV,	/*  D - INV | DZ | OFL */
418 	FPE_FLTDIV,	/*  E - DNML | DZ | OFL */
419 	FPE_FLTINV,	/*  F - INV | DNML | DZ | OFL */
420 	FPE_FLTUND,	/* 10 - UFL */
421 	FPE_FLTINV,	/* 11 - INV | UFL */
422 	FPE_FLTUND,	/* 12 - DNML | UFL */
423 	FPE_FLTINV,	/* 13 - INV | DNML | UFL */
424 	FPE_FLTDIV,	/* 14 - DZ | UFL */
425 	FPE_FLTINV,	/* 15 - INV | DZ | UFL */
426 	FPE_FLTDIV,	/* 16 - DNML | DZ | UFL */
427 	FPE_FLTINV,	/* 17 - INV | DNML | DZ | UFL */
428 	FPE_FLTOVF,	/* 18 - OFL | UFL */
429 	FPE_FLTINV,	/* 19 - INV | OFL | UFL */
430 	FPE_FLTUND,	/* 1A - DNML | OFL | UFL */
431 	FPE_FLTINV,	/* 1B - INV | DNML | OFL | UFL */
432 	FPE_FLTDIV,	/* 1C - DZ | OFL | UFL */
433 	FPE_FLTINV,	/* 1D - INV | DZ | OFL | UFL */
434 	FPE_FLTDIV,	/* 1E - DNML | DZ | OFL | UFL */
435 	FPE_FLTINV,	/* 1F - INV | DNML | DZ | OFL | UFL */
436 	FPE_FLTRES,	/* 20 - IMP */
437 	FPE_FLTINV,	/* 21 - INV | IMP */
438 	FPE_FLTUND,	/* 22 - DNML | IMP */
439 	FPE_FLTINV,	/* 23 - INV | DNML | IMP */
440 	FPE_FLTDIV,	/* 24 - DZ | IMP */
441 	FPE_FLTINV,	/* 25 - INV | DZ | IMP */
442 	FPE_FLTDIV,	/* 26 - DNML | DZ | IMP */
443 	FPE_FLTINV,	/* 27 - INV | DNML | DZ | IMP */
444 	FPE_FLTOVF,	/* 28 - OFL | IMP */
445 	FPE_FLTINV,	/* 29 - INV | OFL | IMP */
446 	FPE_FLTUND,	/* 2A - DNML | OFL | IMP */
447 	FPE_FLTINV,	/* 2B - INV | DNML | OFL | IMP */
448 	FPE_FLTDIV,	/* 2C - DZ | OFL | IMP */
449 	FPE_FLTINV,	/* 2D - INV | DZ | OFL | IMP */
450 	FPE_FLTDIV,	/* 2E - DNML | DZ | OFL | IMP */
451 	FPE_FLTINV,	/* 2F - INV | DNML | DZ | OFL | IMP */
452 	FPE_FLTUND,	/* 30 - UFL | IMP */
453 	FPE_FLTINV,	/* 31 - INV | UFL | IMP */
454 	FPE_FLTUND,	/* 32 - DNML | UFL | IMP */
455 	FPE_FLTINV,	/* 33 - INV | DNML | UFL | IMP */
456 	FPE_FLTDIV,	/* 34 - DZ | UFL | IMP */
457 	FPE_FLTINV,	/* 35 - INV | DZ | UFL | IMP */
458 	FPE_FLTDIV,	/* 36 - DNML | DZ | UFL | IMP */
459 	FPE_FLTINV,	/* 37 - INV | DNML | DZ | UFL | IMP */
460 	FPE_FLTOVF,	/* 38 - OFL | UFL | IMP */
461 	FPE_FLTINV,	/* 39 - INV | OFL | UFL | IMP */
462 	FPE_FLTUND,	/* 3A - DNML | OFL | UFL | IMP */
463 	FPE_FLTINV,	/* 3B - INV | DNML | OFL | UFL | IMP */
464 	FPE_FLTDIV,	/* 3C - DZ | OFL | UFL | IMP */
465 	FPE_FLTINV,	/* 3D - INV | DZ | OFL | UFL | IMP */
466 	FPE_FLTDIV,	/* 3E - DNML | DZ | OFL | UFL | IMP */
467 	FPE_FLTINV,	/* 3F - INV | DNML | DZ | OFL | UFL | IMP */
468 	FPE_FLTSUB,	/* 40 - STK */
469 	FPE_FLTSUB,	/* 41 - INV | STK */
470 	FPE_FLTUND,	/* 42 - DNML | STK */
471 	FPE_FLTSUB,	/* 43 - INV | DNML | STK */
472 	FPE_FLTDIV,	/* 44 - DZ | STK */
473 	FPE_FLTSUB,	/* 45 - INV | DZ | STK */
474 	FPE_FLTDIV,	/* 46 - DNML | DZ | STK */
475 	FPE_FLTSUB,	/* 47 - INV | DNML | DZ | STK */
476 	FPE_FLTOVF,	/* 48 - OFL | STK */
477 	FPE_FLTSUB,	/* 49 - INV | OFL | STK */
478 	FPE_FLTUND,	/* 4A - DNML | OFL | STK */
479 	FPE_FLTSUB,	/* 4B - INV | DNML | OFL | STK */
480 	FPE_FLTDIV,	/* 4C - DZ | OFL | STK */
481 	FPE_FLTSUB,	/* 4D - INV | DZ | OFL | STK */
482 	FPE_FLTDIV,	/* 4E - DNML | DZ | OFL | STK */
483 	FPE_FLTSUB,	/* 4F - INV | DNML | DZ | OFL | STK */
484 	FPE_FLTUND,	/* 50 - UFL | STK */
485 	FPE_FLTSUB,	/* 51 - INV | UFL | STK */
486 	FPE_FLTUND,	/* 52 - DNML | UFL | STK */
487 	FPE_FLTSUB,	/* 53 - INV | DNML | UFL | STK */
488 	FPE_FLTDIV,	/* 54 - DZ | UFL | STK */
489 	FPE_FLTSUB,	/* 55 - INV | DZ | UFL | STK */
490 	FPE_FLTDIV,	/* 56 - DNML | DZ | UFL | STK */
491 	FPE_FLTSUB,	/* 57 - INV | DNML | DZ | UFL | STK */
492 	FPE_FLTOVF,	/* 58 - OFL | UFL | STK */
493 	FPE_FLTSUB,	/* 59 - INV | OFL | UFL | STK */
494 	FPE_FLTUND,	/* 5A - DNML | OFL | UFL | STK */
495 	FPE_FLTSUB,	/* 5B - INV | DNML | OFL | UFL | STK */
496 	FPE_FLTDIV,	/* 5C - DZ | OFL | UFL | STK */
497 	FPE_FLTSUB,	/* 5D - INV | DZ | OFL | UFL | STK */
498 	FPE_FLTDIV,	/* 5E - DNML | DZ | OFL | UFL | STK */
499 	FPE_FLTSUB,	/* 5F - INV | DNML | DZ | OFL | UFL | STK */
500 	FPE_FLTRES,	/* 60 - IMP | STK */
501 	FPE_FLTSUB,	/* 61 - INV | IMP | STK */
502 	FPE_FLTUND,	/* 62 - DNML | IMP | STK */
503 	FPE_FLTSUB,	/* 63 - INV | DNML | IMP | STK */
504 	FPE_FLTDIV,	/* 64 - DZ | IMP | STK */
505 	FPE_FLTSUB,	/* 65 - INV | DZ | IMP | STK */
506 	FPE_FLTDIV,	/* 66 - DNML | DZ | IMP | STK */
507 	FPE_FLTSUB,	/* 67 - INV | DNML | DZ | IMP | STK */
508 	FPE_FLTOVF,	/* 68 - OFL | IMP | STK */
509 	FPE_FLTSUB,	/* 69 - INV | OFL | IMP | STK */
510 	FPE_FLTUND,	/* 6A - DNML | OFL | IMP | STK */
511 	FPE_FLTSUB,	/* 6B - INV | DNML | OFL | IMP | STK */
512 	FPE_FLTDIV,	/* 6C - DZ | OFL | IMP | STK */
513 	FPE_FLTSUB,	/* 6D - INV | DZ | OFL | IMP | STK */
514 	FPE_FLTDIV,	/* 6E - DNML | DZ | OFL | IMP | STK */
515 	FPE_FLTSUB,	/* 6F - INV | DNML | DZ | OFL | IMP | STK */
516 	FPE_FLTUND,	/* 70 - UFL | IMP | STK */
517 	FPE_FLTSUB,	/* 71 - INV | UFL | IMP | STK */
518 	FPE_FLTUND,	/* 72 - DNML | UFL | IMP | STK */
519 	FPE_FLTSUB,	/* 73 - INV | DNML | UFL | IMP | STK */
520 	FPE_FLTDIV,	/* 74 - DZ | UFL | IMP | STK */
521 	FPE_FLTSUB,	/* 75 - INV | DZ | UFL | IMP | STK */
522 	FPE_FLTDIV,	/* 76 - DNML | DZ | UFL | IMP | STK */
523 	FPE_FLTSUB,	/* 77 - INV | DNML | DZ | UFL | IMP | STK */
524 	FPE_FLTOVF,	/* 78 - OFL | UFL | IMP | STK */
525 	FPE_FLTSUB,	/* 79 - INV | OFL | UFL | IMP | STK */
526 	FPE_FLTUND,	/* 7A - DNML | OFL | UFL | IMP | STK */
527 	FPE_FLTSUB,	/* 7B - INV | DNML | OFL | UFL | IMP | STK */
528 	FPE_FLTDIV,	/* 7C - DZ | OFL | UFL | IMP | STK */
529 	FPE_FLTSUB,	/* 7D - INV | DZ | OFL | UFL | IMP | STK */
530 	FPE_FLTDIV,	/* 7E - DNML | DZ | OFL | UFL | IMP | STK */
531 	FPE_FLTSUB,	/* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */
532 };
533 
534 /*
535  * Read the FP status and control words, then generate si_code value
536  * for SIGFPE.  The error code chosen will be one of the
537  * FPE_... macros.  It will be sent as the second argument to old
538  * BSD-style signal handlers and as "siginfo_t->si_code" (second
539  * argument) to SA_SIGINFO signal handlers.
540  *
541  * Some time ago, we cleared the x87 exceptions with FNCLEX there.
542  * Clearing exceptions was necessary mainly to avoid IRQ13 bugs.  The
543  * usermode code which understands the FPU hardware enough to enable
544  * the exceptions, can also handle clearing the exception state in the
545  * handler.  The only consequence of not clearing the exception is the
546  * rethrow of the SIGFPE on return from the signal handler and
547  * reexecution of the corresponding instruction.
548  *
549  * For XMM traps, the exceptions were never cleared.
550  */
551 int
552 fputrap_x87(void)
553 {
554 	struct savefpu *pcb_save;
555 	u_short control, status;
556 
557 	critical_enter();
558 
559 	/*
560 	 * Interrupt handling (for another interrupt) may have pushed the
561 	 * state to memory.  Fetch the relevant parts of the state from
562 	 * wherever they are.
563 	 */
564 	if (PCPU_GET(fpcurthread) != curthread) {
565 		pcb_save = curpcb->pcb_save;
566 		control = pcb_save->sv_env.en_cw;
567 		status = pcb_save->sv_env.en_sw;
568 	} else {
569 		fnstcw(&control);
570 		fnstsw(&status);
571 	}
572 
573 	critical_exit();
574 	return (fpetable[status & ((~control & 0x3f) | 0x40)]);
575 }
576 
577 int
578 fputrap_sse(void)
579 {
580 	u_int mxcsr;
581 
582 	critical_enter();
583 	if (PCPU_GET(fpcurthread) != curthread)
584 		mxcsr = curpcb->pcb_save->sv_env.en_mxcsr;
585 	else
586 		stmxcsr(&mxcsr);
587 	critical_exit();
588 	return (fpetable[(mxcsr & (~mxcsr >> 7)) & 0x3f]);
589 }
590 
591 /*
592  * Implement device not available (DNA) exception
593  *
594  * It would be better to switch FP context here (if curthread != fpcurthread)
595  * and not necessarily for every context switch, but it is too hard to
596  * access foreign pcb's.
597  */
598 
599 static int err_count = 0;
600 
601 void
602 fpudna(void)
603 {
604 
605 	critical_enter();
606 	if (PCPU_GET(fpcurthread) == curthread) {
607 		printf("fpudna: fpcurthread == curthread %d times\n",
608 		    ++err_count);
609 		stop_emulating();
610 		critical_exit();
611 		return;
612 	}
613 	if (PCPU_GET(fpcurthread) != NULL) {
614 		printf("fpudna: fpcurthread = %p (%d), curthread = %p (%d)\n",
615 		       PCPU_GET(fpcurthread),
616 		       PCPU_GET(fpcurthread)->td_proc->p_pid,
617 		       curthread, curthread->td_proc->p_pid);
618 		panic("fpudna");
619 	}
620 	stop_emulating();
621 	/*
622 	 * Record new context early in case frstor causes a trap.
623 	 */
624 	PCPU_SET(fpcurthread, curthread);
625 
626 	fpu_clean_state();
627 
628 	if ((curpcb->pcb_flags & PCB_FPUINITDONE) == 0) {
629 		/*
630 		 * This is the first time this thread has used the FPU or
631 		 * the PCB doesn't contain a clean FPU state.  Explicitly
632 		 * load an initial state.
633 		 *
634 		 * We prefer to restore the state from the actual save
635 		 * area in PCB instead of directly loading from
636 		 * fpu_initialstate, to ignite the XSAVEOPT
637 		 * tracking engine.
638 		 */
639 		bcopy(fpu_initialstate, curpcb->pcb_save, cpu_max_ext_state_size);
640 		fpurestore(curpcb->pcb_save);
641 		if (curpcb->pcb_initial_fpucw != __INITIAL_FPUCW__)
642 			fldcw(curpcb->pcb_initial_fpucw);
643 		if (PCB_USER_FPU(curpcb))
644 			set_pcb_flags(curpcb,
645 			    PCB_FPUINITDONE | PCB_USERFPUINITDONE);
646 		else
647 			set_pcb_flags(curpcb, PCB_FPUINITDONE);
648 	} else
649 		fpurestore(curpcb->pcb_save);
650 	critical_exit();
651 }
652 
653 void
654 fpudrop()
655 {
656 	struct thread *td;
657 
658 	td = PCPU_GET(fpcurthread);
659 	KASSERT(td == curthread, ("fpudrop: fpcurthread != curthread"));
660 	CRITICAL_ASSERT(td);
661 	PCPU_SET(fpcurthread, NULL);
662 	clear_pcb_flags(td->td_pcb, PCB_FPUINITDONE);
663 	start_emulating();
664 }
665 
666 /*
667  * Get the user state of the FPU into pcb->pcb_user_save without
668  * dropping ownership (if possible).  It returns the FPU ownership
669  * status.
670  */
671 int
672 fpugetregs(struct thread *td)
673 {
674 	struct pcb *pcb;
675 	uint64_t *xstate_bv, bit;
676 	char *sa;
677 	int max_ext_n, i, owned;
678 
679 	pcb = td->td_pcb;
680 	if ((pcb->pcb_flags & PCB_USERFPUINITDONE) == 0) {
681 		bcopy(fpu_initialstate, get_pcb_user_save_pcb(pcb),
682 		    cpu_max_ext_state_size);
683 		get_pcb_user_save_pcb(pcb)->sv_env.en_cw =
684 		    pcb->pcb_initial_fpucw;
685 		fpuuserinited(td);
686 		return (_MC_FPOWNED_PCB);
687 	}
688 	critical_enter();
689 	if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) {
690 		fpusave(get_pcb_user_save_pcb(pcb));
691 		owned = _MC_FPOWNED_FPU;
692 	} else {
693 		owned = _MC_FPOWNED_PCB;
694 	}
695 	critical_exit();
696 	if (use_xsave) {
697 		/*
698 		 * Handle partially saved state.
699 		 */
700 		sa = (char *)get_pcb_user_save_pcb(pcb);
701 		xstate_bv = (uint64_t *)(sa + sizeof(struct savefpu) +
702 		    offsetof(struct xstate_hdr, xstate_bv));
703 		max_ext_n = flsl(xsave_mask);
704 		for (i = 0; i < max_ext_n; i++) {
705 			bit = 1ULL << i;
706 			if ((xsave_mask & bit) == 0 || (*xstate_bv & bit) != 0)
707 				continue;
708 			bcopy((char *)fpu_initialstate +
709 			    xsave_area_desc[i].offset,
710 			    sa + xsave_area_desc[i].offset,
711 			    xsave_area_desc[i].size);
712 			*xstate_bv |= bit;
713 		}
714 	}
715 	return (owned);
716 }
717 
718 void
719 fpuuserinited(struct thread *td)
720 {
721 	struct pcb *pcb;
722 
723 	pcb = td->td_pcb;
724 	if (PCB_USER_FPU(pcb))
725 		set_pcb_flags(pcb,
726 		    PCB_FPUINITDONE | PCB_USERFPUINITDONE);
727 	else
728 		set_pcb_flags(pcb, PCB_FPUINITDONE);
729 }
730 
731 int
732 fpusetxstate(struct thread *td, char *xfpustate, size_t xfpustate_size)
733 {
734 	struct xstate_hdr *hdr, *ehdr;
735 	size_t len, max_len;
736 	uint64_t bv;
737 
738 	/* XXXKIB should we clear all extended state in xstate_bv instead ? */
739 	if (xfpustate == NULL)
740 		return (0);
741 	if (!use_xsave)
742 		return (EOPNOTSUPP);
743 
744 	len = xfpustate_size;
745 	if (len < sizeof(struct xstate_hdr))
746 		return (EINVAL);
747 	max_len = cpu_max_ext_state_size - sizeof(struct savefpu);
748 	if (len > max_len)
749 		return (EINVAL);
750 
751 	ehdr = (struct xstate_hdr *)xfpustate;
752 	bv = ehdr->xstate_bv;
753 
754 	/*
755 	 * Avoid #gp.
756 	 */
757 	if (bv & ~xsave_mask)
758 		return (EINVAL);
759 
760 	hdr = (struct xstate_hdr *)(get_pcb_user_save_td(td) + 1);
761 
762 	hdr->xstate_bv = bv;
763 	bcopy(xfpustate + sizeof(struct xstate_hdr),
764 	    (char *)(hdr + 1), len - sizeof(struct xstate_hdr));
765 
766 	return (0);
767 }
768 
769 /*
770  * Set the state of the FPU.
771  */
772 int
773 fpusetregs(struct thread *td, struct savefpu *addr, char *xfpustate,
774     size_t xfpustate_size)
775 {
776 	struct pcb *pcb;
777 	int error;
778 
779 	pcb = td->td_pcb;
780 	critical_enter();
781 	if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) {
782 		error = fpusetxstate(td, xfpustate, xfpustate_size);
783 		if (error != 0) {
784 			critical_exit();
785 			return (error);
786 		}
787 		bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr));
788 		fpurestore(get_pcb_user_save_td(td));
789 		critical_exit();
790 		set_pcb_flags(pcb, PCB_FPUINITDONE | PCB_USERFPUINITDONE);
791 	} else {
792 		critical_exit();
793 		error = fpusetxstate(td, xfpustate, xfpustate_size);
794 		if (error != 0)
795 			return (error);
796 		bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr));
797 		fpuuserinited(td);
798 	}
799 	return (0);
800 }
801 
802 /*
803  * On AuthenticAMD processors, the fxrstor instruction does not restore
804  * the x87's stored last instruction pointer, last data pointer, and last
805  * opcode values, except in the rare case in which the exception summary
806  * (ES) bit in the x87 status word is set to 1.
807  *
808  * In order to avoid leaking this information across processes, we clean
809  * these values by performing a dummy load before executing fxrstor().
810  */
811 static void
812 fpu_clean_state(void)
813 {
814 	static float dummy_variable = 0.0;
815 	u_short status;
816 
817 	/*
818 	 * Clear the ES bit in the x87 status word if it is currently
819 	 * set, in order to avoid causing a fault in the upcoming load.
820 	 */
821 	fnstsw(&status);
822 	if (status & 0x80)
823 		fnclex();
824 
825 	/*
826 	 * Load the dummy variable into the x87 stack.  This mangles
827 	 * the x87 stack, but we don't care since we're about to call
828 	 * fxrstor() anyway.
829 	 */
830 	__asm __volatile("ffree %%st(7); flds %0" : : "m" (dummy_variable));
831 }
832 
833 /*
834  * This really sucks.  We want the acpi version only, but it requires
835  * the isa_if.h file in order to get the definitions.
836  */
837 #include "opt_isa.h"
838 #ifdef DEV_ISA
839 #include <isa/isavar.h>
840 /*
841  * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI.
842  */
843 static struct isa_pnp_id fpupnp_ids[] = {
844 	{ 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */
845 	{ 0 }
846 };
847 
848 static int
849 fpupnp_probe(device_t dev)
850 {
851 	int result;
852 
853 	result = ISA_PNP_PROBE(device_get_parent(dev), dev, fpupnp_ids);
854 	if (result <= 0)
855 		device_quiet(dev);
856 	return (result);
857 }
858 
859 static int
860 fpupnp_attach(device_t dev)
861 {
862 
863 	return (0);
864 }
865 
866 static device_method_t fpupnp_methods[] = {
867 	/* Device interface */
868 	DEVMETHOD(device_probe,		fpupnp_probe),
869 	DEVMETHOD(device_attach,	fpupnp_attach),
870 	DEVMETHOD(device_detach,	bus_generic_detach),
871 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
872 	DEVMETHOD(device_suspend,	bus_generic_suspend),
873 	DEVMETHOD(device_resume,	bus_generic_resume),
874 
875 	{ 0, 0 }
876 };
877 
878 static driver_t fpupnp_driver = {
879 	"fpupnp",
880 	fpupnp_methods,
881 	1,			/* no softc */
882 };
883 
884 static devclass_t fpupnp_devclass;
885 
886 DRIVER_MODULE(fpupnp, acpi, fpupnp_driver, fpupnp_devclass, 0, 0);
887 #endif	/* DEV_ISA */
888 
889 static MALLOC_DEFINE(M_FPUKERN_CTX, "fpukern_ctx",
890     "Kernel contexts for FPU state");
891 
892 #define	FPU_KERN_CTX_FPUINITDONE 0x01
893 #define	FPU_KERN_CTX_DUMMY	 0x02	/* avoided save for the kern thread */
894 
895 struct fpu_kern_ctx {
896 	struct savefpu *prev;
897 	uint32_t flags;
898 	char hwstate1[];
899 };
900 
901 struct fpu_kern_ctx *
902 fpu_kern_alloc_ctx(u_int flags)
903 {
904 	struct fpu_kern_ctx *res;
905 	size_t sz;
906 
907 	sz = sizeof(struct fpu_kern_ctx) + XSAVE_AREA_ALIGN +
908 	    cpu_max_ext_state_size;
909 	res = malloc(sz, M_FPUKERN_CTX, ((flags & FPU_KERN_NOWAIT) ?
910 	    M_NOWAIT : M_WAITOK) | M_ZERO);
911 	return (res);
912 }
913 
914 void
915 fpu_kern_free_ctx(struct fpu_kern_ctx *ctx)
916 {
917 
918 	/* XXXKIB clear the memory ? */
919 	free(ctx, M_FPUKERN_CTX);
920 }
921 
922 static struct savefpu *
923 fpu_kern_ctx_savefpu(struct fpu_kern_ctx *ctx)
924 {
925 	vm_offset_t p;
926 
927 	p = (vm_offset_t)&ctx->hwstate1;
928 	p = roundup2(p, XSAVE_AREA_ALIGN);
929 	return ((struct savefpu *)p);
930 }
931 
932 int
933 fpu_kern_enter(struct thread *td, struct fpu_kern_ctx *ctx, u_int flags)
934 {
935 	struct pcb *pcb;
936 
937 	if ((flags & FPU_KERN_KTHR) != 0 && is_fpu_kern_thread(0)) {
938 		ctx->flags = FPU_KERN_CTX_DUMMY;
939 		return (0);
940 	}
941 	pcb = td->td_pcb;
942 	KASSERT(!PCB_USER_FPU(pcb) || pcb->pcb_save ==
943 	    get_pcb_user_save_pcb(pcb), ("mangled pcb_save"));
944 	ctx->flags = 0;
945 	if ((pcb->pcb_flags & PCB_FPUINITDONE) != 0)
946 		ctx->flags |= FPU_KERN_CTX_FPUINITDONE;
947 	fpuexit(td);
948 	ctx->prev = pcb->pcb_save;
949 	pcb->pcb_save = fpu_kern_ctx_savefpu(ctx);
950 	set_pcb_flags(pcb, PCB_KERNFPU);
951 	clear_pcb_flags(pcb, PCB_FPUINITDONE);
952 	return (0);
953 }
954 
955 int
956 fpu_kern_leave(struct thread *td, struct fpu_kern_ctx *ctx)
957 {
958 	struct pcb *pcb;
959 
960 	if (is_fpu_kern_thread(0) && (ctx->flags & FPU_KERN_CTX_DUMMY) != 0)
961 		return (0);
962 	KASSERT((ctx->flags & FPU_KERN_CTX_DUMMY) == 0, ("dummy ctx"));
963 	pcb = td->td_pcb;
964 	critical_enter();
965 	if (curthread == PCPU_GET(fpcurthread))
966 		fpudrop();
967 	critical_exit();
968 	pcb->pcb_save = ctx->prev;
969 	if (pcb->pcb_save == get_pcb_user_save_pcb(pcb)) {
970 		if ((pcb->pcb_flags & PCB_USERFPUINITDONE) != 0) {
971 			set_pcb_flags(pcb, PCB_FPUINITDONE);
972 			clear_pcb_flags(pcb, PCB_KERNFPU);
973 		} else
974 			clear_pcb_flags(pcb, PCB_FPUINITDONE | PCB_KERNFPU);
975 	} else {
976 		if ((ctx->flags & FPU_KERN_CTX_FPUINITDONE) != 0)
977 			set_pcb_flags(pcb, PCB_FPUINITDONE);
978 		else
979 			clear_pcb_flags(pcb, PCB_FPUINITDONE);
980 		KASSERT(!PCB_USER_FPU(pcb), ("unpaired fpu_kern_leave"));
981 	}
982 	return (0);
983 }
984 
985 int
986 fpu_kern_thread(u_int flags)
987 {
988 
989 	KASSERT((curthread->td_pflags & TDP_KTHREAD) != 0,
990 	    ("Only kthread may use fpu_kern_thread"));
991 	KASSERT(curpcb->pcb_save == get_pcb_user_save_pcb(curpcb),
992 	    ("mangled pcb_save"));
993 	KASSERT(PCB_USER_FPU(curpcb), ("recursive call"));
994 
995 	set_pcb_flags(curpcb, PCB_KERNFPU);
996 	return (0);
997 }
998 
999 int
1000 is_fpu_kern_thread(u_int flags)
1001 {
1002 
1003 	if ((curthread->td_pflags & TDP_KTHREAD) == 0)
1004 		return (0);
1005 	return ((curpcb->pcb_flags & PCB_KERNFPU) != 0);
1006 }
1007 
1008 /*
1009  * FPU save area alloc/free/init utility routines
1010  */
1011 struct savefpu *
1012 fpu_save_area_alloc(void)
1013 {
1014 
1015 	return (uma_zalloc(fpu_save_area_zone, 0));
1016 }
1017 
1018 void
1019 fpu_save_area_free(struct savefpu *fsa)
1020 {
1021 
1022 	uma_zfree(fpu_save_area_zone, fsa);
1023 }
1024 
1025 void
1026 fpu_save_area_reset(struct savefpu *fsa)
1027 {
1028 
1029 	bcopy(fpu_initialstate, fsa, cpu_max_ext_state_size);
1030 }
1031