1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 1990 William Jolitz. 5 * Copyright (c) 1991 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of the University nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 33 */ 34 35 #include <sys/cdefs.h> 36 __FBSDID("$FreeBSD$"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/bus.h> 41 #include <sys/kernel.h> 42 #include <sys/lock.h> 43 #include <sys/malloc.h> 44 #include <sys/module.h> 45 #include <sys/mutex.h> 46 #include <sys/mutex.h> 47 #include <sys/proc.h> 48 #include <sys/sysctl.h> 49 #include <machine/bus.h> 50 #include <sys/rman.h> 51 #include <sys/signalvar.h> 52 #include <vm/uma.h> 53 54 #include <machine/cputypes.h> 55 #include <machine/frame.h> 56 #include <machine/intr_machdep.h> 57 #include <machine/md_var.h> 58 #include <machine/pcb.h> 59 #include <machine/psl.h> 60 #include <machine/resource.h> 61 #include <machine/specialreg.h> 62 #include <machine/segments.h> 63 #include <machine/ucontext.h> 64 #include <x86/ifunc.h> 65 66 /* 67 * Floating point support. 68 */ 69 70 #if defined(__GNUCLIKE_ASM) && !defined(lint) 71 72 #define fldcw(cw) __asm __volatile("fldcw %0" : : "m" (cw)) 73 #define fnclex() __asm __volatile("fnclex") 74 #define fninit() __asm __volatile("fninit") 75 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 76 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=am" (*(addr))) 77 #define fxrstor(addr) __asm __volatile("fxrstor %0" : : "m" (*(addr))) 78 #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 79 #define ldmxcsr(csr) __asm __volatile("ldmxcsr %0" : : "m" (csr)) 80 #define stmxcsr(addr) __asm __volatile("stmxcsr %0" : : "m" (*(addr))) 81 82 static __inline void 83 xrstor(char *addr, uint64_t mask) 84 { 85 uint32_t low, hi; 86 87 low = mask; 88 hi = mask >> 32; 89 __asm __volatile("xrstor %0" : : "m" (*addr), "a" (low), "d" (hi)); 90 } 91 92 static __inline void 93 xsave(char *addr, uint64_t mask) 94 { 95 uint32_t low, hi; 96 97 low = mask; 98 hi = mask >> 32; 99 __asm __volatile("xsave %0" : "=m" (*addr) : "a" (low), "d" (hi) : 100 "memory"); 101 } 102 103 #else /* !(__GNUCLIKE_ASM && !lint) */ 104 105 void fldcw(u_short cw); 106 void fnclex(void); 107 void fninit(void); 108 void fnstcw(caddr_t addr); 109 void fnstsw(caddr_t addr); 110 void fxsave(caddr_t addr); 111 void fxrstor(caddr_t addr); 112 void ldmxcsr(u_int csr); 113 void stmxcsr(u_int *csr); 114 void xrstor(char *addr, uint64_t mask); 115 void xsave(char *addr, uint64_t mask); 116 117 #endif /* __GNUCLIKE_ASM && !lint */ 118 119 #define start_emulating() load_cr0(rcr0() | CR0_TS) 120 #define stop_emulating() clts() 121 122 CTASSERT(sizeof(struct savefpu) == 512); 123 CTASSERT(sizeof(struct xstate_hdr) == 64); 124 CTASSERT(sizeof(struct savefpu_ymm) == 832); 125 126 /* 127 * This requirement is to make it easier for asm code to calculate 128 * offset of the fpu save area from the pcb address. FPU save area 129 * must be 64-byte aligned. 130 */ 131 CTASSERT(sizeof(struct pcb) % XSAVE_AREA_ALIGN == 0); 132 133 /* 134 * Ensure the copy of XCR0 saved in a core is contained in the padding 135 * area. 136 */ 137 CTASSERT(X86_XSTATE_XCR0_OFFSET >= offsetof(struct savefpu, sv_pad) && 138 X86_XSTATE_XCR0_OFFSET + sizeof(uint64_t) <= sizeof(struct savefpu)); 139 140 static void fpu_clean_state(void); 141 142 SYSCTL_INT(_hw, HW_FLOATINGPT, floatingpoint, CTLFLAG_RD, 143 SYSCTL_NULL_INT_PTR, 1, "Floating point instructions executed in hardware"); 144 145 int lazy_fpu_switch = 0; 146 SYSCTL_INT(_hw, OID_AUTO, lazy_fpu_switch, CTLFLAG_RWTUN | CTLFLAG_NOFETCH, 147 &lazy_fpu_switch, 0, 148 "Lazily load FPU context after context switch"); 149 150 int use_xsave; /* non-static for cpu_switch.S */ 151 uint64_t xsave_mask; /* the same */ 152 static uma_zone_t fpu_save_area_zone; 153 static struct savefpu *fpu_initialstate; 154 155 struct xsave_area_elm_descr { 156 u_int offset; 157 u_int size; 158 } *xsave_area_desc; 159 160 static void 161 fpusave_xsave(void *addr) 162 { 163 164 xsave((char *)addr, xsave_mask); 165 } 166 167 static void 168 fpurestore_xrstor(void *addr) 169 { 170 171 xrstor((char *)addr, xsave_mask); 172 } 173 174 static void 175 fpusave_fxsave(void *addr) 176 { 177 178 fxsave((char *)addr); 179 } 180 181 static void 182 fpurestore_fxrstor(void *addr) 183 { 184 185 fxrstor((char *)addr); 186 } 187 188 static void 189 init_xsave(void) 190 { 191 192 if (use_xsave) 193 return; 194 if ((cpu_feature2 & CPUID2_XSAVE) == 0) 195 return; 196 use_xsave = 1; 197 TUNABLE_INT_FETCH("hw.use_xsave", &use_xsave); 198 } 199 200 DEFINE_IFUNC(, void, fpusave, (void *), static) 201 { 202 203 init_xsave(); 204 return (use_xsave ? fpusave_xsave : fpusave_fxsave); 205 } 206 207 DEFINE_IFUNC(, void, fpurestore, (void *), static) 208 { 209 210 init_xsave(); 211 return (use_xsave ? fpurestore_xrstor : fpurestore_fxrstor); 212 } 213 214 void 215 fpususpend(void *addr) 216 { 217 u_long cr0; 218 219 cr0 = rcr0(); 220 stop_emulating(); 221 fpusave(addr); 222 load_cr0(cr0); 223 } 224 225 void 226 fpuresume(void *addr) 227 { 228 u_long cr0; 229 230 cr0 = rcr0(); 231 stop_emulating(); 232 fninit(); 233 if (use_xsave) 234 load_xcr(XCR0, xsave_mask); 235 fpurestore(addr); 236 load_cr0(cr0); 237 } 238 239 /* 240 * Enable XSAVE if supported and allowed by user. 241 * Calculate the xsave_mask. 242 */ 243 static void 244 fpuinit_bsp1(void) 245 { 246 u_int cp[4]; 247 uint64_t xsave_mask_user; 248 bool old_wp; 249 250 TUNABLE_INT_FETCH("hw.lazy_fpu_switch", &lazy_fpu_switch); 251 if (!use_xsave) 252 return; 253 cpuid_count(0xd, 0x0, cp); 254 xsave_mask = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE; 255 if ((cp[0] & xsave_mask) != xsave_mask) 256 panic("CPU0 does not support X87 or SSE: %x", cp[0]); 257 xsave_mask = ((uint64_t)cp[3] << 32) | cp[0]; 258 xsave_mask_user = xsave_mask; 259 TUNABLE_ULONG_FETCH("hw.xsave_mask", &xsave_mask_user); 260 xsave_mask_user |= XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE; 261 xsave_mask &= xsave_mask_user; 262 if ((xsave_mask & XFEATURE_AVX512) != XFEATURE_AVX512) 263 xsave_mask &= ~XFEATURE_AVX512; 264 if ((xsave_mask & XFEATURE_MPX) != XFEATURE_MPX) 265 xsave_mask &= ~XFEATURE_MPX; 266 267 cpuid_count(0xd, 0x1, cp); 268 if ((cp[0] & CPUID_EXTSTATE_XSAVEOPT) != 0) { 269 /* 270 * Patch the XSAVE instruction in the cpu_switch code 271 * to XSAVEOPT. We assume that XSAVE encoding used 272 * REX byte, and set the bit 4 of the r/m byte. 273 * 274 * It seems that some BIOSes give control to the OS 275 * with CR0.WP already set, making the kernel text 276 * read-only before cpu_startup(). 277 */ 278 old_wp = disable_wp(); 279 ctx_switch_xsave[3] |= 0x10; 280 restore_wp(old_wp); 281 } 282 } 283 284 /* 285 * Calculate the fpu save area size. 286 */ 287 static void 288 fpuinit_bsp2(void) 289 { 290 u_int cp[4]; 291 292 if (use_xsave) { 293 cpuid_count(0xd, 0x0, cp); 294 cpu_max_ext_state_size = cp[1]; 295 296 /* 297 * Reload the cpu_feature2, since we enabled OSXSAVE. 298 */ 299 do_cpuid(1, cp); 300 cpu_feature2 = cp[2]; 301 } else 302 cpu_max_ext_state_size = sizeof(struct savefpu); 303 } 304 305 /* 306 * Initialize the floating point unit. 307 */ 308 void 309 fpuinit(void) 310 { 311 register_t saveintr; 312 u_int mxcsr; 313 u_short control; 314 315 if (IS_BSP()) 316 fpuinit_bsp1(); 317 318 if (use_xsave) { 319 load_cr4(rcr4() | CR4_XSAVE); 320 load_xcr(XCR0, xsave_mask); 321 } 322 323 /* 324 * XCR0 shall be set up before CPU can report the save area size. 325 */ 326 if (IS_BSP()) 327 fpuinit_bsp2(); 328 329 /* 330 * It is too early for critical_enter() to work on AP. 331 */ 332 saveintr = intr_disable(); 333 stop_emulating(); 334 fninit(); 335 control = __INITIAL_FPUCW__; 336 fldcw(control); 337 mxcsr = __INITIAL_MXCSR__; 338 ldmxcsr(mxcsr); 339 start_emulating(); 340 intr_restore(saveintr); 341 } 342 343 /* 344 * On the boot CPU we generate a clean state that is used to 345 * initialize the floating point unit when it is first used by a 346 * process. 347 */ 348 static void 349 fpuinitstate(void *arg __unused) 350 { 351 register_t saveintr; 352 int cp[4], i, max_ext_n; 353 354 fpu_initialstate = malloc(cpu_max_ext_state_size, M_DEVBUF, 355 M_WAITOK | M_ZERO); 356 saveintr = intr_disable(); 357 stop_emulating(); 358 359 fpusave(fpu_initialstate); 360 if (fpu_initialstate->sv_env.en_mxcsr_mask) 361 cpu_mxcsr_mask = fpu_initialstate->sv_env.en_mxcsr_mask; 362 else 363 cpu_mxcsr_mask = 0xFFBF; 364 365 /* 366 * The fninit instruction does not modify XMM registers or x87 367 * registers (MM/ST). The fpusave call dumped the garbage 368 * contained in the registers after reset to the initial state 369 * saved. Clear XMM and x87 registers file image to make the 370 * startup program state and signal handler XMM/x87 register 371 * content predictable. 372 */ 373 bzero(fpu_initialstate->sv_fp, sizeof(fpu_initialstate->sv_fp)); 374 bzero(fpu_initialstate->sv_xmm, sizeof(fpu_initialstate->sv_xmm)); 375 376 /* 377 * Create a table describing the layout of the CPU Extended 378 * Save Area. 379 */ 380 if (use_xsave) { 381 max_ext_n = flsl(xsave_mask); 382 xsave_area_desc = malloc(max_ext_n * sizeof(struct 383 xsave_area_elm_descr), M_DEVBUF, M_WAITOK | M_ZERO); 384 /* x87 state */ 385 xsave_area_desc[0].offset = 0; 386 xsave_area_desc[0].size = 160; 387 /* XMM */ 388 xsave_area_desc[1].offset = 160; 389 xsave_area_desc[1].size = 288 - 160; 390 391 for (i = 2; i < max_ext_n; i++) { 392 cpuid_count(0xd, i, cp); 393 xsave_area_desc[i].offset = cp[1]; 394 xsave_area_desc[i].size = cp[0]; 395 } 396 } 397 398 fpu_save_area_zone = uma_zcreate("FPU_save_area", 399 cpu_max_ext_state_size, NULL, NULL, NULL, NULL, 400 XSAVE_AREA_ALIGN - 1, 0); 401 402 start_emulating(); 403 intr_restore(saveintr); 404 } 405 /* EFIRT needs this to be initialized before we can enter our EFI environment */ 406 SYSINIT(fpuinitstate, SI_SUB_DRIVERS, SI_ORDER_FIRST, fpuinitstate, NULL); 407 408 /* 409 * Free coprocessor (if we have it). 410 */ 411 void 412 fpuexit(struct thread *td) 413 { 414 415 critical_enter(); 416 if (curthread == PCPU_GET(fpcurthread)) { 417 stop_emulating(); 418 fpusave(curpcb->pcb_save); 419 start_emulating(); 420 PCPU_SET(fpcurthread, NULL); 421 } 422 critical_exit(); 423 } 424 425 int 426 fpuformat(void) 427 { 428 429 return (_MC_FPFMT_XMM); 430 } 431 432 /* 433 * The following mechanism is used to ensure that the FPE_... value 434 * that is passed as a trapcode to the signal handler of the user 435 * process does not have more than one bit set. 436 * 437 * Multiple bits may be set if the user process modifies the control 438 * word while a status word bit is already set. While this is a sign 439 * of bad coding, we have no choise than to narrow them down to one 440 * bit, since we must not send a trapcode that is not exactly one of 441 * the FPE_ macros. 442 * 443 * The mechanism has a static table with 127 entries. Each combination 444 * of the 7 FPU status word exception bits directly translates to a 445 * position in this table, where a single FPE_... value is stored. 446 * This FPE_... value stored there is considered the "most important" 447 * of the exception bits and will be sent as the signal code. The 448 * precedence of the bits is based upon Intel Document "Numerical 449 * Applications", Chapter "Special Computational Situations". 450 * 451 * The macro to choose one of these values does these steps: 1) Throw 452 * away status word bits that cannot be masked. 2) Throw away the bits 453 * currently masked in the control word, assuming the user isn't 454 * interested in them anymore. 3) Reinsert status word bit 7 (stack 455 * fault) if it is set, which cannot be masked but must be presered. 456 * 4) Use the remaining bits to point into the trapcode table. 457 * 458 * The 6 maskable bits in order of their preference, as stated in the 459 * above referenced Intel manual: 460 * 1 Invalid operation (FP_X_INV) 461 * 1a Stack underflow 462 * 1b Stack overflow 463 * 1c Operand of unsupported format 464 * 1d SNaN operand. 465 * 2 QNaN operand (not an exception, irrelavant here) 466 * 3 Any other invalid-operation not mentioned above or zero divide 467 * (FP_X_INV, FP_X_DZ) 468 * 4 Denormal operand (FP_X_DNML) 469 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 470 * 6 Inexact result (FP_X_IMP) 471 */ 472 static char fpetable[128] = { 473 0, 474 FPE_FLTINV, /* 1 - INV */ 475 FPE_FLTUND, /* 2 - DNML */ 476 FPE_FLTINV, /* 3 - INV | DNML */ 477 FPE_FLTDIV, /* 4 - DZ */ 478 FPE_FLTINV, /* 5 - INV | DZ */ 479 FPE_FLTDIV, /* 6 - DNML | DZ */ 480 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 481 FPE_FLTOVF, /* 8 - OFL */ 482 FPE_FLTINV, /* 9 - INV | OFL */ 483 FPE_FLTUND, /* A - DNML | OFL */ 484 FPE_FLTINV, /* B - INV | DNML | OFL */ 485 FPE_FLTDIV, /* C - DZ | OFL */ 486 FPE_FLTINV, /* D - INV | DZ | OFL */ 487 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 488 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 489 FPE_FLTUND, /* 10 - UFL */ 490 FPE_FLTINV, /* 11 - INV | UFL */ 491 FPE_FLTUND, /* 12 - DNML | UFL */ 492 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 493 FPE_FLTDIV, /* 14 - DZ | UFL */ 494 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 495 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 496 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 497 FPE_FLTOVF, /* 18 - OFL | UFL */ 498 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 499 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 500 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 501 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 502 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 503 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 504 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 505 FPE_FLTRES, /* 20 - IMP */ 506 FPE_FLTINV, /* 21 - INV | IMP */ 507 FPE_FLTUND, /* 22 - DNML | IMP */ 508 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 509 FPE_FLTDIV, /* 24 - DZ | IMP */ 510 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 511 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 512 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 513 FPE_FLTOVF, /* 28 - OFL | IMP */ 514 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 515 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 516 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 517 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 518 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 519 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 520 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 521 FPE_FLTUND, /* 30 - UFL | IMP */ 522 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 523 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 524 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 525 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 526 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 527 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 528 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 529 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 530 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 531 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 532 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 533 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 534 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 535 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 536 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 537 FPE_FLTSUB, /* 40 - STK */ 538 FPE_FLTSUB, /* 41 - INV | STK */ 539 FPE_FLTUND, /* 42 - DNML | STK */ 540 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 541 FPE_FLTDIV, /* 44 - DZ | STK */ 542 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 543 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 544 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 545 FPE_FLTOVF, /* 48 - OFL | STK */ 546 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 547 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 548 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 549 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 550 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 551 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 552 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 553 FPE_FLTUND, /* 50 - UFL | STK */ 554 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 555 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 556 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 557 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 558 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 559 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 560 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 561 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 562 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 563 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 564 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 565 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 566 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 567 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 568 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 569 FPE_FLTRES, /* 60 - IMP | STK */ 570 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 571 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 572 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 573 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 574 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 575 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 576 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 577 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 578 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 579 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 580 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 581 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 582 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 583 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 584 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 585 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 586 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 587 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 588 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 589 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 590 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 591 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 592 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 593 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 594 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 595 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 596 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 597 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 598 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 599 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 600 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 601 }; 602 603 /* 604 * Read the FP status and control words, then generate si_code value 605 * for SIGFPE. The error code chosen will be one of the 606 * FPE_... macros. It will be sent as the second argument to old 607 * BSD-style signal handlers and as "siginfo_t->si_code" (second 608 * argument) to SA_SIGINFO signal handlers. 609 * 610 * Some time ago, we cleared the x87 exceptions with FNCLEX there. 611 * Clearing exceptions was necessary mainly to avoid IRQ13 bugs. The 612 * usermode code which understands the FPU hardware enough to enable 613 * the exceptions, can also handle clearing the exception state in the 614 * handler. The only consequence of not clearing the exception is the 615 * rethrow of the SIGFPE on return from the signal handler and 616 * reexecution of the corresponding instruction. 617 * 618 * For XMM traps, the exceptions were never cleared. 619 */ 620 int 621 fputrap_x87(void) 622 { 623 struct savefpu *pcb_save; 624 u_short control, status; 625 626 critical_enter(); 627 628 /* 629 * Interrupt handling (for another interrupt) may have pushed the 630 * state to memory. Fetch the relevant parts of the state from 631 * wherever they are. 632 */ 633 if (PCPU_GET(fpcurthread) != curthread) { 634 pcb_save = curpcb->pcb_save; 635 control = pcb_save->sv_env.en_cw; 636 status = pcb_save->sv_env.en_sw; 637 } else { 638 fnstcw(&control); 639 fnstsw(&status); 640 } 641 642 critical_exit(); 643 return (fpetable[status & ((~control & 0x3f) | 0x40)]); 644 } 645 646 int 647 fputrap_sse(void) 648 { 649 u_int mxcsr; 650 651 critical_enter(); 652 if (PCPU_GET(fpcurthread) != curthread) 653 mxcsr = curpcb->pcb_save->sv_env.en_mxcsr; 654 else 655 stmxcsr(&mxcsr); 656 critical_exit(); 657 return (fpetable[(mxcsr & (~mxcsr >> 7)) & 0x3f]); 658 } 659 660 static void 661 restore_fpu_curthread(struct thread *td) 662 { 663 struct pcb *pcb; 664 665 /* 666 * Record new context early in case frstor causes a trap. 667 */ 668 PCPU_SET(fpcurthread, td); 669 670 stop_emulating(); 671 fpu_clean_state(); 672 pcb = td->td_pcb; 673 674 if ((pcb->pcb_flags & PCB_FPUINITDONE) == 0) { 675 /* 676 * This is the first time this thread has used the FPU or 677 * the PCB doesn't contain a clean FPU state. Explicitly 678 * load an initial state. 679 * 680 * We prefer to restore the state from the actual save 681 * area in PCB instead of directly loading from 682 * fpu_initialstate, to ignite the XSAVEOPT 683 * tracking engine. 684 */ 685 bcopy(fpu_initialstate, pcb->pcb_save, 686 cpu_max_ext_state_size); 687 fpurestore(pcb->pcb_save); 688 if (pcb->pcb_initial_fpucw != __INITIAL_FPUCW__) 689 fldcw(pcb->pcb_initial_fpucw); 690 if (PCB_USER_FPU(pcb)) 691 set_pcb_flags(pcb, PCB_FPUINITDONE | 692 PCB_USERFPUINITDONE); 693 else 694 set_pcb_flags(pcb, PCB_FPUINITDONE); 695 } else 696 fpurestore(pcb->pcb_save); 697 } 698 699 /* 700 * Device Not Available (DNA, #NM) exception handler. 701 * 702 * It would be better to switch FP context here (if curthread != 703 * fpcurthread) and not necessarily for every context switch, but it 704 * is too hard to access foreign pcb's. 705 */ 706 void 707 fpudna(void) 708 { 709 struct thread *td; 710 711 td = curthread; 712 /* 713 * This handler is entered with interrupts enabled, so context 714 * switches may occur before critical_enter() is executed. If 715 * a context switch occurs, then when we regain control, our 716 * state will have been completely restored. The CPU may 717 * change underneath us, but the only part of our context that 718 * lives in the CPU is CR0.TS and that will be "restored" by 719 * setting it on the new CPU. 720 */ 721 critical_enter(); 722 723 KASSERT((curpcb->pcb_flags & PCB_FPUNOSAVE) == 0, 724 ("fpudna while in fpu_kern_enter(FPU_KERN_NOCTX)")); 725 if (__predict_false(PCPU_GET(fpcurthread) == td)) { 726 /* 727 * Some virtual machines seems to set %cr0.TS at 728 * arbitrary moments. Silently clear the TS bit 729 * regardless of the eager/lazy FPU context switch 730 * mode. 731 */ 732 stop_emulating(); 733 } else { 734 if (__predict_false(PCPU_GET(fpcurthread) != NULL)) { 735 panic( 736 "fpudna: fpcurthread = %p (%d), curthread = %p (%d)\n", 737 PCPU_GET(fpcurthread), 738 PCPU_GET(fpcurthread)->td_tid, td, td->td_tid); 739 } 740 restore_fpu_curthread(td); 741 } 742 critical_exit(); 743 } 744 745 void fpu_activate_sw(struct thread *td); /* Called from the context switch */ 746 void 747 fpu_activate_sw(struct thread *td) 748 { 749 750 if (lazy_fpu_switch || (td->td_pflags & TDP_KTHREAD) != 0 || 751 !PCB_USER_FPU(td->td_pcb)) { 752 PCPU_SET(fpcurthread, NULL); 753 start_emulating(); 754 } else if (PCPU_GET(fpcurthread) != td) { 755 restore_fpu_curthread(td); 756 } 757 } 758 759 void 760 fpudrop(void) 761 { 762 struct thread *td; 763 764 td = PCPU_GET(fpcurthread); 765 KASSERT(td == curthread, ("fpudrop: fpcurthread != curthread")); 766 CRITICAL_ASSERT(td); 767 PCPU_SET(fpcurthread, NULL); 768 clear_pcb_flags(td->td_pcb, PCB_FPUINITDONE); 769 start_emulating(); 770 } 771 772 /* 773 * Get the user state of the FPU into pcb->pcb_user_save without 774 * dropping ownership (if possible). It returns the FPU ownership 775 * status. 776 */ 777 int 778 fpugetregs(struct thread *td) 779 { 780 struct pcb *pcb; 781 uint64_t *xstate_bv, bit; 782 char *sa; 783 int max_ext_n, i, owned; 784 785 pcb = td->td_pcb; 786 critical_enter(); 787 if ((pcb->pcb_flags & PCB_USERFPUINITDONE) == 0) { 788 bcopy(fpu_initialstate, get_pcb_user_save_pcb(pcb), 789 cpu_max_ext_state_size); 790 get_pcb_user_save_pcb(pcb)->sv_env.en_cw = 791 pcb->pcb_initial_fpucw; 792 fpuuserinited(td); 793 critical_exit(); 794 return (_MC_FPOWNED_PCB); 795 } 796 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) { 797 fpusave(get_pcb_user_save_pcb(pcb)); 798 owned = _MC_FPOWNED_FPU; 799 } else { 800 owned = _MC_FPOWNED_PCB; 801 } 802 if (use_xsave) { 803 /* 804 * Handle partially saved state. 805 */ 806 sa = (char *)get_pcb_user_save_pcb(pcb); 807 xstate_bv = (uint64_t *)(sa + sizeof(struct savefpu) + 808 offsetof(struct xstate_hdr, xstate_bv)); 809 max_ext_n = flsl(xsave_mask); 810 for (i = 0; i < max_ext_n; i++) { 811 bit = 1ULL << i; 812 if ((xsave_mask & bit) == 0 || (*xstate_bv & bit) != 0) 813 continue; 814 bcopy((char *)fpu_initialstate + 815 xsave_area_desc[i].offset, 816 sa + xsave_area_desc[i].offset, 817 xsave_area_desc[i].size); 818 *xstate_bv |= bit; 819 } 820 } 821 critical_exit(); 822 return (owned); 823 } 824 825 void 826 fpuuserinited(struct thread *td) 827 { 828 struct pcb *pcb; 829 830 CRITICAL_ASSERT(td); 831 pcb = td->td_pcb; 832 if (PCB_USER_FPU(pcb)) 833 set_pcb_flags(pcb, 834 PCB_FPUINITDONE | PCB_USERFPUINITDONE); 835 else 836 set_pcb_flags(pcb, PCB_FPUINITDONE); 837 } 838 839 int 840 fpusetxstate(struct thread *td, char *xfpustate, size_t xfpustate_size) 841 { 842 struct xstate_hdr *hdr, *ehdr; 843 size_t len, max_len; 844 uint64_t bv; 845 846 /* XXXKIB should we clear all extended state in xstate_bv instead ? */ 847 if (xfpustate == NULL) 848 return (0); 849 if (!use_xsave) 850 return (EOPNOTSUPP); 851 852 len = xfpustate_size; 853 if (len < sizeof(struct xstate_hdr)) 854 return (EINVAL); 855 max_len = cpu_max_ext_state_size - sizeof(struct savefpu); 856 if (len > max_len) 857 return (EINVAL); 858 859 ehdr = (struct xstate_hdr *)xfpustate; 860 bv = ehdr->xstate_bv; 861 862 /* 863 * Avoid #gp. 864 */ 865 if (bv & ~xsave_mask) 866 return (EINVAL); 867 868 hdr = (struct xstate_hdr *)(get_pcb_user_save_td(td) + 1); 869 870 hdr->xstate_bv = bv; 871 bcopy(xfpustate + sizeof(struct xstate_hdr), 872 (char *)(hdr + 1), len - sizeof(struct xstate_hdr)); 873 874 return (0); 875 } 876 877 /* 878 * Set the state of the FPU. 879 */ 880 int 881 fpusetregs(struct thread *td, struct savefpu *addr, char *xfpustate, 882 size_t xfpustate_size) 883 { 884 struct pcb *pcb; 885 int error; 886 887 addr->sv_env.en_mxcsr &= cpu_mxcsr_mask; 888 pcb = td->td_pcb; 889 error = 0; 890 critical_enter(); 891 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) { 892 error = fpusetxstate(td, xfpustate, xfpustate_size); 893 if (error == 0) { 894 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr)); 895 fpurestore(get_pcb_user_save_td(td)); 896 set_pcb_flags(pcb, PCB_FPUINITDONE | 897 PCB_USERFPUINITDONE); 898 } 899 } else { 900 error = fpusetxstate(td, xfpustate, xfpustate_size); 901 if (error == 0) { 902 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr)); 903 fpuuserinited(td); 904 } 905 } 906 critical_exit(); 907 return (error); 908 } 909 910 /* 911 * On AuthenticAMD processors, the fxrstor instruction does not restore 912 * the x87's stored last instruction pointer, last data pointer, and last 913 * opcode values, except in the rare case in which the exception summary 914 * (ES) bit in the x87 status word is set to 1. 915 * 916 * In order to avoid leaking this information across processes, we clean 917 * these values by performing a dummy load before executing fxrstor(). 918 */ 919 static void 920 fpu_clean_state(void) 921 { 922 static float dummy_variable = 0.0; 923 u_short status; 924 925 /* 926 * Clear the ES bit in the x87 status word if it is currently 927 * set, in order to avoid causing a fault in the upcoming load. 928 */ 929 fnstsw(&status); 930 if (status & 0x80) 931 fnclex(); 932 933 /* 934 * Load the dummy variable into the x87 stack. This mangles 935 * the x87 stack, but we don't care since we're about to call 936 * fxrstor() anyway. 937 */ 938 __asm __volatile("ffree %%st(7); flds %0" : : "m" (dummy_variable)); 939 } 940 941 /* 942 * This really sucks. We want the acpi version only, but it requires 943 * the isa_if.h file in order to get the definitions. 944 */ 945 #include "opt_isa.h" 946 #ifdef DEV_ISA 947 #include <isa/isavar.h> 948 /* 949 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI. 950 */ 951 static struct isa_pnp_id fpupnp_ids[] = { 952 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */ 953 { 0 } 954 }; 955 956 static int 957 fpupnp_probe(device_t dev) 958 { 959 int result; 960 961 result = ISA_PNP_PROBE(device_get_parent(dev), dev, fpupnp_ids); 962 if (result <= 0) 963 device_quiet(dev); 964 return (result); 965 } 966 967 static int 968 fpupnp_attach(device_t dev) 969 { 970 971 return (0); 972 } 973 974 static device_method_t fpupnp_methods[] = { 975 /* Device interface */ 976 DEVMETHOD(device_probe, fpupnp_probe), 977 DEVMETHOD(device_attach, fpupnp_attach), 978 DEVMETHOD(device_detach, bus_generic_detach), 979 DEVMETHOD(device_shutdown, bus_generic_shutdown), 980 DEVMETHOD(device_suspend, bus_generic_suspend), 981 DEVMETHOD(device_resume, bus_generic_resume), 982 983 { 0, 0 } 984 }; 985 986 static driver_t fpupnp_driver = { 987 "fpupnp", 988 fpupnp_methods, 989 1, /* no softc */ 990 }; 991 992 static devclass_t fpupnp_devclass; 993 994 DRIVER_MODULE(fpupnp, acpi, fpupnp_driver, fpupnp_devclass, 0, 0); 995 ISA_PNP_INFO(fpupnp_ids); 996 #endif /* DEV_ISA */ 997 998 static MALLOC_DEFINE(M_FPUKERN_CTX, "fpukern_ctx", 999 "Kernel contexts for FPU state"); 1000 1001 #define FPU_KERN_CTX_FPUINITDONE 0x01 1002 #define FPU_KERN_CTX_DUMMY 0x02 /* avoided save for the kern thread */ 1003 #define FPU_KERN_CTX_INUSE 0x04 1004 1005 struct fpu_kern_ctx { 1006 struct savefpu *prev; 1007 uint32_t flags; 1008 char hwstate1[]; 1009 }; 1010 1011 struct fpu_kern_ctx * 1012 fpu_kern_alloc_ctx(u_int flags) 1013 { 1014 struct fpu_kern_ctx *res; 1015 size_t sz; 1016 1017 sz = sizeof(struct fpu_kern_ctx) + XSAVE_AREA_ALIGN + 1018 cpu_max_ext_state_size; 1019 res = malloc(sz, M_FPUKERN_CTX, ((flags & FPU_KERN_NOWAIT) ? 1020 M_NOWAIT : M_WAITOK) | M_ZERO); 1021 return (res); 1022 } 1023 1024 void 1025 fpu_kern_free_ctx(struct fpu_kern_ctx *ctx) 1026 { 1027 1028 KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) == 0, ("free'ing inuse ctx")); 1029 /* XXXKIB clear the memory ? */ 1030 free(ctx, M_FPUKERN_CTX); 1031 } 1032 1033 static struct savefpu * 1034 fpu_kern_ctx_savefpu(struct fpu_kern_ctx *ctx) 1035 { 1036 vm_offset_t p; 1037 1038 p = (vm_offset_t)&ctx->hwstate1; 1039 p = roundup2(p, XSAVE_AREA_ALIGN); 1040 return ((struct savefpu *)p); 1041 } 1042 1043 void 1044 fpu_kern_enter(struct thread *td, struct fpu_kern_ctx *ctx, u_int flags) 1045 { 1046 struct pcb *pcb; 1047 1048 pcb = td->td_pcb; 1049 KASSERT((flags & FPU_KERN_NOCTX) != 0 || ctx != NULL, 1050 ("ctx is required when !FPU_KERN_NOCTX")); 1051 KASSERT(ctx == NULL || (ctx->flags & FPU_KERN_CTX_INUSE) == 0, 1052 ("using inuse ctx")); 1053 KASSERT((pcb->pcb_flags & PCB_FPUNOSAVE) == 0, 1054 ("recursive fpu_kern_enter while in PCB_FPUNOSAVE state")); 1055 1056 if ((flags & FPU_KERN_NOCTX) != 0) { 1057 critical_enter(); 1058 stop_emulating(); 1059 if (curthread == PCPU_GET(fpcurthread)) { 1060 fpusave(curpcb->pcb_save); 1061 PCPU_SET(fpcurthread, NULL); 1062 } else { 1063 KASSERT(PCPU_GET(fpcurthread) == NULL, 1064 ("invalid fpcurthread")); 1065 } 1066 1067 /* 1068 * This breaks XSAVEOPT tracker, but 1069 * PCB_FPUNOSAVE state is supposed to never need to 1070 * save FPU context at all. 1071 */ 1072 fpurestore(fpu_initialstate); 1073 set_pcb_flags(pcb, PCB_KERNFPU | PCB_FPUNOSAVE | 1074 PCB_FPUINITDONE); 1075 return; 1076 } 1077 if ((flags & FPU_KERN_KTHR) != 0 && is_fpu_kern_thread(0)) { 1078 ctx->flags = FPU_KERN_CTX_DUMMY | FPU_KERN_CTX_INUSE; 1079 return; 1080 } 1081 critical_enter(); 1082 KASSERT(!PCB_USER_FPU(pcb) || pcb->pcb_save == 1083 get_pcb_user_save_pcb(pcb), ("mangled pcb_save")); 1084 ctx->flags = FPU_KERN_CTX_INUSE; 1085 if ((pcb->pcb_flags & PCB_FPUINITDONE) != 0) 1086 ctx->flags |= FPU_KERN_CTX_FPUINITDONE; 1087 fpuexit(td); 1088 ctx->prev = pcb->pcb_save; 1089 pcb->pcb_save = fpu_kern_ctx_savefpu(ctx); 1090 set_pcb_flags(pcb, PCB_KERNFPU); 1091 clear_pcb_flags(pcb, PCB_FPUINITDONE); 1092 critical_exit(); 1093 } 1094 1095 int 1096 fpu_kern_leave(struct thread *td, struct fpu_kern_ctx *ctx) 1097 { 1098 struct pcb *pcb; 1099 1100 pcb = td->td_pcb; 1101 1102 if ((pcb->pcb_flags & PCB_FPUNOSAVE) != 0) { 1103 KASSERT(ctx == NULL, ("non-null ctx after FPU_KERN_NOCTX")); 1104 KASSERT(PCPU_GET(fpcurthread) == NULL, 1105 ("non-NULL fpcurthread for PCB_FPUNOSAVE")); 1106 CRITICAL_ASSERT(td); 1107 1108 clear_pcb_flags(pcb, PCB_FPUNOSAVE | PCB_FPUINITDONE); 1109 start_emulating(); 1110 } else { 1111 KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) != 0, 1112 ("leaving not inuse ctx")); 1113 ctx->flags &= ~FPU_KERN_CTX_INUSE; 1114 1115 if (is_fpu_kern_thread(0) && 1116 (ctx->flags & FPU_KERN_CTX_DUMMY) != 0) 1117 return (0); 1118 KASSERT((ctx->flags & FPU_KERN_CTX_DUMMY) == 0, 1119 ("dummy ctx")); 1120 critical_enter(); 1121 if (curthread == PCPU_GET(fpcurthread)) 1122 fpudrop(); 1123 pcb->pcb_save = ctx->prev; 1124 } 1125 1126 if (pcb->pcb_save == get_pcb_user_save_pcb(pcb)) { 1127 if ((pcb->pcb_flags & PCB_USERFPUINITDONE) != 0) { 1128 set_pcb_flags(pcb, PCB_FPUINITDONE); 1129 clear_pcb_flags(pcb, PCB_KERNFPU); 1130 } else 1131 clear_pcb_flags(pcb, PCB_FPUINITDONE | PCB_KERNFPU); 1132 } else { 1133 if ((ctx->flags & FPU_KERN_CTX_FPUINITDONE) != 0) 1134 set_pcb_flags(pcb, PCB_FPUINITDONE); 1135 else 1136 clear_pcb_flags(pcb, PCB_FPUINITDONE); 1137 KASSERT(!PCB_USER_FPU(pcb), ("unpaired fpu_kern_leave")); 1138 } 1139 critical_exit(); 1140 return (0); 1141 } 1142 1143 int 1144 fpu_kern_thread(u_int flags) 1145 { 1146 1147 KASSERT((curthread->td_pflags & TDP_KTHREAD) != 0, 1148 ("Only kthread may use fpu_kern_thread")); 1149 KASSERT(curpcb->pcb_save == get_pcb_user_save_pcb(curpcb), 1150 ("mangled pcb_save")); 1151 KASSERT(PCB_USER_FPU(curpcb), ("recursive call")); 1152 1153 set_pcb_flags(curpcb, PCB_KERNFPU); 1154 return (0); 1155 } 1156 1157 int 1158 is_fpu_kern_thread(u_int flags) 1159 { 1160 1161 if ((curthread->td_pflags & TDP_KTHREAD) == 0) 1162 return (0); 1163 return ((curpcb->pcb_flags & PCB_KERNFPU) != 0); 1164 } 1165 1166 /* 1167 * FPU save area alloc/free/init utility routines 1168 */ 1169 struct savefpu * 1170 fpu_save_area_alloc(void) 1171 { 1172 1173 return (uma_zalloc(fpu_save_area_zone, 0)); 1174 } 1175 1176 void 1177 fpu_save_area_free(struct savefpu *fsa) 1178 { 1179 1180 uma_zfree(fpu_save_area_zone, fsa); 1181 } 1182 1183 void 1184 fpu_save_area_reset(struct savefpu *fsa) 1185 { 1186 1187 bcopy(fpu_initialstate, fsa, cpu_max_ext_state_size); 1188 } 1189