1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 1990 William Jolitz. 5 * Copyright (c) 1991 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of the University nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 33 */ 34 35 #include <sys/cdefs.h> 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/bus.h> 39 #include <sys/domainset.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/malloc.h> 43 #include <sys/module.h> 44 #include <sys/mutex.h> 45 #include <sys/mutex.h> 46 #include <sys/proc.h> 47 #include <sys/sysctl.h> 48 #include <sys/sysent.h> 49 #include <sys/tslog.h> 50 #include <machine/bus.h> 51 #include <sys/rman.h> 52 #include <sys/signalvar.h> 53 #include <vm/uma.h> 54 55 #include <machine/cputypes.h> 56 #include <machine/frame.h> 57 #include <machine/intr_machdep.h> 58 #include <machine/md_var.h> 59 #include <machine/pcb.h> 60 #include <machine/psl.h> 61 #include <machine/resource.h> 62 #include <machine/specialreg.h> 63 #include <machine/segments.h> 64 #include <machine/ucontext.h> 65 #include <x86/ifunc.h> 66 67 /* 68 * Floating point support. 69 */ 70 71 #define fldcw(cw) __asm __volatile("fldcw %0" : : "m" (cw)) 72 #define fnclex() __asm __volatile("fnclex") 73 #define fninit() __asm __volatile("fninit") 74 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 75 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=am" (*(addr))) 76 #define fxrstor(addr) __asm __volatile("fxrstor %0" : : "m" (*(addr))) 77 #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 78 #define ldmxcsr(csr) __asm __volatile("ldmxcsr %0" : : "m" (csr)) 79 #define stmxcsr(addr) __asm __volatile("stmxcsr %0" : "=m" (*(addr))) 80 81 static __inline void 82 xrstor32(char *addr, uint64_t mask) 83 { 84 uint32_t low, hi; 85 86 low = mask; 87 hi = mask >> 32; 88 __asm __volatile("xrstor %0" : : "m" (*addr), "a" (low), "d" (hi)); 89 } 90 91 static __inline void 92 xrstor64(char *addr, uint64_t mask) 93 { 94 uint32_t low, hi; 95 96 low = mask; 97 hi = mask >> 32; 98 __asm __volatile("xrstor64 %0" : : "m" (*addr), "a" (low), "d" (hi)); 99 } 100 101 static __inline void 102 xsave32(char *addr, uint64_t mask) 103 { 104 uint32_t low, hi; 105 106 low = mask; 107 hi = mask >> 32; 108 __asm __volatile("xsave %0" : "=m" (*addr) : "a" (low), "d" (hi) : 109 "memory"); 110 } 111 112 static __inline void 113 xsave64(char *addr, uint64_t mask) 114 { 115 uint32_t low, hi; 116 117 low = mask; 118 hi = mask >> 32; 119 __asm __volatile("xsave64 %0" : "=m" (*addr) : "a" (low), "d" (hi) : 120 "memory"); 121 } 122 123 static __inline void 124 xsaveopt32(char *addr, uint64_t mask) 125 { 126 uint32_t low, hi; 127 128 low = mask; 129 hi = mask >> 32; 130 __asm __volatile("xsaveopt %0" : "=m" (*addr) : "a" (low), "d" (hi) : 131 "memory"); 132 } 133 134 static __inline void 135 xsaveopt64(char *addr, uint64_t mask) 136 { 137 uint32_t low, hi; 138 139 low = mask; 140 hi = mask >> 32; 141 __asm __volatile("xsaveopt64 %0" : "=m" (*addr) : "a" (low), "d" (hi) : 142 "memory"); 143 } 144 145 CTASSERT(sizeof(struct savefpu) == 512); 146 CTASSERT(sizeof(struct xstate_hdr) == 64); 147 CTASSERT(sizeof(struct savefpu_ymm) == 832); 148 149 /* 150 * This requirement is to make it easier for asm code to calculate 151 * offset of the fpu save area from the pcb address. FPU save area 152 * must be 64-byte aligned. 153 */ 154 CTASSERT(sizeof(struct pcb) % XSAVE_AREA_ALIGN == 0); 155 156 /* 157 * Ensure the copy of XCR0 saved in a core is contained in the padding 158 * area. 159 */ 160 CTASSERT(X86_XSTATE_XCR0_OFFSET >= offsetof(struct savefpu, sv_pad) && 161 X86_XSTATE_XCR0_OFFSET + sizeof(uint64_t) <= sizeof(struct savefpu)); 162 163 static void fpu_clean_state(void); 164 165 SYSCTL_INT(_hw, HW_FLOATINGPT, floatingpoint, CTLFLAG_RD, 166 SYSCTL_NULL_INT_PTR, 1, "Floating point instructions executed in hardware"); 167 168 int use_xsave; /* non-static for cpu_switch.S */ 169 uint64_t xsave_mask; /* the same */ 170 static uma_zone_t fpu_save_area_zone; 171 static struct savefpu *fpu_initialstate; 172 173 static struct xsave_area_elm_descr { 174 u_int offset; 175 u_int size; 176 } *xsave_area_desc; 177 178 static void 179 fpusave_xsaveopt64(void *addr) 180 { 181 xsaveopt64((char *)addr, xsave_mask); 182 } 183 184 static void 185 fpusave_xsaveopt3264(void *addr) 186 { 187 if (SV_CURPROC_FLAG(SV_ILP32)) 188 xsaveopt32((char *)addr, xsave_mask); 189 else 190 xsaveopt64((char *)addr, xsave_mask); 191 } 192 193 static void 194 fpusave_xsave64(void *addr) 195 { 196 xsave64((char *)addr, xsave_mask); 197 } 198 199 static void 200 fpusave_xsave3264(void *addr) 201 { 202 if (SV_CURPROC_FLAG(SV_ILP32)) 203 xsave32((char *)addr, xsave_mask); 204 else 205 xsave64((char *)addr, xsave_mask); 206 } 207 208 static void 209 fpurestore_xrstor64(void *addr) 210 { 211 xrstor64((char *)addr, xsave_mask); 212 } 213 214 static void 215 fpurestore_xrstor3264(void *addr) 216 { 217 if (SV_CURPROC_FLAG(SV_ILP32)) 218 xrstor32((char *)addr, xsave_mask); 219 else 220 xrstor64((char *)addr, xsave_mask); 221 } 222 223 static void 224 fpusave_fxsave(void *addr) 225 { 226 227 fxsave((char *)addr); 228 } 229 230 static void 231 fpurestore_fxrstor(void *addr) 232 { 233 234 fxrstor((char *)addr); 235 } 236 237 DEFINE_IFUNC(, void, fpusave, (void *)) 238 { 239 if (!use_xsave) 240 return (fpusave_fxsave); 241 if ((cpu_stdext_feature & CPUID_EXTSTATE_XSAVEOPT) != 0) { 242 return ((cpu_stdext_feature & CPUID_STDEXT_NFPUSG) != 0 ? 243 fpusave_xsaveopt64 : fpusave_xsaveopt3264); 244 } 245 return ((cpu_stdext_feature & CPUID_STDEXT_NFPUSG) != 0 ? 246 fpusave_xsave64 : fpusave_xsave3264); 247 } 248 249 DEFINE_IFUNC(, void, fpurestore, (void *)) 250 { 251 if (!use_xsave) 252 return (fpurestore_fxrstor); 253 return ((cpu_stdext_feature & CPUID_STDEXT_NFPUSG) != 0 ? 254 fpurestore_xrstor64 : fpurestore_xrstor3264); 255 } 256 257 void 258 fpususpend(void *addr) 259 { 260 u_long cr0; 261 262 cr0 = rcr0(); 263 fpu_enable(); 264 fpusave(addr); 265 load_cr0(cr0); 266 } 267 268 void 269 fpuresume(void *addr) 270 { 271 u_long cr0; 272 273 cr0 = rcr0(); 274 fpu_enable(); 275 fninit(); 276 if (use_xsave) 277 load_xcr(XCR0, xsave_mask); 278 fpurestore(addr); 279 load_cr0(cr0); 280 } 281 282 /* 283 * Enable XSAVE if supported and allowed by user. 284 * Calculate the xsave_mask. 285 */ 286 static void 287 fpuinit_bsp1(void) 288 { 289 u_int cp[4]; 290 uint64_t xsave_mask_user; 291 bool old_wp; 292 293 if (!use_xsave) 294 return; 295 cpuid_count(0xd, 0x0, cp); 296 xsave_mask = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE; 297 if ((cp[0] & xsave_mask) != xsave_mask) 298 panic("CPU0 does not support X87 or SSE: %x", cp[0]); 299 xsave_mask = ((uint64_t)cp[3] << 32) | cp[0]; 300 xsave_mask_user = xsave_mask; 301 TUNABLE_ULONG_FETCH("hw.xsave_mask", &xsave_mask_user); 302 xsave_mask_user |= XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE; 303 xsave_mask &= xsave_mask_user; 304 if ((xsave_mask & XFEATURE_AVX512) != XFEATURE_AVX512) 305 xsave_mask &= ~XFEATURE_AVX512; 306 if ((xsave_mask & XFEATURE_MPX) != XFEATURE_MPX) 307 xsave_mask &= ~XFEATURE_MPX; 308 309 cpuid_count(0xd, 0x1, cp); 310 if ((cp[0] & CPUID_EXTSTATE_XSAVEOPT) != 0) { 311 /* 312 * Patch the XSAVE instruction in the cpu_switch code 313 * to XSAVEOPT. We assume that XSAVE encoding used 314 * REX byte, and set the bit 4 of the r/m byte. 315 * 316 * It seems that some BIOSes give control to the OS 317 * with CR0.WP already set, making the kernel text 318 * read-only before cpu_startup(). 319 */ 320 old_wp = disable_wp(); 321 ctx_switch_xsave32[3] |= 0x10; 322 ctx_switch_xsave[3] |= 0x10; 323 restore_wp(old_wp); 324 } 325 } 326 327 /* 328 * Calculate the fpu save area size. 329 */ 330 static void 331 fpuinit_bsp2(void) 332 { 333 u_int cp[4]; 334 335 if (use_xsave) { 336 cpuid_count(0xd, 0x0, cp); 337 cpu_max_ext_state_size = cp[1]; 338 339 /* 340 * Reload the cpu_feature2, since we enabled OSXSAVE. 341 */ 342 do_cpuid(1, cp); 343 cpu_feature2 = cp[2]; 344 } else 345 cpu_max_ext_state_size = sizeof(struct savefpu); 346 } 347 348 /* 349 * Initialize the floating point unit. 350 */ 351 void 352 fpuinit(void) 353 { 354 register_t saveintr; 355 uint64_t cr4; 356 u_int mxcsr; 357 u_short control; 358 359 TSENTER(); 360 if (IS_BSP()) 361 fpuinit_bsp1(); 362 363 if (use_xsave) { 364 cr4 = rcr4(); 365 366 /* 367 * Revert enablement of PKRU if user disabled its 368 * saving on context switches by clearing the bit in 369 * the xsave mask. Also redundantly clear the bit in 370 * cpu_stdext_feature2 to prevent pmap from ever 371 * trying to set the page table bits. 372 */ 373 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0 && 374 (xsave_mask & XFEATURE_ENABLED_PKRU) == 0) { 375 cr4 &= ~CR4_PKE; 376 cpu_stdext_feature2 &= ~CPUID_STDEXT2_PKU; 377 } 378 379 load_cr4(cr4 | CR4_XSAVE); 380 load_xcr(XCR0, xsave_mask); 381 } 382 383 /* 384 * XCR0 shall be set up before CPU can report the save area size. 385 */ 386 if (IS_BSP()) 387 fpuinit_bsp2(); 388 389 /* 390 * It is too early for critical_enter() to work on AP. 391 */ 392 saveintr = intr_disable(); 393 fpu_enable(); 394 fninit(); 395 control = __INITIAL_FPUCW__; 396 fldcw(control); 397 mxcsr = __INITIAL_MXCSR__; 398 ldmxcsr(mxcsr); 399 fpu_disable(); 400 intr_restore(saveintr); 401 TSEXIT(); 402 } 403 404 /* 405 * On the boot CPU we generate a clean state that is used to 406 * initialize the floating point unit when it is first used by a 407 * process. 408 */ 409 static void 410 fpuinitstate(void *arg __unused) 411 { 412 uint64_t *xstate_bv; 413 register_t saveintr; 414 int cp[4], i, max_ext_n; 415 416 /* Do potentially blocking operations before disabling interrupts. */ 417 fpu_save_area_zone = uma_zcreate("FPU_save_area", 418 cpu_max_ext_state_size, NULL, NULL, NULL, NULL, 419 XSAVE_AREA_ALIGN - 1, 0); 420 fpu_initialstate = uma_zalloc(fpu_save_area_zone, M_WAITOK | M_ZERO); 421 if (use_xsave) { 422 max_ext_n = flsl(xsave_mask); 423 xsave_area_desc = malloc(max_ext_n * sizeof(struct 424 xsave_area_elm_descr), M_DEVBUF, M_WAITOK | M_ZERO); 425 } 426 427 cpu_thread_alloc(&thread0); 428 429 saveintr = intr_disable(); 430 fpu_enable(); 431 432 fpusave_fxsave(fpu_initialstate); 433 if (fpu_initialstate->sv_env.en_mxcsr_mask) 434 cpu_mxcsr_mask = fpu_initialstate->sv_env.en_mxcsr_mask; 435 else 436 cpu_mxcsr_mask = 0xFFBF; 437 438 /* 439 * The fninit instruction does not modify XMM registers or x87 440 * registers (MM/ST). The fpusave call dumped the garbage 441 * contained in the registers after reset to the initial state 442 * saved. Clear XMM and x87 registers file image to make the 443 * startup program state and signal handler XMM/x87 register 444 * content predictable. 445 */ 446 bzero(fpu_initialstate->sv_fp, sizeof(fpu_initialstate->sv_fp)); 447 bzero(fpu_initialstate->sv_xmm, sizeof(fpu_initialstate->sv_xmm)); 448 449 /* 450 * Create a table describing the layout of the CPU Extended 451 * Save Area. See Intel SDM rev. 075 Vol. 1 13.4.1 "Legacy 452 * Region of an XSAVE Area" for the source of offsets/sizes. 453 */ 454 if (use_xsave) { 455 xstate_bv = (uint64_t *)((char *)(fpu_initialstate + 1) + 456 offsetof(struct xstate_hdr, xstate_bv)); 457 *xstate_bv = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE; 458 459 /* x87 state */ 460 xsave_area_desc[0].offset = 0; 461 xsave_area_desc[0].size = 160; 462 /* XMM */ 463 xsave_area_desc[1].offset = 160; 464 xsave_area_desc[1].size = 416 - 160; 465 466 for (i = 2; i < max_ext_n; i++) { 467 cpuid_count(0xd, i, cp); 468 xsave_area_desc[i].offset = cp[1]; 469 xsave_area_desc[i].size = cp[0]; 470 } 471 } 472 473 fpu_disable(); 474 intr_restore(saveintr); 475 } 476 /* EFIRT needs this to be initialized before we can enter our EFI environment */ 477 SYSINIT(fpuinitstate, SI_SUB_CPU, SI_ORDER_ANY, fpuinitstate, NULL); 478 479 /* 480 * Free coprocessor (if we have it). 481 */ 482 void 483 fpuexit(struct thread *td) 484 { 485 486 critical_enter(); 487 if (curthread == PCPU_GET(fpcurthread)) { 488 fpu_enable(); 489 fpusave(curpcb->pcb_save); 490 fpu_disable(); 491 PCPU_SET(fpcurthread, NULL); 492 } 493 critical_exit(); 494 } 495 496 int 497 fpuformat(void) 498 { 499 500 return (_MC_FPFMT_XMM); 501 } 502 503 /* 504 * The following mechanism is used to ensure that the FPE_... value 505 * that is passed as a trapcode to the signal handler of the user 506 * process does not have more than one bit set. 507 * 508 * Multiple bits may be set if the user process modifies the control 509 * word while a status word bit is already set. While this is a sign 510 * of bad coding, we have no choice than to narrow them down to one 511 * bit, since we must not send a trapcode that is not exactly one of 512 * the FPE_ macros. 513 * 514 * The mechanism has a static table with 127 entries. Each combination 515 * of the 7 FPU status word exception bits directly translates to a 516 * position in this table, where a single FPE_... value is stored. 517 * This FPE_... value stored there is considered the "most important" 518 * of the exception bits and will be sent as the signal code. The 519 * precedence of the bits is based upon Intel Document "Numerical 520 * Applications", Chapter "Special Computational Situations". 521 * 522 * The macro to choose one of these values does these steps: 1) Throw 523 * away status word bits that cannot be masked. 2) Throw away the bits 524 * currently masked in the control word, assuming the user isn't 525 * interested in them anymore. 3) Reinsert status word bit 7 (stack 526 * fault) if it is set, which cannot be masked but must be presered. 527 * 4) Use the remaining bits to point into the trapcode table. 528 * 529 * The 6 maskable bits in order of their preference, as stated in the 530 * above referenced Intel manual: 531 * 1 Invalid operation (FP_X_INV) 532 * 1a Stack underflow 533 * 1b Stack overflow 534 * 1c Operand of unsupported format 535 * 1d SNaN operand. 536 * 2 QNaN operand (not an exception, irrelavant here) 537 * 3 Any other invalid-operation not mentioned above or zero divide 538 * (FP_X_INV, FP_X_DZ) 539 * 4 Denormal operand (FP_X_DNML) 540 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 541 * 6 Inexact result (FP_X_IMP) 542 */ 543 static char fpetable[128] = { 544 0, 545 FPE_FLTINV, /* 1 - INV */ 546 FPE_FLTUND, /* 2 - DNML */ 547 FPE_FLTINV, /* 3 - INV | DNML */ 548 FPE_FLTDIV, /* 4 - DZ */ 549 FPE_FLTINV, /* 5 - INV | DZ */ 550 FPE_FLTDIV, /* 6 - DNML | DZ */ 551 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 552 FPE_FLTOVF, /* 8 - OFL */ 553 FPE_FLTINV, /* 9 - INV | OFL */ 554 FPE_FLTUND, /* A - DNML | OFL */ 555 FPE_FLTINV, /* B - INV | DNML | OFL */ 556 FPE_FLTDIV, /* C - DZ | OFL */ 557 FPE_FLTINV, /* D - INV | DZ | OFL */ 558 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 559 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 560 FPE_FLTUND, /* 10 - UFL */ 561 FPE_FLTINV, /* 11 - INV | UFL */ 562 FPE_FLTUND, /* 12 - DNML | UFL */ 563 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 564 FPE_FLTDIV, /* 14 - DZ | UFL */ 565 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 566 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 567 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 568 FPE_FLTOVF, /* 18 - OFL | UFL */ 569 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 570 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 571 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 572 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 573 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 574 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 575 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 576 FPE_FLTRES, /* 20 - IMP */ 577 FPE_FLTINV, /* 21 - INV | IMP */ 578 FPE_FLTUND, /* 22 - DNML | IMP */ 579 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 580 FPE_FLTDIV, /* 24 - DZ | IMP */ 581 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 582 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 583 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 584 FPE_FLTOVF, /* 28 - OFL | IMP */ 585 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 586 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 587 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 588 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 589 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 590 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 591 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 592 FPE_FLTUND, /* 30 - UFL | IMP */ 593 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 594 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 595 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 596 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 597 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 598 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 599 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 600 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 601 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 602 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 603 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 604 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 605 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 606 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 607 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 608 FPE_FLTSUB, /* 40 - STK */ 609 FPE_FLTSUB, /* 41 - INV | STK */ 610 FPE_FLTUND, /* 42 - DNML | STK */ 611 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 612 FPE_FLTDIV, /* 44 - DZ | STK */ 613 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 614 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 615 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 616 FPE_FLTOVF, /* 48 - OFL | STK */ 617 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 618 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 619 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 620 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 621 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 622 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 623 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 624 FPE_FLTUND, /* 50 - UFL | STK */ 625 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 626 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 627 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 628 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 629 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 630 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 631 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 632 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 633 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 634 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 635 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 636 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 637 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 638 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 639 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 640 FPE_FLTRES, /* 60 - IMP | STK */ 641 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 642 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 643 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 644 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 645 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 646 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 647 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 648 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 649 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 650 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 651 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 652 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 653 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 654 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 655 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 656 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 657 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 658 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 659 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 660 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 661 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 662 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 663 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 664 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 665 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 666 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 667 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 668 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 669 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 670 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 671 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 672 }; 673 674 /* 675 * Read the FP status and control words, then generate si_code value 676 * for SIGFPE. The error code chosen will be one of the 677 * FPE_... macros. It will be sent as the second argument to old 678 * BSD-style signal handlers and as "siginfo_t->si_code" (second 679 * argument) to SA_SIGINFO signal handlers. 680 * 681 * Some time ago, we cleared the x87 exceptions with FNCLEX there. 682 * Clearing exceptions was necessary mainly to avoid IRQ13 bugs. The 683 * usermode code which understands the FPU hardware enough to enable 684 * the exceptions, can also handle clearing the exception state in the 685 * handler. The only consequence of not clearing the exception is the 686 * rethrow of the SIGFPE on return from the signal handler and 687 * reexecution of the corresponding instruction. 688 * 689 * For XMM traps, the exceptions were never cleared. 690 */ 691 int 692 fputrap_x87(void) 693 { 694 struct savefpu *pcb_save; 695 u_short control, status; 696 697 critical_enter(); 698 699 /* 700 * Interrupt handling (for another interrupt) may have pushed the 701 * state to memory. Fetch the relevant parts of the state from 702 * wherever they are. 703 */ 704 if (PCPU_GET(fpcurthread) != curthread) { 705 pcb_save = curpcb->pcb_save; 706 control = pcb_save->sv_env.en_cw; 707 status = pcb_save->sv_env.en_sw; 708 } else { 709 fnstcw(&control); 710 fnstsw(&status); 711 } 712 713 critical_exit(); 714 return (fpetable[status & ((~control & 0x3f) | 0x40)]); 715 } 716 717 int 718 fputrap_sse(void) 719 { 720 u_int mxcsr; 721 722 critical_enter(); 723 if (PCPU_GET(fpcurthread) != curthread) 724 mxcsr = curpcb->pcb_save->sv_env.en_mxcsr; 725 else 726 stmxcsr(&mxcsr); 727 critical_exit(); 728 return (fpetable[(mxcsr & (~mxcsr >> 7)) & 0x3f]); 729 } 730 731 static void 732 restore_fpu_curthread(struct thread *td) 733 { 734 struct pcb *pcb; 735 736 /* 737 * Record new context early in case frstor causes a trap. 738 */ 739 PCPU_SET(fpcurthread, td); 740 741 fpu_enable(); 742 fpu_clean_state(); 743 pcb = td->td_pcb; 744 745 if ((pcb->pcb_flags & PCB_FPUINITDONE) == 0) { 746 /* 747 * This is the first time this thread has used the FPU or 748 * the PCB doesn't contain a clean FPU state. Explicitly 749 * load an initial state. 750 * 751 * We prefer to restore the state from the actual save 752 * area in PCB instead of directly loading from 753 * fpu_initialstate, to ignite the XSAVEOPT 754 * tracking engine. 755 */ 756 bcopy(fpu_initialstate, pcb->pcb_save, 757 cpu_max_ext_state_size); 758 fpurestore(pcb->pcb_save); 759 if (pcb->pcb_initial_fpucw != __INITIAL_FPUCW__) 760 fldcw(pcb->pcb_initial_fpucw); 761 if (PCB_USER_FPU(pcb)) 762 set_pcb_flags(pcb, PCB_FPUINITDONE | 763 PCB_USERFPUINITDONE); 764 else 765 set_pcb_flags(pcb, PCB_FPUINITDONE); 766 } else 767 fpurestore(pcb->pcb_save); 768 } 769 770 /* 771 * Device Not Available (DNA, #NM) exception handler. 772 * 773 * It would be better to switch FP context here (if curthread != 774 * fpcurthread) and not necessarily for every context switch, but it 775 * is too hard to access foreign pcb's. 776 */ 777 void 778 fpudna(void) 779 { 780 struct thread *td; 781 782 td = curthread; 783 /* 784 * This handler is entered with interrupts enabled, so context 785 * switches may occur before critical_enter() is executed. If 786 * a context switch occurs, then when we regain control, our 787 * state will have been completely restored. The CPU may 788 * change underneath us, but the only part of our context that 789 * lives in the CPU is CR0.TS and that will be "restored" by 790 * setting it on the new CPU. 791 */ 792 critical_enter(); 793 794 KASSERT((curpcb->pcb_flags & PCB_FPUNOSAVE) == 0, 795 ("fpudna while in fpu_kern_enter(FPU_KERN_NOCTX)")); 796 if (__predict_false(PCPU_GET(fpcurthread) == td)) { 797 /* 798 * Some virtual machines seems to set %cr0.TS at 799 * arbitrary moments. Silently clear the TS bit 800 * regardless of the eager/lazy FPU context switch 801 * mode. 802 */ 803 fpu_enable(); 804 } else { 805 if (__predict_false(PCPU_GET(fpcurthread) != NULL)) { 806 panic( 807 "fpudna: fpcurthread = %p (%d), curthread = %p (%d)\n", 808 PCPU_GET(fpcurthread), 809 PCPU_GET(fpcurthread)->td_tid, td, td->td_tid); 810 } 811 restore_fpu_curthread(td); 812 } 813 critical_exit(); 814 } 815 816 void fpu_activate_sw(struct thread *td); /* Called from the context switch */ 817 void 818 fpu_activate_sw(struct thread *td) 819 { 820 821 if ((td->td_pflags & TDP_KTHREAD) != 0 || !PCB_USER_FPU(td->td_pcb)) { 822 PCPU_SET(fpcurthread, NULL); 823 fpu_disable(); 824 } else if (PCPU_GET(fpcurthread) != td) { 825 restore_fpu_curthread(td); 826 } 827 } 828 829 void 830 fpudrop(void) 831 { 832 struct thread *td; 833 834 td = PCPU_GET(fpcurthread); 835 KASSERT(td == curthread, ("fpudrop: fpcurthread != curthread")); 836 CRITICAL_ASSERT(td); 837 PCPU_SET(fpcurthread, NULL); 838 clear_pcb_flags(td->td_pcb, PCB_FPUINITDONE); 839 fpu_disable(); 840 } 841 842 /* 843 * Get the user state of the FPU into pcb->pcb_user_save without 844 * dropping ownership (if possible). It returns the FPU ownership 845 * status. 846 */ 847 int 848 fpugetregs(struct thread *td) 849 { 850 struct pcb *pcb; 851 uint64_t *xstate_bv, bit; 852 char *sa; 853 int max_ext_n, i, owned; 854 855 pcb = td->td_pcb; 856 critical_enter(); 857 if ((pcb->pcb_flags & PCB_USERFPUINITDONE) == 0) { 858 bcopy(fpu_initialstate, get_pcb_user_save_pcb(pcb), 859 cpu_max_ext_state_size); 860 get_pcb_user_save_pcb(pcb)->sv_env.en_cw = 861 pcb->pcb_initial_fpucw; 862 fpuuserinited(td); 863 critical_exit(); 864 return (_MC_FPOWNED_PCB); 865 } 866 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) { 867 fpusave(get_pcb_user_save_pcb(pcb)); 868 owned = _MC_FPOWNED_FPU; 869 } else { 870 owned = _MC_FPOWNED_PCB; 871 } 872 if (use_xsave) { 873 /* 874 * Handle partially saved state. 875 */ 876 sa = (char *)get_pcb_user_save_pcb(pcb); 877 xstate_bv = (uint64_t *)(sa + sizeof(struct savefpu) + 878 offsetof(struct xstate_hdr, xstate_bv)); 879 max_ext_n = flsl(xsave_mask); 880 for (i = 0; i < max_ext_n; i++) { 881 bit = 1ULL << i; 882 if ((xsave_mask & bit) == 0 || (*xstate_bv & bit) != 0) 883 continue; 884 bcopy((char *)fpu_initialstate + 885 xsave_area_desc[i].offset, 886 sa + xsave_area_desc[i].offset, 887 xsave_area_desc[i].size); 888 *xstate_bv |= bit; 889 } 890 } 891 critical_exit(); 892 return (owned); 893 } 894 895 void 896 fpuuserinited(struct thread *td) 897 { 898 struct pcb *pcb; 899 900 CRITICAL_ASSERT(td); 901 pcb = td->td_pcb; 902 if (PCB_USER_FPU(pcb)) 903 set_pcb_flags(pcb, 904 PCB_FPUINITDONE | PCB_USERFPUINITDONE); 905 else 906 set_pcb_flags(pcb, PCB_FPUINITDONE); 907 } 908 909 int 910 fpusetxstate(struct thread *td, char *xfpustate, size_t xfpustate_size) 911 { 912 struct xstate_hdr *hdr, *ehdr; 913 size_t len, max_len; 914 uint64_t bv; 915 916 /* XXXKIB should we clear all extended state in xstate_bv instead ? */ 917 if (xfpustate == NULL) 918 return (0); 919 if (!use_xsave) 920 return (EOPNOTSUPP); 921 922 len = xfpustate_size; 923 if (len < sizeof(struct xstate_hdr)) 924 return (EINVAL); 925 max_len = cpu_max_ext_state_size - sizeof(struct savefpu); 926 if (len > max_len) 927 return (EINVAL); 928 929 ehdr = (struct xstate_hdr *)xfpustate; 930 bv = ehdr->xstate_bv; 931 932 /* 933 * Avoid #gp. 934 */ 935 if (bv & ~xsave_mask) 936 return (EINVAL); 937 938 hdr = (struct xstate_hdr *)(get_pcb_user_save_td(td) + 1); 939 940 hdr->xstate_bv = bv; 941 bcopy(xfpustate + sizeof(struct xstate_hdr), 942 (char *)(hdr + 1), len - sizeof(struct xstate_hdr)); 943 944 return (0); 945 } 946 947 /* 948 * Set the state of the FPU. 949 */ 950 int 951 fpusetregs(struct thread *td, struct savefpu *addr, char *xfpustate, 952 size_t xfpustate_size) 953 { 954 struct pcb *pcb; 955 int error; 956 957 addr->sv_env.en_mxcsr &= cpu_mxcsr_mask; 958 pcb = td->td_pcb; 959 error = 0; 960 critical_enter(); 961 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) { 962 error = fpusetxstate(td, xfpustate, xfpustate_size); 963 if (error == 0) { 964 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr)); 965 fpurestore(get_pcb_user_save_td(td)); 966 set_pcb_flags(pcb, PCB_FPUINITDONE | 967 PCB_USERFPUINITDONE); 968 } 969 } else { 970 error = fpusetxstate(td, xfpustate, xfpustate_size); 971 if (error == 0) { 972 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr)); 973 fpuuserinited(td); 974 } 975 } 976 critical_exit(); 977 return (error); 978 } 979 980 /* 981 * On AuthenticAMD processors, the fxrstor instruction does not restore 982 * the x87's stored last instruction pointer, last data pointer, and last 983 * opcode values, except in the rare case in which the exception summary 984 * (ES) bit in the x87 status word is set to 1. 985 * 986 * In order to avoid leaking this information across processes, we clean 987 * these values by performing a dummy load before executing fxrstor(). 988 */ 989 static void 990 fpu_clean_state(void) 991 { 992 static float dummy_variable = 0.0; 993 u_short status; 994 995 /* 996 * Clear the ES bit in the x87 status word if it is currently 997 * set, in order to avoid causing a fault in the upcoming load. 998 */ 999 fnstsw(&status); 1000 if (status & 0x80) 1001 fnclex(); 1002 1003 /* 1004 * Load the dummy variable into the x87 stack. This mangles 1005 * the x87 stack, but we don't care since we're about to call 1006 * fxrstor() anyway. 1007 */ 1008 __asm __volatile("ffree %%st(7); flds %0" : : "m" (dummy_variable)); 1009 } 1010 1011 /* 1012 * This really sucks. We want the acpi version only, but it requires 1013 * the isa_if.h file in order to get the definitions. 1014 */ 1015 #include "opt_isa.h" 1016 #ifdef DEV_ISA 1017 #include <isa/isavar.h> 1018 /* 1019 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI. 1020 */ 1021 static struct isa_pnp_id fpupnp_ids[] = { 1022 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */ 1023 { 0 } 1024 }; 1025 1026 static int 1027 fpupnp_probe(device_t dev) 1028 { 1029 int result; 1030 1031 result = ISA_PNP_PROBE(device_get_parent(dev), dev, fpupnp_ids); 1032 if (result <= 0) 1033 device_quiet(dev); 1034 return (result); 1035 } 1036 1037 static int 1038 fpupnp_attach(device_t dev) 1039 { 1040 1041 return (0); 1042 } 1043 1044 static device_method_t fpupnp_methods[] = { 1045 /* Device interface */ 1046 DEVMETHOD(device_probe, fpupnp_probe), 1047 DEVMETHOD(device_attach, fpupnp_attach), 1048 DEVMETHOD(device_detach, bus_generic_detach), 1049 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1050 DEVMETHOD(device_suspend, bus_generic_suspend), 1051 DEVMETHOD(device_resume, bus_generic_resume), 1052 { 0, 0 } 1053 }; 1054 1055 static driver_t fpupnp_driver = { 1056 "fpupnp", 1057 fpupnp_methods, 1058 1, /* no softc */ 1059 }; 1060 1061 DRIVER_MODULE(fpupnp, acpi, fpupnp_driver, 0, 0); 1062 ISA_PNP_INFO(fpupnp_ids); 1063 #endif /* DEV_ISA */ 1064 1065 static MALLOC_DEFINE(M_FPUKERN_CTX, "fpukern_ctx", 1066 "Kernel contexts for FPU state"); 1067 1068 #define FPU_KERN_CTX_FPUINITDONE 0x01 1069 #define FPU_KERN_CTX_DUMMY 0x02 /* avoided save for the kern thread */ 1070 #define FPU_KERN_CTX_INUSE 0x04 1071 1072 struct fpu_kern_ctx { 1073 struct savefpu *prev; 1074 uint32_t flags; 1075 char hwstate1[]; 1076 }; 1077 1078 static inline size_t __pure2 1079 fpu_kern_alloc_sz(u_int max_est) 1080 { 1081 return (sizeof(struct fpu_kern_ctx) + XSAVE_AREA_ALIGN + max_est); 1082 } 1083 1084 static inline int __pure2 1085 fpu_kern_malloc_flags(u_int fpflags) 1086 { 1087 return (((fpflags & FPU_KERN_NOWAIT) ? M_NOWAIT : M_WAITOK) | M_ZERO); 1088 } 1089 1090 struct fpu_kern_ctx * 1091 fpu_kern_alloc_ctx_domain(int domain, u_int flags) 1092 { 1093 return (malloc_domainset(fpu_kern_alloc_sz(cpu_max_ext_state_size), 1094 M_FPUKERN_CTX, DOMAINSET_PREF(domain), 1095 fpu_kern_malloc_flags(flags))); 1096 } 1097 1098 struct fpu_kern_ctx * 1099 fpu_kern_alloc_ctx(u_int flags) 1100 { 1101 return (malloc(fpu_kern_alloc_sz(cpu_max_ext_state_size), 1102 M_FPUKERN_CTX, fpu_kern_malloc_flags(flags))); 1103 } 1104 1105 void 1106 fpu_kern_free_ctx(struct fpu_kern_ctx *ctx) 1107 { 1108 1109 KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) == 0, ("free'ing inuse ctx")); 1110 /* XXXKIB clear the memory ? */ 1111 free(ctx, M_FPUKERN_CTX); 1112 } 1113 1114 static struct savefpu * 1115 fpu_kern_ctx_savefpu(struct fpu_kern_ctx *ctx) 1116 { 1117 vm_offset_t p; 1118 1119 p = (vm_offset_t)&ctx->hwstate1; 1120 p = roundup2(p, XSAVE_AREA_ALIGN); 1121 return ((struct savefpu *)p); 1122 } 1123 1124 void 1125 fpu_kern_enter(struct thread *td, struct fpu_kern_ctx *ctx, u_int flags) 1126 { 1127 struct pcb *pcb; 1128 1129 pcb = td->td_pcb; 1130 KASSERT((flags & FPU_KERN_NOCTX) != 0 || ctx != NULL, 1131 ("ctx is required when !FPU_KERN_NOCTX")); 1132 KASSERT(ctx == NULL || (ctx->flags & FPU_KERN_CTX_INUSE) == 0, 1133 ("using inuse ctx")); 1134 KASSERT((pcb->pcb_flags & PCB_FPUNOSAVE) == 0, 1135 ("recursive fpu_kern_enter while in PCB_FPUNOSAVE state")); 1136 1137 if ((flags & FPU_KERN_NOCTX) != 0) { 1138 critical_enter(); 1139 fpu_enable(); 1140 if (curthread == PCPU_GET(fpcurthread)) { 1141 fpusave(curpcb->pcb_save); 1142 PCPU_SET(fpcurthread, NULL); 1143 } else { 1144 KASSERT(PCPU_GET(fpcurthread) == NULL, 1145 ("invalid fpcurthread")); 1146 } 1147 1148 /* 1149 * This breaks XSAVEOPT tracker, but 1150 * PCB_FPUNOSAVE state is supposed to never need to 1151 * save FPU context at all. 1152 */ 1153 fpurestore(fpu_initialstate); 1154 set_pcb_flags(pcb, PCB_KERNFPU | PCB_FPUNOSAVE | 1155 PCB_FPUINITDONE); 1156 return; 1157 } 1158 if ((flags & FPU_KERN_KTHR) != 0 && is_fpu_kern_thread(0)) { 1159 ctx->flags = FPU_KERN_CTX_DUMMY | FPU_KERN_CTX_INUSE; 1160 return; 1161 } 1162 critical_enter(); 1163 KASSERT(!PCB_USER_FPU(pcb) || pcb->pcb_save == 1164 get_pcb_user_save_pcb(pcb), ("mangled pcb_save")); 1165 ctx->flags = FPU_KERN_CTX_INUSE; 1166 if ((pcb->pcb_flags & PCB_FPUINITDONE) != 0) 1167 ctx->flags |= FPU_KERN_CTX_FPUINITDONE; 1168 fpuexit(td); 1169 ctx->prev = pcb->pcb_save; 1170 pcb->pcb_save = fpu_kern_ctx_savefpu(ctx); 1171 set_pcb_flags(pcb, PCB_KERNFPU); 1172 clear_pcb_flags(pcb, PCB_FPUINITDONE); 1173 critical_exit(); 1174 } 1175 1176 int 1177 fpu_kern_leave(struct thread *td, struct fpu_kern_ctx *ctx) 1178 { 1179 struct pcb *pcb; 1180 1181 pcb = td->td_pcb; 1182 1183 if ((pcb->pcb_flags & PCB_FPUNOSAVE) != 0) { 1184 KASSERT(ctx == NULL, ("non-null ctx after FPU_KERN_NOCTX")); 1185 KASSERT(PCPU_GET(fpcurthread) == NULL, 1186 ("non-NULL fpcurthread for PCB_FPUNOSAVE")); 1187 CRITICAL_ASSERT(td); 1188 1189 clear_pcb_flags(pcb, PCB_FPUNOSAVE | PCB_FPUINITDONE); 1190 fpu_disable(); 1191 } else { 1192 KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) != 0, 1193 ("leaving not inuse ctx")); 1194 ctx->flags &= ~FPU_KERN_CTX_INUSE; 1195 1196 if (is_fpu_kern_thread(0) && 1197 (ctx->flags & FPU_KERN_CTX_DUMMY) != 0) 1198 return (0); 1199 KASSERT((ctx->flags & FPU_KERN_CTX_DUMMY) == 0, 1200 ("dummy ctx")); 1201 critical_enter(); 1202 if (curthread == PCPU_GET(fpcurthread)) 1203 fpudrop(); 1204 pcb->pcb_save = ctx->prev; 1205 } 1206 1207 if (pcb->pcb_save == get_pcb_user_save_pcb(pcb)) { 1208 if ((pcb->pcb_flags & PCB_USERFPUINITDONE) != 0) { 1209 set_pcb_flags(pcb, PCB_FPUINITDONE); 1210 if ((pcb->pcb_flags & PCB_KERNFPU_THR) == 0) 1211 clear_pcb_flags(pcb, PCB_KERNFPU); 1212 } else if ((pcb->pcb_flags & PCB_KERNFPU_THR) == 0) 1213 clear_pcb_flags(pcb, PCB_FPUINITDONE | PCB_KERNFPU); 1214 } else { 1215 if ((ctx->flags & FPU_KERN_CTX_FPUINITDONE) != 0) 1216 set_pcb_flags(pcb, PCB_FPUINITDONE); 1217 else 1218 clear_pcb_flags(pcb, PCB_FPUINITDONE); 1219 KASSERT(!PCB_USER_FPU(pcb), ("unpaired fpu_kern_leave")); 1220 } 1221 critical_exit(); 1222 return (0); 1223 } 1224 1225 int 1226 fpu_kern_thread(u_int flags) 1227 { 1228 1229 KASSERT((curthread->td_pflags & TDP_KTHREAD) != 0, 1230 ("Only kthread may use fpu_kern_thread")); 1231 KASSERT(curpcb->pcb_save == get_pcb_user_save_pcb(curpcb), 1232 ("mangled pcb_save")); 1233 KASSERT(PCB_USER_FPU(curpcb), ("recursive call")); 1234 1235 set_pcb_flags(curpcb, PCB_KERNFPU | PCB_KERNFPU_THR); 1236 return (0); 1237 } 1238 1239 int 1240 is_fpu_kern_thread(u_int flags) 1241 { 1242 1243 if ((curthread->td_pflags & TDP_KTHREAD) == 0) 1244 return (0); 1245 return ((curpcb->pcb_flags & PCB_KERNFPU_THR) != 0); 1246 } 1247 1248 /* 1249 * FPU save area alloc/free/init utility routines 1250 */ 1251 struct savefpu * 1252 fpu_save_area_alloc(void) 1253 { 1254 1255 return (uma_zalloc(fpu_save_area_zone, M_WAITOK)); 1256 } 1257 1258 void 1259 fpu_save_area_free(struct savefpu *fsa) 1260 { 1261 1262 uma_zfree(fpu_save_area_zone, fsa); 1263 } 1264 1265 void 1266 fpu_save_area_reset(struct savefpu *fsa) 1267 { 1268 1269 bcopy(fpu_initialstate, fsa, cpu_max_ext_state_size); 1270 } 1271