1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 1990 William Jolitz. 5 * Copyright (c) 1991 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of the University nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 33 */ 34 35 #include <sys/cdefs.h> 36 __FBSDID("$FreeBSD$"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/bus.h> 41 #include <sys/kernel.h> 42 #include <sys/lock.h> 43 #include <sys/malloc.h> 44 #include <sys/module.h> 45 #include <sys/mutex.h> 46 #include <sys/mutex.h> 47 #include <sys/proc.h> 48 #include <sys/sysctl.h> 49 #include <machine/bus.h> 50 #include <sys/rman.h> 51 #include <sys/signalvar.h> 52 #include <vm/uma.h> 53 54 #include <machine/cputypes.h> 55 #include <machine/frame.h> 56 #include <machine/intr_machdep.h> 57 #include <machine/md_var.h> 58 #include <machine/pcb.h> 59 #include <machine/psl.h> 60 #include <machine/resource.h> 61 #include <machine/specialreg.h> 62 #include <machine/segments.h> 63 #include <machine/ucontext.h> 64 #include <x86/ifunc.h> 65 66 /* 67 * Floating point support. 68 */ 69 70 #if defined(__GNUCLIKE_ASM) && !defined(lint) 71 72 #define fldcw(cw) __asm __volatile("fldcw %0" : : "m" (cw)) 73 #define fnclex() __asm __volatile("fnclex") 74 #define fninit() __asm __volatile("fninit") 75 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 76 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=am" (*(addr))) 77 #define fxrstor(addr) __asm __volatile("fxrstor %0" : : "m" (*(addr))) 78 #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 79 #define ldmxcsr(csr) __asm __volatile("ldmxcsr %0" : : "m" (csr)) 80 #define stmxcsr(addr) __asm __volatile("stmxcsr %0" : : "m" (*(addr))) 81 82 static __inline void 83 xrstor(char *addr, uint64_t mask) 84 { 85 uint32_t low, hi; 86 87 low = mask; 88 hi = mask >> 32; 89 __asm __volatile("xrstor %0" : : "m" (*addr), "a" (low), "d" (hi)); 90 } 91 92 static __inline void 93 xsave(char *addr, uint64_t mask) 94 { 95 uint32_t low, hi; 96 97 low = mask; 98 hi = mask >> 32; 99 __asm __volatile("xsave %0" : "=m" (*addr) : "a" (low), "d" (hi) : 100 "memory"); 101 } 102 103 #else /* !(__GNUCLIKE_ASM && !lint) */ 104 105 void fldcw(u_short cw); 106 void fnclex(void); 107 void fninit(void); 108 void fnstcw(caddr_t addr); 109 void fnstsw(caddr_t addr); 110 void fxsave(caddr_t addr); 111 void fxrstor(caddr_t addr); 112 void ldmxcsr(u_int csr); 113 void stmxcsr(u_int *csr); 114 void xrstor(char *addr, uint64_t mask); 115 void xsave(char *addr, uint64_t mask); 116 117 #endif /* __GNUCLIKE_ASM && !lint */ 118 119 #define start_emulating() load_cr0(rcr0() | CR0_TS) 120 #define stop_emulating() clts() 121 122 CTASSERT(sizeof(struct savefpu) == 512); 123 CTASSERT(sizeof(struct xstate_hdr) == 64); 124 CTASSERT(sizeof(struct savefpu_ymm) == 832); 125 126 /* 127 * This requirement is to make it easier for asm code to calculate 128 * offset of the fpu save area from the pcb address. FPU save area 129 * must be 64-byte aligned. 130 */ 131 CTASSERT(sizeof(struct pcb) % XSAVE_AREA_ALIGN == 0); 132 133 /* 134 * Ensure the copy of XCR0 saved in a core is contained in the padding 135 * area. 136 */ 137 CTASSERT(X86_XSTATE_XCR0_OFFSET >= offsetof(struct savefpu, sv_pad) && 138 X86_XSTATE_XCR0_OFFSET + sizeof(uint64_t) <= sizeof(struct savefpu)); 139 140 static void fpu_clean_state(void); 141 142 SYSCTL_INT(_hw, HW_FLOATINGPT, floatingpoint, CTLFLAG_RD, 143 SYSCTL_NULL_INT_PTR, 1, "Floating point instructions executed in hardware"); 144 145 int use_xsave; /* non-static for cpu_switch.S */ 146 uint64_t xsave_mask; /* the same */ 147 static uma_zone_t fpu_save_area_zone; 148 static struct savefpu *fpu_initialstate; 149 150 struct xsave_area_elm_descr { 151 u_int offset; 152 u_int size; 153 } *xsave_area_desc; 154 155 static void 156 fpusave_xsave(void *addr) 157 { 158 159 xsave((char *)addr, xsave_mask); 160 } 161 162 static void 163 fpurestore_xrstor(void *addr) 164 { 165 166 xrstor((char *)addr, xsave_mask); 167 } 168 169 static void 170 fpusave_fxsave(void *addr) 171 { 172 173 fxsave((char *)addr); 174 } 175 176 static void 177 fpurestore_fxrstor(void *addr) 178 { 179 180 fxrstor((char *)addr); 181 } 182 183 static void 184 init_xsave(void) 185 { 186 187 if (use_xsave) 188 return; 189 if ((cpu_feature2 & CPUID2_XSAVE) == 0) 190 return; 191 use_xsave = 1; 192 TUNABLE_INT_FETCH("hw.use_xsave", &use_xsave); 193 } 194 195 DEFINE_IFUNC(, void, fpusave, (void *), static) 196 { 197 198 init_xsave(); 199 return (use_xsave ? fpusave_xsave : fpusave_fxsave); 200 } 201 202 DEFINE_IFUNC(, void, fpurestore, (void *), static) 203 { 204 205 init_xsave(); 206 return (use_xsave ? fpurestore_xrstor : fpurestore_fxrstor); 207 } 208 209 void 210 fpususpend(void *addr) 211 { 212 u_long cr0; 213 214 cr0 = rcr0(); 215 stop_emulating(); 216 fpusave(addr); 217 load_cr0(cr0); 218 } 219 220 void 221 fpuresume(void *addr) 222 { 223 u_long cr0; 224 225 cr0 = rcr0(); 226 stop_emulating(); 227 fninit(); 228 if (use_xsave) 229 load_xcr(XCR0, xsave_mask); 230 fpurestore(addr); 231 load_cr0(cr0); 232 } 233 234 /* 235 * Enable XSAVE if supported and allowed by user. 236 * Calculate the xsave_mask. 237 */ 238 static void 239 fpuinit_bsp1(void) 240 { 241 u_int cp[4]; 242 uint64_t xsave_mask_user; 243 bool old_wp; 244 245 if (!use_xsave) 246 return; 247 cpuid_count(0xd, 0x0, cp); 248 xsave_mask = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE; 249 if ((cp[0] & xsave_mask) != xsave_mask) 250 panic("CPU0 does not support X87 or SSE: %x", cp[0]); 251 xsave_mask = ((uint64_t)cp[3] << 32) | cp[0]; 252 xsave_mask_user = xsave_mask; 253 TUNABLE_ULONG_FETCH("hw.xsave_mask", &xsave_mask_user); 254 xsave_mask_user |= XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE; 255 xsave_mask &= xsave_mask_user; 256 if ((xsave_mask & XFEATURE_AVX512) != XFEATURE_AVX512) 257 xsave_mask &= ~XFEATURE_AVX512; 258 if ((xsave_mask & XFEATURE_MPX) != XFEATURE_MPX) 259 xsave_mask &= ~XFEATURE_MPX; 260 261 cpuid_count(0xd, 0x1, cp); 262 if ((cp[0] & CPUID_EXTSTATE_XSAVEOPT) != 0) { 263 /* 264 * Patch the XSAVE instruction in the cpu_switch code 265 * to XSAVEOPT. We assume that XSAVE encoding used 266 * REX byte, and set the bit 4 of the r/m byte. 267 * 268 * It seems that some BIOSes give control to the OS 269 * with CR0.WP already set, making the kernel text 270 * read-only before cpu_startup(). 271 */ 272 old_wp = disable_wp(); 273 ctx_switch_xsave[3] |= 0x10; 274 restore_wp(old_wp); 275 } 276 } 277 278 /* 279 * Calculate the fpu save area size. 280 */ 281 static void 282 fpuinit_bsp2(void) 283 { 284 u_int cp[4]; 285 286 if (use_xsave) { 287 cpuid_count(0xd, 0x0, cp); 288 cpu_max_ext_state_size = cp[1]; 289 290 /* 291 * Reload the cpu_feature2, since we enabled OSXSAVE. 292 */ 293 do_cpuid(1, cp); 294 cpu_feature2 = cp[2]; 295 } else 296 cpu_max_ext_state_size = sizeof(struct savefpu); 297 } 298 299 /* 300 * Initialize the floating point unit. 301 */ 302 void 303 fpuinit(void) 304 { 305 register_t saveintr; 306 u_int mxcsr; 307 u_short control; 308 309 if (IS_BSP()) 310 fpuinit_bsp1(); 311 312 if (use_xsave) { 313 load_cr4(rcr4() | CR4_XSAVE); 314 load_xcr(XCR0, xsave_mask); 315 } 316 317 /* 318 * XCR0 shall be set up before CPU can report the save area size. 319 */ 320 if (IS_BSP()) 321 fpuinit_bsp2(); 322 323 /* 324 * It is too early for critical_enter() to work on AP. 325 */ 326 saveintr = intr_disable(); 327 stop_emulating(); 328 fninit(); 329 control = __INITIAL_FPUCW__; 330 fldcw(control); 331 mxcsr = __INITIAL_MXCSR__; 332 ldmxcsr(mxcsr); 333 start_emulating(); 334 intr_restore(saveintr); 335 } 336 337 /* 338 * On the boot CPU we generate a clean state that is used to 339 * initialize the floating point unit when it is first used by a 340 * process. 341 */ 342 static void 343 fpuinitstate(void *arg __unused) 344 { 345 register_t saveintr; 346 int cp[4], i, max_ext_n; 347 348 fpu_initialstate = malloc(cpu_max_ext_state_size, M_DEVBUF, 349 M_WAITOK | M_ZERO); 350 saveintr = intr_disable(); 351 stop_emulating(); 352 353 fpusave(fpu_initialstate); 354 if (fpu_initialstate->sv_env.en_mxcsr_mask) 355 cpu_mxcsr_mask = fpu_initialstate->sv_env.en_mxcsr_mask; 356 else 357 cpu_mxcsr_mask = 0xFFBF; 358 359 /* 360 * The fninit instruction does not modify XMM registers or x87 361 * registers (MM/ST). The fpusave call dumped the garbage 362 * contained in the registers after reset to the initial state 363 * saved. Clear XMM and x87 registers file image to make the 364 * startup program state and signal handler XMM/x87 register 365 * content predictable. 366 */ 367 bzero(fpu_initialstate->sv_fp, sizeof(fpu_initialstate->sv_fp)); 368 bzero(fpu_initialstate->sv_xmm, sizeof(fpu_initialstate->sv_xmm)); 369 370 /* 371 * Create a table describing the layout of the CPU Extended 372 * Save Area. 373 */ 374 if (use_xsave) { 375 max_ext_n = flsl(xsave_mask); 376 xsave_area_desc = malloc(max_ext_n * sizeof(struct 377 xsave_area_elm_descr), M_DEVBUF, M_WAITOK | M_ZERO); 378 /* x87 state */ 379 xsave_area_desc[0].offset = 0; 380 xsave_area_desc[0].size = 160; 381 /* XMM */ 382 xsave_area_desc[1].offset = 160; 383 xsave_area_desc[1].size = 288 - 160; 384 385 for (i = 2; i < max_ext_n; i++) { 386 cpuid_count(0xd, i, cp); 387 xsave_area_desc[i].offset = cp[1]; 388 xsave_area_desc[i].size = cp[0]; 389 } 390 } 391 392 fpu_save_area_zone = uma_zcreate("FPU_save_area", 393 cpu_max_ext_state_size, NULL, NULL, NULL, NULL, 394 XSAVE_AREA_ALIGN - 1, 0); 395 396 start_emulating(); 397 intr_restore(saveintr); 398 } 399 /* EFIRT needs this to be initialized before we can enter our EFI environment */ 400 SYSINIT(fpuinitstate, SI_SUB_DRIVERS, SI_ORDER_FIRST, fpuinitstate, NULL); 401 402 /* 403 * Free coprocessor (if we have it). 404 */ 405 void 406 fpuexit(struct thread *td) 407 { 408 409 critical_enter(); 410 if (curthread == PCPU_GET(fpcurthread)) { 411 stop_emulating(); 412 fpusave(curpcb->pcb_save); 413 start_emulating(); 414 PCPU_SET(fpcurthread, NULL); 415 } 416 critical_exit(); 417 } 418 419 int 420 fpuformat(void) 421 { 422 423 return (_MC_FPFMT_XMM); 424 } 425 426 /* 427 * The following mechanism is used to ensure that the FPE_... value 428 * that is passed as a trapcode to the signal handler of the user 429 * process does not have more than one bit set. 430 * 431 * Multiple bits may be set if the user process modifies the control 432 * word while a status word bit is already set. While this is a sign 433 * of bad coding, we have no choise than to narrow them down to one 434 * bit, since we must not send a trapcode that is not exactly one of 435 * the FPE_ macros. 436 * 437 * The mechanism has a static table with 127 entries. Each combination 438 * of the 7 FPU status word exception bits directly translates to a 439 * position in this table, where a single FPE_... value is stored. 440 * This FPE_... value stored there is considered the "most important" 441 * of the exception bits and will be sent as the signal code. The 442 * precedence of the bits is based upon Intel Document "Numerical 443 * Applications", Chapter "Special Computational Situations". 444 * 445 * The macro to choose one of these values does these steps: 1) Throw 446 * away status word bits that cannot be masked. 2) Throw away the bits 447 * currently masked in the control word, assuming the user isn't 448 * interested in them anymore. 3) Reinsert status word bit 7 (stack 449 * fault) if it is set, which cannot be masked but must be presered. 450 * 4) Use the remaining bits to point into the trapcode table. 451 * 452 * The 6 maskable bits in order of their preference, as stated in the 453 * above referenced Intel manual: 454 * 1 Invalid operation (FP_X_INV) 455 * 1a Stack underflow 456 * 1b Stack overflow 457 * 1c Operand of unsupported format 458 * 1d SNaN operand. 459 * 2 QNaN operand (not an exception, irrelavant here) 460 * 3 Any other invalid-operation not mentioned above or zero divide 461 * (FP_X_INV, FP_X_DZ) 462 * 4 Denormal operand (FP_X_DNML) 463 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 464 * 6 Inexact result (FP_X_IMP) 465 */ 466 static char fpetable[128] = { 467 0, 468 FPE_FLTINV, /* 1 - INV */ 469 FPE_FLTUND, /* 2 - DNML */ 470 FPE_FLTINV, /* 3 - INV | DNML */ 471 FPE_FLTDIV, /* 4 - DZ */ 472 FPE_FLTINV, /* 5 - INV | DZ */ 473 FPE_FLTDIV, /* 6 - DNML | DZ */ 474 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 475 FPE_FLTOVF, /* 8 - OFL */ 476 FPE_FLTINV, /* 9 - INV | OFL */ 477 FPE_FLTUND, /* A - DNML | OFL */ 478 FPE_FLTINV, /* B - INV | DNML | OFL */ 479 FPE_FLTDIV, /* C - DZ | OFL */ 480 FPE_FLTINV, /* D - INV | DZ | OFL */ 481 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 482 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 483 FPE_FLTUND, /* 10 - UFL */ 484 FPE_FLTINV, /* 11 - INV | UFL */ 485 FPE_FLTUND, /* 12 - DNML | UFL */ 486 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 487 FPE_FLTDIV, /* 14 - DZ | UFL */ 488 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 489 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 490 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 491 FPE_FLTOVF, /* 18 - OFL | UFL */ 492 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 493 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 494 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 495 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 496 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 497 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 498 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 499 FPE_FLTRES, /* 20 - IMP */ 500 FPE_FLTINV, /* 21 - INV | IMP */ 501 FPE_FLTUND, /* 22 - DNML | IMP */ 502 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 503 FPE_FLTDIV, /* 24 - DZ | IMP */ 504 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 505 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 506 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 507 FPE_FLTOVF, /* 28 - OFL | IMP */ 508 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 509 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 510 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 511 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 512 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 513 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 514 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 515 FPE_FLTUND, /* 30 - UFL | IMP */ 516 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 517 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 518 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 519 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 520 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 521 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 522 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 523 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 524 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 525 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 526 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 527 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 528 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 529 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 530 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 531 FPE_FLTSUB, /* 40 - STK */ 532 FPE_FLTSUB, /* 41 - INV | STK */ 533 FPE_FLTUND, /* 42 - DNML | STK */ 534 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 535 FPE_FLTDIV, /* 44 - DZ | STK */ 536 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 537 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 538 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 539 FPE_FLTOVF, /* 48 - OFL | STK */ 540 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 541 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 542 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 543 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 544 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 545 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 546 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 547 FPE_FLTUND, /* 50 - UFL | STK */ 548 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 549 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 550 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 551 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 552 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 553 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 554 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 555 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 556 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 557 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 558 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 559 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 560 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 561 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 562 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 563 FPE_FLTRES, /* 60 - IMP | STK */ 564 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 565 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 566 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 567 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 568 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 569 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 570 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 571 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 572 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 573 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 574 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 575 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 576 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 577 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 578 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 579 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 580 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 581 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 582 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 583 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 584 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 585 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 586 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 587 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 588 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 589 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 590 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 591 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 592 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 593 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 594 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 595 }; 596 597 /* 598 * Read the FP status and control words, then generate si_code value 599 * for SIGFPE. The error code chosen will be one of the 600 * FPE_... macros. It will be sent as the second argument to old 601 * BSD-style signal handlers and as "siginfo_t->si_code" (second 602 * argument) to SA_SIGINFO signal handlers. 603 * 604 * Some time ago, we cleared the x87 exceptions with FNCLEX there. 605 * Clearing exceptions was necessary mainly to avoid IRQ13 bugs. The 606 * usermode code which understands the FPU hardware enough to enable 607 * the exceptions, can also handle clearing the exception state in the 608 * handler. The only consequence of not clearing the exception is the 609 * rethrow of the SIGFPE on return from the signal handler and 610 * reexecution of the corresponding instruction. 611 * 612 * For XMM traps, the exceptions were never cleared. 613 */ 614 int 615 fputrap_x87(void) 616 { 617 struct savefpu *pcb_save; 618 u_short control, status; 619 620 critical_enter(); 621 622 /* 623 * Interrupt handling (for another interrupt) may have pushed the 624 * state to memory. Fetch the relevant parts of the state from 625 * wherever they are. 626 */ 627 if (PCPU_GET(fpcurthread) != curthread) { 628 pcb_save = curpcb->pcb_save; 629 control = pcb_save->sv_env.en_cw; 630 status = pcb_save->sv_env.en_sw; 631 } else { 632 fnstcw(&control); 633 fnstsw(&status); 634 } 635 636 critical_exit(); 637 return (fpetable[status & ((~control & 0x3f) | 0x40)]); 638 } 639 640 int 641 fputrap_sse(void) 642 { 643 u_int mxcsr; 644 645 critical_enter(); 646 if (PCPU_GET(fpcurthread) != curthread) 647 mxcsr = curpcb->pcb_save->sv_env.en_mxcsr; 648 else 649 stmxcsr(&mxcsr); 650 critical_exit(); 651 return (fpetable[(mxcsr & (~mxcsr >> 7)) & 0x3f]); 652 } 653 654 /* 655 * Device Not Available (DNA, #NM) exception handler. 656 * 657 * It would be better to switch FP context here (if curthread != 658 * fpcurthread) and not necessarily for every context switch, but it 659 * is too hard to access foreign pcb's. 660 */ 661 void 662 fpudna(void) 663 { 664 665 /* 666 * This handler is entered with interrupts enabled, so context 667 * switches may occur before critical_enter() is executed. If 668 * a context switch occurs, then when we regain control, our 669 * state will have been completely restored. The CPU may 670 * change underneath us, but the only part of our context that 671 * lives in the CPU is CR0.TS and that will be "restored" by 672 * setting it on the new CPU. 673 */ 674 critical_enter(); 675 676 KASSERT((curpcb->pcb_flags & PCB_FPUNOSAVE) == 0, 677 ("fpudna while in fpu_kern_enter(FPU_KERN_NOCTX)")); 678 if (PCPU_GET(fpcurthread) == curthread) { 679 printf("fpudna: fpcurthread == curthread\n"); 680 stop_emulating(); 681 critical_exit(); 682 return; 683 } 684 if (PCPU_GET(fpcurthread) != NULL) { 685 panic("fpudna: fpcurthread = %p (%d), curthread = %p (%d)\n", 686 PCPU_GET(fpcurthread), PCPU_GET(fpcurthread)->td_tid, 687 curthread, curthread->td_tid); 688 } 689 stop_emulating(); 690 /* 691 * Record new context early in case frstor causes a trap. 692 */ 693 PCPU_SET(fpcurthread, curthread); 694 695 fpu_clean_state(); 696 697 if ((curpcb->pcb_flags & PCB_FPUINITDONE) == 0) { 698 /* 699 * This is the first time this thread has used the FPU or 700 * the PCB doesn't contain a clean FPU state. Explicitly 701 * load an initial state. 702 * 703 * We prefer to restore the state from the actual save 704 * area in PCB instead of directly loading from 705 * fpu_initialstate, to ignite the XSAVEOPT 706 * tracking engine. 707 */ 708 bcopy(fpu_initialstate, curpcb->pcb_save, 709 cpu_max_ext_state_size); 710 fpurestore(curpcb->pcb_save); 711 if (curpcb->pcb_initial_fpucw != __INITIAL_FPUCW__) 712 fldcw(curpcb->pcb_initial_fpucw); 713 if (PCB_USER_FPU(curpcb)) 714 set_pcb_flags(curpcb, 715 PCB_FPUINITDONE | PCB_USERFPUINITDONE); 716 else 717 set_pcb_flags(curpcb, PCB_FPUINITDONE); 718 } else 719 fpurestore(curpcb->pcb_save); 720 critical_exit(); 721 } 722 723 void 724 fpudrop(void) 725 { 726 struct thread *td; 727 728 td = PCPU_GET(fpcurthread); 729 KASSERT(td == curthread, ("fpudrop: fpcurthread != curthread")); 730 CRITICAL_ASSERT(td); 731 PCPU_SET(fpcurthread, NULL); 732 clear_pcb_flags(td->td_pcb, PCB_FPUINITDONE); 733 start_emulating(); 734 } 735 736 /* 737 * Get the user state of the FPU into pcb->pcb_user_save without 738 * dropping ownership (if possible). It returns the FPU ownership 739 * status. 740 */ 741 int 742 fpugetregs(struct thread *td) 743 { 744 struct pcb *pcb; 745 uint64_t *xstate_bv, bit; 746 char *sa; 747 int max_ext_n, i, owned; 748 749 pcb = td->td_pcb; 750 if ((pcb->pcb_flags & PCB_USERFPUINITDONE) == 0) { 751 bcopy(fpu_initialstate, get_pcb_user_save_pcb(pcb), 752 cpu_max_ext_state_size); 753 get_pcb_user_save_pcb(pcb)->sv_env.en_cw = 754 pcb->pcb_initial_fpucw; 755 fpuuserinited(td); 756 return (_MC_FPOWNED_PCB); 757 } 758 critical_enter(); 759 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) { 760 fpusave(get_pcb_user_save_pcb(pcb)); 761 owned = _MC_FPOWNED_FPU; 762 } else { 763 owned = _MC_FPOWNED_PCB; 764 } 765 critical_exit(); 766 if (use_xsave) { 767 /* 768 * Handle partially saved state. 769 */ 770 sa = (char *)get_pcb_user_save_pcb(pcb); 771 xstate_bv = (uint64_t *)(sa + sizeof(struct savefpu) + 772 offsetof(struct xstate_hdr, xstate_bv)); 773 max_ext_n = flsl(xsave_mask); 774 for (i = 0; i < max_ext_n; i++) { 775 bit = 1ULL << i; 776 if ((xsave_mask & bit) == 0 || (*xstate_bv & bit) != 0) 777 continue; 778 bcopy((char *)fpu_initialstate + 779 xsave_area_desc[i].offset, 780 sa + xsave_area_desc[i].offset, 781 xsave_area_desc[i].size); 782 *xstate_bv |= bit; 783 } 784 } 785 return (owned); 786 } 787 788 void 789 fpuuserinited(struct thread *td) 790 { 791 struct pcb *pcb; 792 793 pcb = td->td_pcb; 794 if (PCB_USER_FPU(pcb)) 795 set_pcb_flags(pcb, 796 PCB_FPUINITDONE | PCB_USERFPUINITDONE); 797 else 798 set_pcb_flags(pcb, PCB_FPUINITDONE); 799 } 800 801 int 802 fpusetxstate(struct thread *td, char *xfpustate, size_t xfpustate_size) 803 { 804 struct xstate_hdr *hdr, *ehdr; 805 size_t len, max_len; 806 uint64_t bv; 807 808 /* XXXKIB should we clear all extended state in xstate_bv instead ? */ 809 if (xfpustate == NULL) 810 return (0); 811 if (!use_xsave) 812 return (EOPNOTSUPP); 813 814 len = xfpustate_size; 815 if (len < sizeof(struct xstate_hdr)) 816 return (EINVAL); 817 max_len = cpu_max_ext_state_size - sizeof(struct savefpu); 818 if (len > max_len) 819 return (EINVAL); 820 821 ehdr = (struct xstate_hdr *)xfpustate; 822 bv = ehdr->xstate_bv; 823 824 /* 825 * Avoid #gp. 826 */ 827 if (bv & ~xsave_mask) 828 return (EINVAL); 829 830 hdr = (struct xstate_hdr *)(get_pcb_user_save_td(td) + 1); 831 832 hdr->xstate_bv = bv; 833 bcopy(xfpustate + sizeof(struct xstate_hdr), 834 (char *)(hdr + 1), len - sizeof(struct xstate_hdr)); 835 836 return (0); 837 } 838 839 /* 840 * Set the state of the FPU. 841 */ 842 int 843 fpusetregs(struct thread *td, struct savefpu *addr, char *xfpustate, 844 size_t xfpustate_size) 845 { 846 struct pcb *pcb; 847 int error; 848 849 addr->sv_env.en_mxcsr &= cpu_mxcsr_mask; 850 pcb = td->td_pcb; 851 critical_enter(); 852 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) { 853 error = fpusetxstate(td, xfpustate, xfpustate_size); 854 if (error != 0) { 855 critical_exit(); 856 return (error); 857 } 858 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr)); 859 fpurestore(get_pcb_user_save_td(td)); 860 critical_exit(); 861 set_pcb_flags(pcb, PCB_FPUINITDONE | PCB_USERFPUINITDONE); 862 } else { 863 critical_exit(); 864 error = fpusetxstate(td, xfpustate, xfpustate_size); 865 if (error != 0) 866 return (error); 867 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr)); 868 fpuuserinited(td); 869 } 870 return (0); 871 } 872 873 /* 874 * On AuthenticAMD processors, the fxrstor instruction does not restore 875 * the x87's stored last instruction pointer, last data pointer, and last 876 * opcode values, except in the rare case in which the exception summary 877 * (ES) bit in the x87 status word is set to 1. 878 * 879 * In order to avoid leaking this information across processes, we clean 880 * these values by performing a dummy load before executing fxrstor(). 881 */ 882 static void 883 fpu_clean_state(void) 884 { 885 static float dummy_variable = 0.0; 886 u_short status; 887 888 /* 889 * Clear the ES bit in the x87 status word if it is currently 890 * set, in order to avoid causing a fault in the upcoming load. 891 */ 892 fnstsw(&status); 893 if (status & 0x80) 894 fnclex(); 895 896 /* 897 * Load the dummy variable into the x87 stack. This mangles 898 * the x87 stack, but we don't care since we're about to call 899 * fxrstor() anyway. 900 */ 901 __asm __volatile("ffree %%st(7); flds %0" : : "m" (dummy_variable)); 902 } 903 904 /* 905 * This really sucks. We want the acpi version only, but it requires 906 * the isa_if.h file in order to get the definitions. 907 */ 908 #include "opt_isa.h" 909 #ifdef DEV_ISA 910 #include <isa/isavar.h> 911 /* 912 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI. 913 */ 914 static struct isa_pnp_id fpupnp_ids[] = { 915 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */ 916 { 0 } 917 }; 918 919 static int 920 fpupnp_probe(device_t dev) 921 { 922 int result; 923 924 result = ISA_PNP_PROBE(device_get_parent(dev), dev, fpupnp_ids); 925 if (result <= 0) 926 device_quiet(dev); 927 return (result); 928 } 929 930 static int 931 fpupnp_attach(device_t dev) 932 { 933 934 return (0); 935 } 936 937 static device_method_t fpupnp_methods[] = { 938 /* Device interface */ 939 DEVMETHOD(device_probe, fpupnp_probe), 940 DEVMETHOD(device_attach, fpupnp_attach), 941 DEVMETHOD(device_detach, bus_generic_detach), 942 DEVMETHOD(device_shutdown, bus_generic_shutdown), 943 DEVMETHOD(device_suspend, bus_generic_suspend), 944 DEVMETHOD(device_resume, bus_generic_resume), 945 946 { 0, 0 } 947 }; 948 949 static driver_t fpupnp_driver = { 950 "fpupnp", 951 fpupnp_methods, 952 1, /* no softc */ 953 }; 954 955 static devclass_t fpupnp_devclass; 956 957 DRIVER_MODULE(fpupnp, acpi, fpupnp_driver, fpupnp_devclass, 0, 0); 958 ISA_PNP_INFO(fpupnp_ids); 959 #endif /* DEV_ISA */ 960 961 static MALLOC_DEFINE(M_FPUKERN_CTX, "fpukern_ctx", 962 "Kernel contexts for FPU state"); 963 964 #define FPU_KERN_CTX_FPUINITDONE 0x01 965 #define FPU_KERN_CTX_DUMMY 0x02 /* avoided save for the kern thread */ 966 #define FPU_KERN_CTX_INUSE 0x04 967 968 struct fpu_kern_ctx { 969 struct savefpu *prev; 970 uint32_t flags; 971 char hwstate1[]; 972 }; 973 974 struct fpu_kern_ctx * 975 fpu_kern_alloc_ctx(u_int flags) 976 { 977 struct fpu_kern_ctx *res; 978 size_t sz; 979 980 sz = sizeof(struct fpu_kern_ctx) + XSAVE_AREA_ALIGN + 981 cpu_max_ext_state_size; 982 res = malloc(sz, M_FPUKERN_CTX, ((flags & FPU_KERN_NOWAIT) ? 983 M_NOWAIT : M_WAITOK) | M_ZERO); 984 return (res); 985 } 986 987 void 988 fpu_kern_free_ctx(struct fpu_kern_ctx *ctx) 989 { 990 991 KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) == 0, ("free'ing inuse ctx")); 992 /* XXXKIB clear the memory ? */ 993 free(ctx, M_FPUKERN_CTX); 994 } 995 996 static struct savefpu * 997 fpu_kern_ctx_savefpu(struct fpu_kern_ctx *ctx) 998 { 999 vm_offset_t p; 1000 1001 p = (vm_offset_t)&ctx->hwstate1; 1002 p = roundup2(p, XSAVE_AREA_ALIGN); 1003 return ((struct savefpu *)p); 1004 } 1005 1006 void 1007 fpu_kern_enter(struct thread *td, struct fpu_kern_ctx *ctx, u_int flags) 1008 { 1009 struct pcb *pcb; 1010 1011 pcb = td->td_pcb; 1012 KASSERT((flags & FPU_KERN_NOCTX) != 0 || ctx != NULL, 1013 ("ctx is required when !FPU_KERN_NOCTX")); 1014 KASSERT(ctx == NULL || (ctx->flags & FPU_KERN_CTX_INUSE) == 0, 1015 ("using inuse ctx")); 1016 KASSERT((pcb->pcb_flags & PCB_FPUNOSAVE) == 0, 1017 ("recursive fpu_kern_enter while in PCB_FPUNOSAVE state")); 1018 1019 if ((flags & FPU_KERN_NOCTX) != 0) { 1020 critical_enter(); 1021 stop_emulating(); 1022 if (curthread == PCPU_GET(fpcurthread)) { 1023 fpusave(curpcb->pcb_save); 1024 PCPU_SET(fpcurthread, NULL); 1025 } else { 1026 KASSERT(PCPU_GET(fpcurthread) == NULL, 1027 ("invalid fpcurthread")); 1028 } 1029 1030 /* 1031 * This breaks XSAVEOPT tracker, but 1032 * PCB_FPUNOSAVE state is supposed to never need to 1033 * save FPU context at all. 1034 */ 1035 fpurestore(fpu_initialstate); 1036 set_pcb_flags(pcb, PCB_KERNFPU | PCB_FPUNOSAVE | 1037 PCB_FPUINITDONE); 1038 return; 1039 } 1040 if ((flags & FPU_KERN_KTHR) != 0 && is_fpu_kern_thread(0)) { 1041 ctx->flags = FPU_KERN_CTX_DUMMY | FPU_KERN_CTX_INUSE; 1042 return; 1043 } 1044 KASSERT(!PCB_USER_FPU(pcb) || pcb->pcb_save == 1045 get_pcb_user_save_pcb(pcb), ("mangled pcb_save")); 1046 ctx->flags = FPU_KERN_CTX_INUSE; 1047 if ((pcb->pcb_flags & PCB_FPUINITDONE) != 0) 1048 ctx->flags |= FPU_KERN_CTX_FPUINITDONE; 1049 fpuexit(td); 1050 ctx->prev = pcb->pcb_save; 1051 pcb->pcb_save = fpu_kern_ctx_savefpu(ctx); 1052 set_pcb_flags(pcb, PCB_KERNFPU); 1053 clear_pcb_flags(pcb, PCB_FPUINITDONE); 1054 return; 1055 } 1056 1057 int 1058 fpu_kern_leave(struct thread *td, struct fpu_kern_ctx *ctx) 1059 { 1060 struct pcb *pcb; 1061 1062 pcb = td->td_pcb; 1063 1064 if ((pcb->pcb_flags & PCB_FPUNOSAVE) != 0) { 1065 KASSERT(ctx == NULL, ("non-null ctx after FPU_KERN_NOCTX")); 1066 KASSERT(PCPU_GET(fpcurthread) == NULL, 1067 ("non-NULL fpcurthread for PCB_FPUNOSAVE")); 1068 CRITICAL_ASSERT(td); 1069 1070 clear_pcb_flags(pcb, PCB_FPUNOSAVE | PCB_FPUINITDONE); 1071 start_emulating(); 1072 critical_exit(); 1073 } else { 1074 KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) != 0, 1075 ("leaving not inuse ctx")); 1076 ctx->flags &= ~FPU_KERN_CTX_INUSE; 1077 1078 if (is_fpu_kern_thread(0) && 1079 (ctx->flags & FPU_KERN_CTX_DUMMY) != 0) 1080 return (0); 1081 KASSERT((ctx->flags & FPU_KERN_CTX_DUMMY) == 0, 1082 ("dummy ctx")); 1083 critical_enter(); 1084 if (curthread == PCPU_GET(fpcurthread)) 1085 fpudrop(); 1086 critical_exit(); 1087 pcb->pcb_save = ctx->prev; 1088 } 1089 1090 if (pcb->pcb_save == get_pcb_user_save_pcb(pcb)) { 1091 if ((pcb->pcb_flags & PCB_USERFPUINITDONE) != 0) { 1092 set_pcb_flags(pcb, PCB_FPUINITDONE); 1093 clear_pcb_flags(pcb, PCB_KERNFPU); 1094 } else 1095 clear_pcb_flags(pcb, PCB_FPUINITDONE | PCB_KERNFPU); 1096 } else { 1097 if ((ctx->flags & FPU_KERN_CTX_FPUINITDONE) != 0) 1098 set_pcb_flags(pcb, PCB_FPUINITDONE); 1099 else 1100 clear_pcb_flags(pcb, PCB_FPUINITDONE); 1101 KASSERT(!PCB_USER_FPU(pcb), ("unpaired fpu_kern_leave")); 1102 } 1103 return (0); 1104 } 1105 1106 int 1107 fpu_kern_thread(u_int flags) 1108 { 1109 1110 KASSERT((curthread->td_pflags & TDP_KTHREAD) != 0, 1111 ("Only kthread may use fpu_kern_thread")); 1112 KASSERT(curpcb->pcb_save == get_pcb_user_save_pcb(curpcb), 1113 ("mangled pcb_save")); 1114 KASSERT(PCB_USER_FPU(curpcb), ("recursive call")); 1115 1116 set_pcb_flags(curpcb, PCB_KERNFPU); 1117 return (0); 1118 } 1119 1120 int 1121 is_fpu_kern_thread(u_int flags) 1122 { 1123 1124 if ((curthread->td_pflags & TDP_KTHREAD) == 0) 1125 return (0); 1126 return ((curpcb->pcb_flags & PCB_KERNFPU) != 0); 1127 } 1128 1129 /* 1130 * FPU save area alloc/free/init utility routines 1131 */ 1132 struct savefpu * 1133 fpu_save_area_alloc(void) 1134 { 1135 1136 return (uma_zalloc(fpu_save_area_zone, 0)); 1137 } 1138 1139 void 1140 fpu_save_area_free(struct savefpu *fsa) 1141 { 1142 1143 uma_zfree(fpu_save_area_zone, fsa); 1144 } 1145 1146 void 1147 fpu_save_area_reset(struct savefpu *fsa) 1148 { 1149 1150 bcopy(fpu_initialstate, fsa, cpu_max_ext_state_size); 1151 } 1152