1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 1990 William Jolitz. 5 * Copyright (c) 1991 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of the University nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 33 */ 34 35 #include <sys/cdefs.h> 36 __FBSDID("$FreeBSD$"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/bus.h> 41 #include <sys/domainset.h> 42 #include <sys/kernel.h> 43 #include <sys/lock.h> 44 #include <sys/malloc.h> 45 #include <sys/module.h> 46 #include <sys/mutex.h> 47 #include <sys/mutex.h> 48 #include <sys/proc.h> 49 #include <sys/sysctl.h> 50 #include <sys/sysent.h> 51 #include <machine/bus.h> 52 #include <sys/rman.h> 53 #include <sys/signalvar.h> 54 #include <vm/uma.h> 55 56 #include <machine/cputypes.h> 57 #include <machine/frame.h> 58 #include <machine/intr_machdep.h> 59 #include <machine/md_var.h> 60 #include <machine/pcb.h> 61 #include <machine/psl.h> 62 #include <machine/resource.h> 63 #include <machine/specialreg.h> 64 #include <machine/segments.h> 65 #include <machine/ucontext.h> 66 #include <x86/ifunc.h> 67 68 /* 69 * Floating point support. 70 */ 71 72 #if defined(__GNUCLIKE_ASM) && !defined(lint) 73 74 #define fldcw(cw) __asm __volatile("fldcw %0" : : "m" (cw)) 75 #define fnclex() __asm __volatile("fnclex") 76 #define fninit() __asm __volatile("fninit") 77 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 78 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=am" (*(addr))) 79 #define fxrstor(addr) __asm __volatile("fxrstor %0" : : "m" (*(addr))) 80 #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 81 #define ldmxcsr(csr) __asm __volatile("ldmxcsr %0" : : "m" (csr)) 82 #define stmxcsr(addr) __asm __volatile("stmxcsr %0" : "=m" (*(addr))) 83 84 static __inline void 85 xrstor32(char *addr, uint64_t mask) 86 { 87 uint32_t low, hi; 88 89 low = mask; 90 hi = mask >> 32; 91 __asm __volatile("xrstor %0" : : "m" (*addr), "a" (low), "d" (hi)); 92 } 93 94 static __inline void 95 xrstor64(char *addr, uint64_t mask) 96 { 97 uint32_t low, hi; 98 99 low = mask; 100 hi = mask >> 32; 101 __asm __volatile("xrstor64 %0" : : "m" (*addr), "a" (low), "d" (hi)); 102 } 103 104 static __inline void 105 xsave32(char *addr, uint64_t mask) 106 { 107 uint32_t low, hi; 108 109 low = mask; 110 hi = mask >> 32; 111 __asm __volatile("xsave %0" : "=m" (*addr) : "a" (low), "d" (hi) : 112 "memory"); 113 } 114 115 static __inline void 116 xsave64(char *addr, uint64_t mask) 117 { 118 uint32_t low, hi; 119 120 low = mask; 121 hi = mask >> 32; 122 __asm __volatile("xsave64 %0" : "=m" (*addr) : "a" (low), "d" (hi) : 123 "memory"); 124 } 125 126 static __inline void 127 xsaveopt32(char *addr, uint64_t mask) 128 { 129 uint32_t low, hi; 130 131 low = mask; 132 hi = mask >> 32; 133 __asm __volatile("xsaveopt %0" : "=m" (*addr) : "a" (low), "d" (hi) : 134 "memory"); 135 } 136 137 static __inline void 138 xsaveopt64(char *addr, uint64_t mask) 139 { 140 uint32_t low, hi; 141 142 low = mask; 143 hi = mask >> 32; 144 __asm __volatile("xsaveopt64 %0" : "=m" (*addr) : "a" (low), "d" (hi) : 145 "memory"); 146 } 147 148 #else /* !(__GNUCLIKE_ASM && !lint) */ 149 150 void fldcw(u_short cw); 151 void fnclex(void); 152 void fninit(void); 153 void fnstcw(caddr_t addr); 154 void fnstsw(caddr_t addr); 155 void fxsave(caddr_t addr); 156 void fxrstor(caddr_t addr); 157 void ldmxcsr(u_int csr); 158 void stmxcsr(u_int *csr); 159 void xrstor32(char *addr, uint64_t mask); 160 void xrstor64(char *addr, uint64_t mask); 161 void xsave32(char *addr, uint64_t mask); 162 void xsave64(char *addr, uint64_t mask); 163 void xsaveopt32(char *addr, uint64_t mask); 164 void xsaveopt64(char *addr, uint64_t mask); 165 166 #endif /* __GNUCLIKE_ASM && !lint */ 167 168 #define start_emulating() load_cr0(rcr0() | CR0_TS) 169 #define stop_emulating() clts() 170 171 CTASSERT(sizeof(struct savefpu) == 512); 172 CTASSERT(sizeof(struct xstate_hdr) == 64); 173 CTASSERT(sizeof(struct savefpu_ymm) == 832); 174 175 /* 176 * This requirement is to make it easier for asm code to calculate 177 * offset of the fpu save area from the pcb address. FPU save area 178 * must be 64-byte aligned. 179 */ 180 CTASSERT(sizeof(struct pcb) % XSAVE_AREA_ALIGN == 0); 181 182 /* 183 * Ensure the copy of XCR0 saved in a core is contained in the padding 184 * area. 185 */ 186 CTASSERT(X86_XSTATE_XCR0_OFFSET >= offsetof(struct savefpu, sv_pad) && 187 X86_XSTATE_XCR0_OFFSET + sizeof(uint64_t) <= sizeof(struct savefpu)); 188 189 static void fpu_clean_state(void); 190 191 SYSCTL_INT(_hw, HW_FLOATINGPT, floatingpoint, CTLFLAG_RD, 192 SYSCTL_NULL_INT_PTR, 1, "Floating point instructions executed in hardware"); 193 194 int use_xsave; /* non-static for cpu_switch.S */ 195 uint64_t xsave_mask; /* the same */ 196 static uma_zone_t fpu_save_area_zone; 197 static struct savefpu *fpu_initialstate; 198 199 static struct xsave_area_elm_descr { 200 u_int offset; 201 u_int size; 202 } *xsave_area_desc; 203 204 static void 205 fpusave_xsaveopt64(void *addr) 206 { 207 xsaveopt64((char *)addr, xsave_mask); 208 } 209 210 static void 211 fpusave_xsaveopt3264(void *addr) 212 { 213 if (SV_CURPROC_FLAG(SV_ILP32)) 214 xsaveopt32((char *)addr, xsave_mask); 215 else 216 xsaveopt64((char *)addr, xsave_mask); 217 } 218 219 static void 220 fpusave_xsave64(void *addr) 221 { 222 xsave64((char *)addr, xsave_mask); 223 } 224 225 static void 226 fpusave_xsave3264(void *addr) 227 { 228 if (SV_CURPROC_FLAG(SV_ILP32)) 229 xsave32((char *)addr, xsave_mask); 230 else 231 xsave64((char *)addr, xsave_mask); 232 } 233 234 static void 235 fpurestore_xrstor64(void *addr) 236 { 237 xrstor64((char *)addr, xsave_mask); 238 } 239 240 static void 241 fpurestore_xrstor3264(void *addr) 242 { 243 if (SV_CURPROC_FLAG(SV_ILP32)) 244 xrstor32((char *)addr, xsave_mask); 245 else 246 xrstor64((char *)addr, xsave_mask); 247 } 248 249 static void 250 fpusave_fxsave(void *addr) 251 { 252 253 fxsave((char *)addr); 254 } 255 256 static void 257 fpurestore_fxrstor(void *addr) 258 { 259 260 fxrstor((char *)addr); 261 } 262 263 static void 264 init_xsave(void) 265 { 266 267 if (use_xsave) 268 return; 269 if ((cpu_feature2 & CPUID2_XSAVE) == 0) 270 return; 271 use_xsave = 1; 272 TUNABLE_INT_FETCH("hw.use_xsave", &use_xsave); 273 } 274 275 DEFINE_IFUNC(, void, fpusave, (void *)) 276 { 277 278 init_xsave(); 279 if (!use_xsave) 280 return (fpusave_fxsave); 281 if ((cpu_stdext_feature & CPUID_EXTSTATE_XSAVEOPT) != 0) { 282 return ((cpu_stdext_feature & CPUID_STDEXT_NFPUSG) != 0 ? 283 fpusave_xsaveopt64 : fpusave_xsaveopt3264); 284 } 285 return ((cpu_stdext_feature & CPUID_STDEXT_NFPUSG) != 0 ? 286 fpusave_xsave64 : fpusave_xsave3264); 287 } 288 289 DEFINE_IFUNC(, void, fpurestore, (void *)) 290 { 291 292 init_xsave(); 293 if (!use_xsave) 294 return (fpurestore_fxrstor); 295 return ((cpu_stdext_feature & CPUID_STDEXT_NFPUSG) != 0 ? 296 fpurestore_xrstor64 : fpurestore_xrstor3264); 297 } 298 299 void 300 fpususpend(void *addr) 301 { 302 u_long cr0; 303 304 cr0 = rcr0(); 305 stop_emulating(); 306 fpusave(addr); 307 load_cr0(cr0); 308 } 309 310 void 311 fpuresume(void *addr) 312 { 313 u_long cr0; 314 315 cr0 = rcr0(); 316 stop_emulating(); 317 fninit(); 318 if (use_xsave) 319 load_xcr(XCR0, xsave_mask); 320 fpurestore(addr); 321 load_cr0(cr0); 322 } 323 324 /* 325 * Enable XSAVE if supported and allowed by user. 326 * Calculate the xsave_mask. 327 */ 328 static void 329 fpuinit_bsp1(void) 330 { 331 u_int cp[4]; 332 uint64_t xsave_mask_user; 333 bool old_wp; 334 335 if (!use_xsave) 336 return; 337 cpuid_count(0xd, 0x0, cp); 338 xsave_mask = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE; 339 if ((cp[0] & xsave_mask) != xsave_mask) 340 panic("CPU0 does not support X87 or SSE: %x", cp[0]); 341 xsave_mask = ((uint64_t)cp[3] << 32) | cp[0]; 342 xsave_mask_user = xsave_mask; 343 TUNABLE_ULONG_FETCH("hw.xsave_mask", &xsave_mask_user); 344 xsave_mask_user |= XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE; 345 xsave_mask &= xsave_mask_user; 346 if ((xsave_mask & XFEATURE_AVX512) != XFEATURE_AVX512) 347 xsave_mask &= ~XFEATURE_AVX512; 348 if ((xsave_mask & XFEATURE_MPX) != XFEATURE_MPX) 349 xsave_mask &= ~XFEATURE_MPX; 350 351 cpuid_count(0xd, 0x1, cp); 352 if ((cp[0] & CPUID_EXTSTATE_XSAVEOPT) != 0) { 353 /* 354 * Patch the XSAVE instruction in the cpu_switch code 355 * to XSAVEOPT. We assume that XSAVE encoding used 356 * REX byte, and set the bit 4 of the r/m byte. 357 * 358 * It seems that some BIOSes give control to the OS 359 * with CR0.WP already set, making the kernel text 360 * read-only before cpu_startup(). 361 */ 362 old_wp = disable_wp(); 363 ctx_switch_xsave32[3] |= 0x10; 364 ctx_switch_xsave[3] |= 0x10; 365 restore_wp(old_wp); 366 } 367 } 368 369 /* 370 * Calculate the fpu save area size. 371 */ 372 static void 373 fpuinit_bsp2(void) 374 { 375 u_int cp[4]; 376 377 if (use_xsave) { 378 cpuid_count(0xd, 0x0, cp); 379 cpu_max_ext_state_size = cp[1]; 380 381 /* 382 * Reload the cpu_feature2, since we enabled OSXSAVE. 383 */ 384 do_cpuid(1, cp); 385 cpu_feature2 = cp[2]; 386 } else 387 cpu_max_ext_state_size = sizeof(struct savefpu); 388 } 389 390 /* 391 * Initialize the floating point unit. 392 */ 393 void 394 fpuinit(void) 395 { 396 register_t saveintr; 397 u_int mxcsr; 398 u_short control; 399 400 if (IS_BSP()) 401 fpuinit_bsp1(); 402 403 if (use_xsave) { 404 load_cr4(rcr4() | CR4_XSAVE); 405 load_xcr(XCR0, xsave_mask); 406 } 407 408 /* 409 * XCR0 shall be set up before CPU can report the save area size. 410 */ 411 if (IS_BSP()) 412 fpuinit_bsp2(); 413 414 /* 415 * It is too early for critical_enter() to work on AP. 416 */ 417 saveintr = intr_disable(); 418 stop_emulating(); 419 fninit(); 420 control = __INITIAL_FPUCW__; 421 fldcw(control); 422 mxcsr = __INITIAL_MXCSR__; 423 ldmxcsr(mxcsr); 424 start_emulating(); 425 intr_restore(saveintr); 426 } 427 428 /* 429 * On the boot CPU we generate a clean state that is used to 430 * initialize the floating point unit when it is first used by a 431 * process. 432 */ 433 static void 434 fpuinitstate(void *arg __unused) 435 { 436 uint64_t *xstate_bv; 437 register_t saveintr; 438 int cp[4], i, max_ext_n; 439 440 /* Do potentially blocking operations before disabling interrupts. */ 441 fpu_save_area_zone = uma_zcreate("FPU_save_area", 442 cpu_max_ext_state_size, NULL, NULL, NULL, NULL, 443 XSAVE_AREA_ALIGN - 1, 0); 444 fpu_initialstate = uma_zalloc(fpu_save_area_zone, M_WAITOK | M_ZERO); 445 if (use_xsave) { 446 max_ext_n = flsl(xsave_mask); 447 xsave_area_desc = malloc(max_ext_n * sizeof(struct 448 xsave_area_elm_descr), M_DEVBUF, M_WAITOK | M_ZERO); 449 } 450 451 cpu_thread_alloc(&thread0); 452 453 saveintr = intr_disable(); 454 stop_emulating(); 455 456 fpusave_fxsave(fpu_initialstate); 457 if (fpu_initialstate->sv_env.en_mxcsr_mask) 458 cpu_mxcsr_mask = fpu_initialstate->sv_env.en_mxcsr_mask; 459 else 460 cpu_mxcsr_mask = 0xFFBF; 461 462 /* 463 * The fninit instruction does not modify XMM registers or x87 464 * registers (MM/ST). The fpusave call dumped the garbage 465 * contained in the registers after reset to the initial state 466 * saved. Clear XMM and x87 registers file image to make the 467 * startup program state and signal handler XMM/x87 register 468 * content predictable. 469 */ 470 bzero(fpu_initialstate->sv_fp, sizeof(fpu_initialstate->sv_fp)); 471 bzero(fpu_initialstate->sv_xmm, sizeof(fpu_initialstate->sv_xmm)); 472 473 /* 474 * Create a table describing the layout of the CPU Extended 475 * Save Area. See Intel SDM rev. 075 Vol. 1 13.4.1 "Legacy 476 * Region of an XSAVE Area" for the source of offsets/sizes. 477 */ 478 if (use_xsave) { 479 xstate_bv = (uint64_t *)((char *)(fpu_initialstate + 1) + 480 offsetof(struct xstate_hdr, xstate_bv)); 481 *xstate_bv = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE; 482 483 /* x87 state */ 484 xsave_area_desc[0].offset = 0; 485 xsave_area_desc[0].size = 160; 486 /* XMM */ 487 xsave_area_desc[1].offset = 160; 488 xsave_area_desc[1].size = 416 - 160; 489 490 for (i = 2; i < max_ext_n; i++) { 491 cpuid_count(0xd, i, cp); 492 xsave_area_desc[i].offset = cp[1]; 493 xsave_area_desc[i].size = cp[0]; 494 } 495 } 496 497 start_emulating(); 498 intr_restore(saveintr); 499 } 500 /* EFIRT needs this to be initialized before we can enter our EFI environment */ 501 SYSINIT(fpuinitstate, SI_SUB_CPU, SI_ORDER_ANY, fpuinitstate, NULL); 502 503 /* 504 * Free coprocessor (if we have it). 505 */ 506 void 507 fpuexit(struct thread *td) 508 { 509 510 critical_enter(); 511 if (curthread == PCPU_GET(fpcurthread)) { 512 stop_emulating(); 513 fpusave(curpcb->pcb_save); 514 start_emulating(); 515 PCPU_SET(fpcurthread, NULL); 516 } 517 critical_exit(); 518 } 519 520 int 521 fpuformat(void) 522 { 523 524 return (_MC_FPFMT_XMM); 525 } 526 527 /* 528 * The following mechanism is used to ensure that the FPE_... value 529 * that is passed as a trapcode to the signal handler of the user 530 * process does not have more than one bit set. 531 * 532 * Multiple bits may be set if the user process modifies the control 533 * word while a status word bit is already set. While this is a sign 534 * of bad coding, we have no choise than to narrow them down to one 535 * bit, since we must not send a trapcode that is not exactly one of 536 * the FPE_ macros. 537 * 538 * The mechanism has a static table with 127 entries. Each combination 539 * of the 7 FPU status word exception bits directly translates to a 540 * position in this table, where a single FPE_... value is stored. 541 * This FPE_... value stored there is considered the "most important" 542 * of the exception bits and will be sent as the signal code. The 543 * precedence of the bits is based upon Intel Document "Numerical 544 * Applications", Chapter "Special Computational Situations". 545 * 546 * The macro to choose one of these values does these steps: 1) Throw 547 * away status word bits that cannot be masked. 2) Throw away the bits 548 * currently masked in the control word, assuming the user isn't 549 * interested in them anymore. 3) Reinsert status word bit 7 (stack 550 * fault) if it is set, which cannot be masked but must be presered. 551 * 4) Use the remaining bits to point into the trapcode table. 552 * 553 * The 6 maskable bits in order of their preference, as stated in the 554 * above referenced Intel manual: 555 * 1 Invalid operation (FP_X_INV) 556 * 1a Stack underflow 557 * 1b Stack overflow 558 * 1c Operand of unsupported format 559 * 1d SNaN operand. 560 * 2 QNaN operand (not an exception, irrelavant here) 561 * 3 Any other invalid-operation not mentioned above or zero divide 562 * (FP_X_INV, FP_X_DZ) 563 * 4 Denormal operand (FP_X_DNML) 564 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 565 * 6 Inexact result (FP_X_IMP) 566 */ 567 static char fpetable[128] = { 568 0, 569 FPE_FLTINV, /* 1 - INV */ 570 FPE_FLTUND, /* 2 - DNML */ 571 FPE_FLTINV, /* 3 - INV | DNML */ 572 FPE_FLTDIV, /* 4 - DZ */ 573 FPE_FLTINV, /* 5 - INV | DZ */ 574 FPE_FLTDIV, /* 6 - DNML | DZ */ 575 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 576 FPE_FLTOVF, /* 8 - OFL */ 577 FPE_FLTINV, /* 9 - INV | OFL */ 578 FPE_FLTUND, /* A - DNML | OFL */ 579 FPE_FLTINV, /* B - INV | DNML | OFL */ 580 FPE_FLTDIV, /* C - DZ | OFL */ 581 FPE_FLTINV, /* D - INV | DZ | OFL */ 582 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 583 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 584 FPE_FLTUND, /* 10 - UFL */ 585 FPE_FLTINV, /* 11 - INV | UFL */ 586 FPE_FLTUND, /* 12 - DNML | UFL */ 587 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 588 FPE_FLTDIV, /* 14 - DZ | UFL */ 589 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 590 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 591 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 592 FPE_FLTOVF, /* 18 - OFL | UFL */ 593 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 594 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 595 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 596 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 597 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 598 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 599 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 600 FPE_FLTRES, /* 20 - IMP */ 601 FPE_FLTINV, /* 21 - INV | IMP */ 602 FPE_FLTUND, /* 22 - DNML | IMP */ 603 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 604 FPE_FLTDIV, /* 24 - DZ | IMP */ 605 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 606 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 607 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 608 FPE_FLTOVF, /* 28 - OFL | IMP */ 609 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 610 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 611 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 612 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 613 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 614 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 615 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 616 FPE_FLTUND, /* 30 - UFL | IMP */ 617 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 618 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 619 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 620 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 621 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 622 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 623 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 624 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 625 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 626 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 627 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 628 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 629 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 630 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 631 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 632 FPE_FLTSUB, /* 40 - STK */ 633 FPE_FLTSUB, /* 41 - INV | STK */ 634 FPE_FLTUND, /* 42 - DNML | STK */ 635 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 636 FPE_FLTDIV, /* 44 - DZ | STK */ 637 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 638 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 639 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 640 FPE_FLTOVF, /* 48 - OFL | STK */ 641 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 642 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 643 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 644 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 645 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 646 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 647 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 648 FPE_FLTUND, /* 50 - UFL | STK */ 649 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 650 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 651 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 652 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 653 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 654 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 655 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 656 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 657 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 658 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 659 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 660 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 661 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 662 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 663 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 664 FPE_FLTRES, /* 60 - IMP | STK */ 665 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 666 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 667 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 668 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 669 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 670 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 671 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 672 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 673 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 674 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 675 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 676 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 677 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 678 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 679 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 680 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 681 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 682 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 683 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 684 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 685 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 686 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 687 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 688 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 689 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 690 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 691 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 692 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 693 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 694 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 695 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 696 }; 697 698 /* 699 * Read the FP status and control words, then generate si_code value 700 * for SIGFPE. The error code chosen will be one of the 701 * FPE_... macros. It will be sent as the second argument to old 702 * BSD-style signal handlers and as "siginfo_t->si_code" (second 703 * argument) to SA_SIGINFO signal handlers. 704 * 705 * Some time ago, we cleared the x87 exceptions with FNCLEX there. 706 * Clearing exceptions was necessary mainly to avoid IRQ13 bugs. The 707 * usermode code which understands the FPU hardware enough to enable 708 * the exceptions, can also handle clearing the exception state in the 709 * handler. The only consequence of not clearing the exception is the 710 * rethrow of the SIGFPE on return from the signal handler and 711 * reexecution of the corresponding instruction. 712 * 713 * For XMM traps, the exceptions were never cleared. 714 */ 715 int 716 fputrap_x87(void) 717 { 718 struct savefpu *pcb_save; 719 u_short control, status; 720 721 critical_enter(); 722 723 /* 724 * Interrupt handling (for another interrupt) may have pushed the 725 * state to memory. Fetch the relevant parts of the state from 726 * wherever they are. 727 */ 728 if (PCPU_GET(fpcurthread) != curthread) { 729 pcb_save = curpcb->pcb_save; 730 control = pcb_save->sv_env.en_cw; 731 status = pcb_save->sv_env.en_sw; 732 } else { 733 fnstcw(&control); 734 fnstsw(&status); 735 } 736 737 critical_exit(); 738 return (fpetable[status & ((~control & 0x3f) | 0x40)]); 739 } 740 741 int 742 fputrap_sse(void) 743 { 744 u_int mxcsr; 745 746 critical_enter(); 747 if (PCPU_GET(fpcurthread) != curthread) 748 mxcsr = curpcb->pcb_save->sv_env.en_mxcsr; 749 else 750 stmxcsr(&mxcsr); 751 critical_exit(); 752 return (fpetable[(mxcsr & (~mxcsr >> 7)) & 0x3f]); 753 } 754 755 static void 756 restore_fpu_curthread(struct thread *td) 757 { 758 struct pcb *pcb; 759 760 /* 761 * Record new context early in case frstor causes a trap. 762 */ 763 PCPU_SET(fpcurthread, td); 764 765 stop_emulating(); 766 fpu_clean_state(); 767 pcb = td->td_pcb; 768 769 if ((pcb->pcb_flags & PCB_FPUINITDONE) == 0) { 770 /* 771 * This is the first time this thread has used the FPU or 772 * the PCB doesn't contain a clean FPU state. Explicitly 773 * load an initial state. 774 * 775 * We prefer to restore the state from the actual save 776 * area in PCB instead of directly loading from 777 * fpu_initialstate, to ignite the XSAVEOPT 778 * tracking engine. 779 */ 780 bcopy(fpu_initialstate, pcb->pcb_save, 781 cpu_max_ext_state_size); 782 fpurestore(pcb->pcb_save); 783 if (pcb->pcb_initial_fpucw != __INITIAL_FPUCW__) 784 fldcw(pcb->pcb_initial_fpucw); 785 if (PCB_USER_FPU(pcb)) 786 set_pcb_flags(pcb, PCB_FPUINITDONE | 787 PCB_USERFPUINITDONE); 788 else 789 set_pcb_flags(pcb, PCB_FPUINITDONE); 790 } else 791 fpurestore(pcb->pcb_save); 792 } 793 794 /* 795 * Device Not Available (DNA, #NM) exception handler. 796 * 797 * It would be better to switch FP context here (if curthread != 798 * fpcurthread) and not necessarily for every context switch, but it 799 * is too hard to access foreign pcb's. 800 */ 801 void 802 fpudna(void) 803 { 804 struct thread *td; 805 806 td = curthread; 807 /* 808 * This handler is entered with interrupts enabled, so context 809 * switches may occur before critical_enter() is executed. If 810 * a context switch occurs, then when we regain control, our 811 * state will have been completely restored. The CPU may 812 * change underneath us, but the only part of our context that 813 * lives in the CPU is CR0.TS and that will be "restored" by 814 * setting it on the new CPU. 815 */ 816 critical_enter(); 817 818 KASSERT((curpcb->pcb_flags & PCB_FPUNOSAVE) == 0, 819 ("fpudna while in fpu_kern_enter(FPU_KERN_NOCTX)")); 820 if (__predict_false(PCPU_GET(fpcurthread) == td)) { 821 /* 822 * Some virtual machines seems to set %cr0.TS at 823 * arbitrary moments. Silently clear the TS bit 824 * regardless of the eager/lazy FPU context switch 825 * mode. 826 */ 827 stop_emulating(); 828 } else { 829 if (__predict_false(PCPU_GET(fpcurthread) != NULL)) { 830 panic( 831 "fpudna: fpcurthread = %p (%d), curthread = %p (%d)\n", 832 PCPU_GET(fpcurthread), 833 PCPU_GET(fpcurthread)->td_tid, td, td->td_tid); 834 } 835 restore_fpu_curthread(td); 836 } 837 critical_exit(); 838 } 839 840 void fpu_activate_sw(struct thread *td); /* Called from the context switch */ 841 void 842 fpu_activate_sw(struct thread *td) 843 { 844 845 if ((td->td_pflags & TDP_KTHREAD) != 0 || !PCB_USER_FPU(td->td_pcb)) { 846 PCPU_SET(fpcurthread, NULL); 847 start_emulating(); 848 } else if (PCPU_GET(fpcurthread) != td) { 849 restore_fpu_curthread(td); 850 } 851 } 852 853 void 854 fpudrop(void) 855 { 856 struct thread *td; 857 858 td = PCPU_GET(fpcurthread); 859 KASSERT(td == curthread, ("fpudrop: fpcurthread != curthread")); 860 CRITICAL_ASSERT(td); 861 PCPU_SET(fpcurthread, NULL); 862 clear_pcb_flags(td->td_pcb, PCB_FPUINITDONE); 863 start_emulating(); 864 } 865 866 /* 867 * Get the user state of the FPU into pcb->pcb_user_save without 868 * dropping ownership (if possible). It returns the FPU ownership 869 * status. 870 */ 871 int 872 fpugetregs(struct thread *td) 873 { 874 struct pcb *pcb; 875 uint64_t *xstate_bv, bit; 876 char *sa; 877 int max_ext_n, i, owned; 878 879 pcb = td->td_pcb; 880 critical_enter(); 881 if ((pcb->pcb_flags & PCB_USERFPUINITDONE) == 0) { 882 bcopy(fpu_initialstate, get_pcb_user_save_pcb(pcb), 883 cpu_max_ext_state_size); 884 get_pcb_user_save_pcb(pcb)->sv_env.en_cw = 885 pcb->pcb_initial_fpucw; 886 fpuuserinited(td); 887 critical_exit(); 888 return (_MC_FPOWNED_PCB); 889 } 890 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) { 891 fpusave(get_pcb_user_save_pcb(pcb)); 892 owned = _MC_FPOWNED_FPU; 893 } else { 894 owned = _MC_FPOWNED_PCB; 895 } 896 if (use_xsave) { 897 /* 898 * Handle partially saved state. 899 */ 900 sa = (char *)get_pcb_user_save_pcb(pcb); 901 xstate_bv = (uint64_t *)(sa + sizeof(struct savefpu) + 902 offsetof(struct xstate_hdr, xstate_bv)); 903 max_ext_n = flsl(xsave_mask); 904 for (i = 0; i < max_ext_n; i++) { 905 bit = 1ULL << i; 906 if ((xsave_mask & bit) == 0 || (*xstate_bv & bit) != 0) 907 continue; 908 bcopy((char *)fpu_initialstate + 909 xsave_area_desc[i].offset, 910 sa + xsave_area_desc[i].offset, 911 xsave_area_desc[i].size); 912 *xstate_bv |= bit; 913 } 914 } 915 critical_exit(); 916 return (owned); 917 } 918 919 void 920 fpuuserinited(struct thread *td) 921 { 922 struct pcb *pcb; 923 924 CRITICAL_ASSERT(td); 925 pcb = td->td_pcb; 926 if (PCB_USER_FPU(pcb)) 927 set_pcb_flags(pcb, 928 PCB_FPUINITDONE | PCB_USERFPUINITDONE); 929 else 930 set_pcb_flags(pcb, PCB_FPUINITDONE); 931 } 932 933 int 934 fpusetxstate(struct thread *td, char *xfpustate, size_t xfpustate_size) 935 { 936 struct xstate_hdr *hdr, *ehdr; 937 size_t len, max_len; 938 uint64_t bv; 939 940 /* XXXKIB should we clear all extended state in xstate_bv instead ? */ 941 if (xfpustate == NULL) 942 return (0); 943 if (!use_xsave) 944 return (EOPNOTSUPP); 945 946 len = xfpustate_size; 947 if (len < sizeof(struct xstate_hdr)) 948 return (EINVAL); 949 max_len = cpu_max_ext_state_size - sizeof(struct savefpu); 950 if (len > max_len) 951 return (EINVAL); 952 953 ehdr = (struct xstate_hdr *)xfpustate; 954 bv = ehdr->xstate_bv; 955 956 /* 957 * Avoid #gp. 958 */ 959 if (bv & ~xsave_mask) 960 return (EINVAL); 961 962 hdr = (struct xstate_hdr *)(get_pcb_user_save_td(td) + 1); 963 964 hdr->xstate_bv = bv; 965 bcopy(xfpustate + sizeof(struct xstate_hdr), 966 (char *)(hdr + 1), len - sizeof(struct xstate_hdr)); 967 968 return (0); 969 } 970 971 /* 972 * Set the state of the FPU. 973 */ 974 int 975 fpusetregs(struct thread *td, struct savefpu *addr, char *xfpustate, 976 size_t xfpustate_size) 977 { 978 struct pcb *pcb; 979 int error; 980 981 addr->sv_env.en_mxcsr &= cpu_mxcsr_mask; 982 pcb = td->td_pcb; 983 error = 0; 984 critical_enter(); 985 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) { 986 error = fpusetxstate(td, xfpustate, xfpustate_size); 987 if (error == 0) { 988 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr)); 989 fpurestore(get_pcb_user_save_td(td)); 990 set_pcb_flags(pcb, PCB_FPUINITDONE | 991 PCB_USERFPUINITDONE); 992 } 993 } else { 994 error = fpusetxstate(td, xfpustate, xfpustate_size); 995 if (error == 0) { 996 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr)); 997 fpuuserinited(td); 998 } 999 } 1000 critical_exit(); 1001 return (error); 1002 } 1003 1004 /* 1005 * On AuthenticAMD processors, the fxrstor instruction does not restore 1006 * the x87's stored last instruction pointer, last data pointer, and last 1007 * opcode values, except in the rare case in which the exception summary 1008 * (ES) bit in the x87 status word is set to 1. 1009 * 1010 * In order to avoid leaking this information across processes, we clean 1011 * these values by performing a dummy load before executing fxrstor(). 1012 */ 1013 static void 1014 fpu_clean_state(void) 1015 { 1016 static float dummy_variable = 0.0; 1017 u_short status; 1018 1019 /* 1020 * Clear the ES bit in the x87 status word if it is currently 1021 * set, in order to avoid causing a fault in the upcoming load. 1022 */ 1023 fnstsw(&status); 1024 if (status & 0x80) 1025 fnclex(); 1026 1027 /* 1028 * Load the dummy variable into the x87 stack. This mangles 1029 * the x87 stack, but we don't care since we're about to call 1030 * fxrstor() anyway. 1031 */ 1032 __asm __volatile("ffree %%st(7); flds %0" : : "m" (dummy_variable)); 1033 } 1034 1035 /* 1036 * This really sucks. We want the acpi version only, but it requires 1037 * the isa_if.h file in order to get the definitions. 1038 */ 1039 #include "opt_isa.h" 1040 #ifdef DEV_ISA 1041 #include <isa/isavar.h> 1042 /* 1043 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI. 1044 */ 1045 static struct isa_pnp_id fpupnp_ids[] = { 1046 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */ 1047 { 0 } 1048 }; 1049 1050 static int 1051 fpupnp_probe(device_t dev) 1052 { 1053 int result; 1054 1055 result = ISA_PNP_PROBE(device_get_parent(dev), dev, fpupnp_ids); 1056 if (result <= 0) 1057 device_quiet(dev); 1058 return (result); 1059 } 1060 1061 static int 1062 fpupnp_attach(device_t dev) 1063 { 1064 1065 return (0); 1066 } 1067 1068 static device_method_t fpupnp_methods[] = { 1069 /* Device interface */ 1070 DEVMETHOD(device_probe, fpupnp_probe), 1071 DEVMETHOD(device_attach, fpupnp_attach), 1072 DEVMETHOD(device_detach, bus_generic_detach), 1073 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1074 DEVMETHOD(device_suspend, bus_generic_suspend), 1075 DEVMETHOD(device_resume, bus_generic_resume), 1076 { 0, 0 } 1077 }; 1078 1079 static driver_t fpupnp_driver = { 1080 "fpupnp", 1081 fpupnp_methods, 1082 1, /* no softc */ 1083 }; 1084 1085 static devclass_t fpupnp_devclass; 1086 1087 DRIVER_MODULE(fpupnp, acpi, fpupnp_driver, fpupnp_devclass, 0, 0); 1088 ISA_PNP_INFO(fpupnp_ids); 1089 #endif /* DEV_ISA */ 1090 1091 static MALLOC_DEFINE(M_FPUKERN_CTX, "fpukern_ctx", 1092 "Kernel contexts for FPU state"); 1093 1094 #define FPU_KERN_CTX_FPUINITDONE 0x01 1095 #define FPU_KERN_CTX_DUMMY 0x02 /* avoided save for the kern thread */ 1096 #define FPU_KERN_CTX_INUSE 0x04 1097 1098 struct fpu_kern_ctx { 1099 struct savefpu *prev; 1100 uint32_t flags; 1101 char hwstate1[]; 1102 }; 1103 1104 static inline size_t __pure2 1105 fpu_kern_alloc_sz(u_int max_est) 1106 { 1107 return (sizeof(struct fpu_kern_ctx) + XSAVE_AREA_ALIGN + max_est); 1108 } 1109 1110 static inline int __pure2 1111 fpu_kern_malloc_flags(u_int fpflags) 1112 { 1113 return (((fpflags & FPU_KERN_NOWAIT) ? M_NOWAIT : M_WAITOK) | M_ZERO); 1114 } 1115 1116 struct fpu_kern_ctx * 1117 fpu_kern_alloc_ctx_domain(int domain, u_int flags) 1118 { 1119 return (malloc_domainset(fpu_kern_alloc_sz(cpu_max_ext_state_size), 1120 M_FPUKERN_CTX, DOMAINSET_PREF(domain), 1121 fpu_kern_malloc_flags(flags))); 1122 } 1123 1124 struct fpu_kern_ctx * 1125 fpu_kern_alloc_ctx(u_int flags) 1126 { 1127 return (malloc(fpu_kern_alloc_sz(cpu_max_ext_state_size), 1128 M_FPUKERN_CTX, fpu_kern_malloc_flags(flags))); 1129 } 1130 1131 void 1132 fpu_kern_free_ctx(struct fpu_kern_ctx *ctx) 1133 { 1134 1135 KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) == 0, ("free'ing inuse ctx")); 1136 /* XXXKIB clear the memory ? */ 1137 free(ctx, M_FPUKERN_CTX); 1138 } 1139 1140 static struct savefpu * 1141 fpu_kern_ctx_savefpu(struct fpu_kern_ctx *ctx) 1142 { 1143 vm_offset_t p; 1144 1145 p = (vm_offset_t)&ctx->hwstate1; 1146 p = roundup2(p, XSAVE_AREA_ALIGN); 1147 return ((struct savefpu *)p); 1148 } 1149 1150 void 1151 fpu_kern_enter(struct thread *td, struct fpu_kern_ctx *ctx, u_int flags) 1152 { 1153 struct pcb *pcb; 1154 1155 pcb = td->td_pcb; 1156 KASSERT((flags & FPU_KERN_NOCTX) != 0 || ctx != NULL, 1157 ("ctx is required when !FPU_KERN_NOCTX")); 1158 KASSERT(ctx == NULL || (ctx->flags & FPU_KERN_CTX_INUSE) == 0, 1159 ("using inuse ctx")); 1160 KASSERT((pcb->pcb_flags & PCB_FPUNOSAVE) == 0, 1161 ("recursive fpu_kern_enter while in PCB_FPUNOSAVE state")); 1162 1163 if ((flags & FPU_KERN_NOCTX) != 0) { 1164 critical_enter(); 1165 stop_emulating(); 1166 if (curthread == PCPU_GET(fpcurthread)) { 1167 fpusave(curpcb->pcb_save); 1168 PCPU_SET(fpcurthread, NULL); 1169 } else { 1170 KASSERT(PCPU_GET(fpcurthread) == NULL, 1171 ("invalid fpcurthread")); 1172 } 1173 1174 /* 1175 * This breaks XSAVEOPT tracker, but 1176 * PCB_FPUNOSAVE state is supposed to never need to 1177 * save FPU context at all. 1178 */ 1179 fpurestore(fpu_initialstate); 1180 set_pcb_flags(pcb, PCB_KERNFPU | PCB_FPUNOSAVE | 1181 PCB_FPUINITDONE); 1182 return; 1183 } 1184 if ((flags & FPU_KERN_KTHR) != 0 && is_fpu_kern_thread(0)) { 1185 ctx->flags = FPU_KERN_CTX_DUMMY | FPU_KERN_CTX_INUSE; 1186 return; 1187 } 1188 critical_enter(); 1189 KASSERT(!PCB_USER_FPU(pcb) || pcb->pcb_save == 1190 get_pcb_user_save_pcb(pcb), ("mangled pcb_save")); 1191 ctx->flags = FPU_KERN_CTX_INUSE; 1192 if ((pcb->pcb_flags & PCB_FPUINITDONE) != 0) 1193 ctx->flags |= FPU_KERN_CTX_FPUINITDONE; 1194 fpuexit(td); 1195 ctx->prev = pcb->pcb_save; 1196 pcb->pcb_save = fpu_kern_ctx_savefpu(ctx); 1197 set_pcb_flags(pcb, PCB_KERNFPU); 1198 clear_pcb_flags(pcb, PCB_FPUINITDONE); 1199 critical_exit(); 1200 } 1201 1202 int 1203 fpu_kern_leave(struct thread *td, struct fpu_kern_ctx *ctx) 1204 { 1205 struct pcb *pcb; 1206 1207 pcb = td->td_pcb; 1208 1209 if ((pcb->pcb_flags & PCB_FPUNOSAVE) != 0) { 1210 KASSERT(ctx == NULL, ("non-null ctx after FPU_KERN_NOCTX")); 1211 KASSERT(PCPU_GET(fpcurthread) == NULL, 1212 ("non-NULL fpcurthread for PCB_FPUNOSAVE")); 1213 CRITICAL_ASSERT(td); 1214 1215 clear_pcb_flags(pcb, PCB_FPUNOSAVE | PCB_FPUINITDONE); 1216 start_emulating(); 1217 } else { 1218 KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) != 0, 1219 ("leaving not inuse ctx")); 1220 ctx->flags &= ~FPU_KERN_CTX_INUSE; 1221 1222 if (is_fpu_kern_thread(0) && 1223 (ctx->flags & FPU_KERN_CTX_DUMMY) != 0) 1224 return (0); 1225 KASSERT((ctx->flags & FPU_KERN_CTX_DUMMY) == 0, 1226 ("dummy ctx")); 1227 critical_enter(); 1228 if (curthread == PCPU_GET(fpcurthread)) 1229 fpudrop(); 1230 pcb->pcb_save = ctx->prev; 1231 } 1232 1233 if (pcb->pcb_save == get_pcb_user_save_pcb(pcb)) { 1234 if ((pcb->pcb_flags & PCB_USERFPUINITDONE) != 0) { 1235 set_pcb_flags(pcb, PCB_FPUINITDONE); 1236 if ((pcb->pcb_flags & PCB_KERNFPU_THR) == 0) 1237 clear_pcb_flags(pcb, PCB_KERNFPU); 1238 } else if ((pcb->pcb_flags & PCB_KERNFPU_THR) == 0) 1239 clear_pcb_flags(pcb, PCB_FPUINITDONE | PCB_KERNFPU); 1240 } else { 1241 if ((ctx->flags & FPU_KERN_CTX_FPUINITDONE) != 0) 1242 set_pcb_flags(pcb, PCB_FPUINITDONE); 1243 else 1244 clear_pcb_flags(pcb, PCB_FPUINITDONE); 1245 KASSERT(!PCB_USER_FPU(pcb), ("unpaired fpu_kern_leave")); 1246 } 1247 critical_exit(); 1248 return (0); 1249 } 1250 1251 int 1252 fpu_kern_thread(u_int flags) 1253 { 1254 1255 KASSERT((curthread->td_pflags & TDP_KTHREAD) != 0, 1256 ("Only kthread may use fpu_kern_thread")); 1257 KASSERT(curpcb->pcb_save == get_pcb_user_save_pcb(curpcb), 1258 ("mangled pcb_save")); 1259 KASSERT(PCB_USER_FPU(curpcb), ("recursive call")); 1260 1261 set_pcb_flags(curpcb, PCB_KERNFPU | PCB_KERNFPU_THR); 1262 return (0); 1263 } 1264 1265 int 1266 is_fpu_kern_thread(u_int flags) 1267 { 1268 1269 if ((curthread->td_pflags & TDP_KTHREAD) == 0) 1270 return (0); 1271 return ((curpcb->pcb_flags & PCB_KERNFPU_THR) != 0); 1272 } 1273 1274 /* 1275 * FPU save area alloc/free/init utility routines 1276 */ 1277 struct savefpu * 1278 fpu_save_area_alloc(void) 1279 { 1280 1281 return (uma_zalloc(fpu_save_area_zone, M_WAITOK)); 1282 } 1283 1284 void 1285 fpu_save_area_free(struct savefpu *fsa) 1286 { 1287 1288 uma_zfree(fpu_save_area_zone, fsa); 1289 } 1290 1291 void 1292 fpu_save_area_reset(struct savefpu *fsa) 1293 { 1294 1295 bcopy(fpu_initialstate, fsa, cpu_max_ext_state_size); 1296 } 1297