1 /*- 2 * Copyright (c) 1990 William Jolitz. 3 * Copyright (c) 1991 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 4. Neither the name of the University nor the names of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/bus.h> 39 #include <sys/kernel.h> 40 #include <sys/lock.h> 41 #include <sys/malloc.h> 42 #include <sys/module.h> 43 #include <sys/mutex.h> 44 #include <sys/mutex.h> 45 #include <sys/proc.h> 46 #include <sys/sysctl.h> 47 #include <machine/bus.h> 48 #include <sys/rman.h> 49 #include <sys/signalvar.h> 50 #include <vm/uma.h> 51 52 #include <machine/cputypes.h> 53 #include <machine/frame.h> 54 #include <machine/intr_machdep.h> 55 #include <machine/md_var.h> 56 #include <machine/pcb.h> 57 #include <machine/psl.h> 58 #include <machine/resource.h> 59 #include <machine/specialreg.h> 60 #include <machine/segments.h> 61 #include <machine/ucontext.h> 62 63 /* 64 * Floating point support. 65 */ 66 67 #if defined(__GNUCLIKE_ASM) && !defined(lint) 68 69 #define fldcw(cw) __asm __volatile("fldcw %0" : : "m" (cw)) 70 #define fnclex() __asm __volatile("fnclex") 71 #define fninit() __asm __volatile("fninit") 72 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 73 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=am" (*(addr))) 74 #define fxrstor(addr) __asm __volatile("fxrstor %0" : : "m" (*(addr))) 75 #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 76 #define ldmxcsr(csr) __asm __volatile("ldmxcsr %0" : : "m" (csr)) 77 #define stmxcsr(addr) __asm __volatile("stmxcsr %0" : : "m" (*(addr))) 78 79 static __inline void 80 xrstor(char *addr, uint64_t mask) 81 { 82 uint32_t low, hi; 83 84 low = mask; 85 hi = mask >> 32; 86 __asm __volatile("xrstor %0" : : "m" (*addr), "a" (low), "d" (hi)); 87 } 88 89 static __inline void 90 xsave(char *addr, uint64_t mask) 91 { 92 uint32_t low, hi; 93 94 low = mask; 95 hi = mask >> 32; 96 __asm __volatile("xsave %0" : "=m" (*addr) : "a" (low), "d" (hi) : 97 "memory"); 98 } 99 100 #else /* !(__GNUCLIKE_ASM && !lint) */ 101 102 void fldcw(u_short cw); 103 void fnclex(void); 104 void fninit(void); 105 void fnstcw(caddr_t addr); 106 void fnstsw(caddr_t addr); 107 void fxsave(caddr_t addr); 108 void fxrstor(caddr_t addr); 109 void ldmxcsr(u_int csr); 110 void stmxcsr(u_int *csr); 111 void xrstor(char *addr, uint64_t mask); 112 void xsave(char *addr, uint64_t mask); 113 114 #endif /* __GNUCLIKE_ASM && !lint */ 115 116 #define start_emulating() load_cr0(rcr0() | CR0_TS) 117 #define stop_emulating() clts() 118 119 CTASSERT(sizeof(struct savefpu) == 512); 120 CTASSERT(sizeof(struct xstate_hdr) == 64); 121 CTASSERT(sizeof(struct savefpu_ymm) == 832); 122 123 /* 124 * This requirement is to make it easier for asm code to calculate 125 * offset of the fpu save area from the pcb address. FPU save area 126 * must be 64-byte aligned. 127 */ 128 CTASSERT(sizeof(struct pcb) % XSAVE_AREA_ALIGN == 0); 129 130 static void fpu_clean_state(void); 131 132 SYSCTL_INT(_hw, HW_FLOATINGPT, floatingpoint, CTLFLAG_RD, 133 SYSCTL_NULL_INT_PTR, 1, "Floating point instructions executed in hardware"); 134 135 int use_xsave; /* non-static for cpu_switch.S */ 136 uint64_t xsave_mask; /* the same */ 137 static uma_zone_t fpu_save_area_zone; 138 static struct savefpu *fpu_initialstate; 139 140 struct xsave_area_elm_descr { 141 u_int offset; 142 u_int size; 143 } *xsave_area_desc; 144 145 void 146 fpusave(void *addr) 147 { 148 149 if (use_xsave) 150 xsave((char *)addr, xsave_mask); 151 else 152 fxsave((char *)addr); 153 } 154 155 void 156 fpurestore(void *addr) 157 { 158 159 if (use_xsave) 160 xrstor((char *)addr, xsave_mask); 161 else 162 fxrstor((char *)addr); 163 } 164 165 void 166 fpususpend(void *addr) 167 { 168 u_long cr0; 169 170 cr0 = rcr0(); 171 stop_emulating(); 172 fpusave(addr); 173 load_cr0(cr0); 174 } 175 176 void 177 fpuresume(void *addr) 178 { 179 u_long cr0; 180 181 cr0 = rcr0(); 182 stop_emulating(); 183 fninit(); 184 if (use_xsave) 185 load_xcr(XCR0, xsave_mask); 186 fpurestore(addr); 187 load_cr0(cr0); 188 } 189 190 /* 191 * Enable XSAVE if supported and allowed by user. 192 * Calculate the xsave_mask. 193 */ 194 static void 195 fpuinit_bsp1(void) 196 { 197 u_int cp[4]; 198 uint64_t xsave_mask_user; 199 200 if ((cpu_feature2 & CPUID2_XSAVE) != 0) { 201 use_xsave = 1; 202 TUNABLE_INT_FETCH("hw.use_xsave", &use_xsave); 203 } 204 if (!use_xsave) 205 return; 206 207 cpuid_count(0xd, 0x0, cp); 208 xsave_mask = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE; 209 if ((cp[0] & xsave_mask) != xsave_mask) 210 panic("CPU0 does not support X87 or SSE: %x", cp[0]); 211 xsave_mask = ((uint64_t)cp[3] << 32) | cp[0]; 212 xsave_mask_user = xsave_mask; 213 TUNABLE_ULONG_FETCH("hw.xsave_mask", &xsave_mask_user); 214 xsave_mask_user |= XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE; 215 xsave_mask &= xsave_mask_user; 216 if ((xsave_mask & XFEATURE_AVX512) != XFEATURE_AVX512) 217 xsave_mask &= ~XFEATURE_AVX512; 218 if ((xsave_mask & XFEATURE_MPX) != XFEATURE_MPX) 219 xsave_mask &= ~XFEATURE_MPX; 220 221 cpuid_count(0xd, 0x1, cp); 222 if ((cp[0] & CPUID_EXTSTATE_XSAVEOPT) != 0) { 223 /* 224 * Patch the XSAVE instruction in the cpu_switch code 225 * to XSAVEOPT. We assume that XSAVE encoding used 226 * REX byte, and set the bit 4 of the r/m byte. 227 */ 228 ctx_switch_xsave[3] |= 0x10; 229 } 230 } 231 232 /* 233 * Calculate the fpu save area size. 234 */ 235 static void 236 fpuinit_bsp2(void) 237 { 238 u_int cp[4]; 239 240 if (use_xsave) { 241 cpuid_count(0xd, 0x0, cp); 242 cpu_max_ext_state_size = cp[1]; 243 244 /* 245 * Reload the cpu_feature2, since we enabled OSXSAVE. 246 */ 247 do_cpuid(1, cp); 248 cpu_feature2 = cp[2]; 249 } else 250 cpu_max_ext_state_size = sizeof(struct savefpu); 251 } 252 253 /* 254 * Initialize the floating point unit. 255 */ 256 void 257 fpuinit(void) 258 { 259 register_t saveintr; 260 u_int mxcsr; 261 u_short control; 262 263 if (IS_BSP()) 264 fpuinit_bsp1(); 265 266 if (use_xsave) { 267 load_cr4(rcr4() | CR4_XSAVE); 268 load_xcr(XCR0, xsave_mask); 269 } 270 271 /* 272 * XCR0 shall be set up before CPU can report the save area size. 273 */ 274 if (IS_BSP()) 275 fpuinit_bsp2(); 276 277 /* 278 * It is too early for critical_enter() to work on AP. 279 */ 280 saveintr = intr_disable(); 281 stop_emulating(); 282 fninit(); 283 control = __INITIAL_FPUCW__; 284 fldcw(control); 285 mxcsr = __INITIAL_MXCSR__; 286 ldmxcsr(mxcsr); 287 start_emulating(); 288 intr_restore(saveintr); 289 } 290 291 /* 292 * On the boot CPU we generate a clean state that is used to 293 * initialize the floating point unit when it is first used by a 294 * process. 295 */ 296 static void 297 fpuinitstate(void *arg __unused) 298 { 299 register_t saveintr; 300 int cp[4], i, max_ext_n; 301 302 fpu_initialstate = malloc(cpu_max_ext_state_size, M_DEVBUF, 303 M_WAITOK | M_ZERO); 304 saveintr = intr_disable(); 305 stop_emulating(); 306 307 fpusave(fpu_initialstate); 308 if (fpu_initialstate->sv_env.en_mxcsr_mask) 309 cpu_mxcsr_mask = fpu_initialstate->sv_env.en_mxcsr_mask; 310 else 311 cpu_mxcsr_mask = 0xFFBF; 312 313 /* 314 * The fninit instruction does not modify XMM registers. The 315 * fpusave call dumped the garbage contained in the registers 316 * after reset to the initial state saved. Clear XMM 317 * registers file image to make the startup program state and 318 * signal handler XMM register content predictable. 319 */ 320 bzero(&fpu_initialstate->sv_xmm[0], sizeof(struct xmmacc)); 321 322 /* 323 * Create a table describing the layout of the CPU Extended 324 * Save Area. 325 */ 326 if (use_xsave) { 327 max_ext_n = flsl(xsave_mask); 328 xsave_area_desc = malloc(max_ext_n * sizeof(struct 329 xsave_area_elm_descr), M_DEVBUF, M_WAITOK | M_ZERO); 330 /* x87 state */ 331 xsave_area_desc[0].offset = 0; 332 xsave_area_desc[0].size = 160; 333 /* XMM */ 334 xsave_area_desc[1].offset = 160; 335 xsave_area_desc[1].size = 288 - 160; 336 337 for (i = 2; i < max_ext_n; i++) { 338 cpuid_count(0xd, i, cp); 339 xsave_area_desc[i].offset = cp[1]; 340 xsave_area_desc[i].size = cp[0]; 341 } 342 } 343 344 fpu_save_area_zone = uma_zcreate("FPU_save_area", 345 cpu_max_ext_state_size, NULL, NULL, NULL, NULL, 346 XSAVE_AREA_ALIGN - 1, 0); 347 348 start_emulating(); 349 intr_restore(saveintr); 350 } 351 SYSINIT(fpuinitstate, SI_SUB_DRIVERS, SI_ORDER_ANY, fpuinitstate, NULL); 352 353 /* 354 * Free coprocessor (if we have it). 355 */ 356 void 357 fpuexit(struct thread *td) 358 { 359 360 critical_enter(); 361 if (curthread == PCPU_GET(fpcurthread)) { 362 stop_emulating(); 363 fpusave(curpcb->pcb_save); 364 start_emulating(); 365 PCPU_SET(fpcurthread, NULL); 366 } 367 critical_exit(); 368 } 369 370 int 371 fpuformat() 372 { 373 374 return (_MC_FPFMT_XMM); 375 } 376 377 /* 378 * The following mechanism is used to ensure that the FPE_... value 379 * that is passed as a trapcode to the signal handler of the user 380 * process does not have more than one bit set. 381 * 382 * Multiple bits may be set if the user process modifies the control 383 * word while a status word bit is already set. While this is a sign 384 * of bad coding, we have no choise than to narrow them down to one 385 * bit, since we must not send a trapcode that is not exactly one of 386 * the FPE_ macros. 387 * 388 * The mechanism has a static table with 127 entries. Each combination 389 * of the 7 FPU status word exception bits directly translates to a 390 * position in this table, where a single FPE_... value is stored. 391 * This FPE_... value stored there is considered the "most important" 392 * of the exception bits and will be sent as the signal code. The 393 * precedence of the bits is based upon Intel Document "Numerical 394 * Applications", Chapter "Special Computational Situations". 395 * 396 * The macro to choose one of these values does these steps: 1) Throw 397 * away status word bits that cannot be masked. 2) Throw away the bits 398 * currently masked in the control word, assuming the user isn't 399 * interested in them anymore. 3) Reinsert status word bit 7 (stack 400 * fault) if it is set, which cannot be masked but must be presered. 401 * 4) Use the remaining bits to point into the trapcode table. 402 * 403 * The 6 maskable bits in order of their preference, as stated in the 404 * above referenced Intel manual: 405 * 1 Invalid operation (FP_X_INV) 406 * 1a Stack underflow 407 * 1b Stack overflow 408 * 1c Operand of unsupported format 409 * 1d SNaN operand. 410 * 2 QNaN operand (not an exception, irrelavant here) 411 * 3 Any other invalid-operation not mentioned above or zero divide 412 * (FP_X_INV, FP_X_DZ) 413 * 4 Denormal operand (FP_X_DNML) 414 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 415 * 6 Inexact result (FP_X_IMP) 416 */ 417 static char fpetable[128] = { 418 0, 419 FPE_FLTINV, /* 1 - INV */ 420 FPE_FLTUND, /* 2 - DNML */ 421 FPE_FLTINV, /* 3 - INV | DNML */ 422 FPE_FLTDIV, /* 4 - DZ */ 423 FPE_FLTINV, /* 5 - INV | DZ */ 424 FPE_FLTDIV, /* 6 - DNML | DZ */ 425 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 426 FPE_FLTOVF, /* 8 - OFL */ 427 FPE_FLTINV, /* 9 - INV | OFL */ 428 FPE_FLTUND, /* A - DNML | OFL */ 429 FPE_FLTINV, /* B - INV | DNML | OFL */ 430 FPE_FLTDIV, /* C - DZ | OFL */ 431 FPE_FLTINV, /* D - INV | DZ | OFL */ 432 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 433 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 434 FPE_FLTUND, /* 10 - UFL */ 435 FPE_FLTINV, /* 11 - INV | UFL */ 436 FPE_FLTUND, /* 12 - DNML | UFL */ 437 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 438 FPE_FLTDIV, /* 14 - DZ | UFL */ 439 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 440 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 441 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 442 FPE_FLTOVF, /* 18 - OFL | UFL */ 443 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 444 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 445 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 446 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 447 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 448 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 449 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 450 FPE_FLTRES, /* 20 - IMP */ 451 FPE_FLTINV, /* 21 - INV | IMP */ 452 FPE_FLTUND, /* 22 - DNML | IMP */ 453 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 454 FPE_FLTDIV, /* 24 - DZ | IMP */ 455 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 456 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 457 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 458 FPE_FLTOVF, /* 28 - OFL | IMP */ 459 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 460 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 461 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 462 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 463 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 464 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 465 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 466 FPE_FLTUND, /* 30 - UFL | IMP */ 467 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 468 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 469 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 470 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 471 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 472 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 473 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 474 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 475 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 476 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 477 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 478 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 479 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 480 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 481 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 482 FPE_FLTSUB, /* 40 - STK */ 483 FPE_FLTSUB, /* 41 - INV | STK */ 484 FPE_FLTUND, /* 42 - DNML | STK */ 485 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 486 FPE_FLTDIV, /* 44 - DZ | STK */ 487 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 488 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 489 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 490 FPE_FLTOVF, /* 48 - OFL | STK */ 491 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 492 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 493 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 494 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 495 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 496 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 497 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 498 FPE_FLTUND, /* 50 - UFL | STK */ 499 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 500 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 501 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 502 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 503 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 504 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 505 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 506 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 507 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 508 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 509 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 510 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 511 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 512 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 513 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 514 FPE_FLTRES, /* 60 - IMP | STK */ 515 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 516 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 517 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 518 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 519 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 520 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 521 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 522 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 523 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 524 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 525 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 526 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 527 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 528 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 529 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 530 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 531 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 532 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 533 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 534 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 535 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 536 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 537 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 538 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 539 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 540 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 541 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 542 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 543 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 544 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 545 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 546 }; 547 548 /* 549 * Read the FP status and control words, then generate si_code value 550 * for SIGFPE. The error code chosen will be one of the 551 * FPE_... macros. It will be sent as the second argument to old 552 * BSD-style signal handlers and as "siginfo_t->si_code" (second 553 * argument) to SA_SIGINFO signal handlers. 554 * 555 * Some time ago, we cleared the x87 exceptions with FNCLEX there. 556 * Clearing exceptions was necessary mainly to avoid IRQ13 bugs. The 557 * usermode code which understands the FPU hardware enough to enable 558 * the exceptions, can also handle clearing the exception state in the 559 * handler. The only consequence of not clearing the exception is the 560 * rethrow of the SIGFPE on return from the signal handler and 561 * reexecution of the corresponding instruction. 562 * 563 * For XMM traps, the exceptions were never cleared. 564 */ 565 int 566 fputrap_x87(void) 567 { 568 struct savefpu *pcb_save; 569 u_short control, status; 570 571 critical_enter(); 572 573 /* 574 * Interrupt handling (for another interrupt) may have pushed the 575 * state to memory. Fetch the relevant parts of the state from 576 * wherever they are. 577 */ 578 if (PCPU_GET(fpcurthread) != curthread) { 579 pcb_save = curpcb->pcb_save; 580 control = pcb_save->sv_env.en_cw; 581 status = pcb_save->sv_env.en_sw; 582 } else { 583 fnstcw(&control); 584 fnstsw(&status); 585 } 586 587 critical_exit(); 588 return (fpetable[status & ((~control & 0x3f) | 0x40)]); 589 } 590 591 int 592 fputrap_sse(void) 593 { 594 u_int mxcsr; 595 596 critical_enter(); 597 if (PCPU_GET(fpcurthread) != curthread) 598 mxcsr = curpcb->pcb_save->sv_env.en_mxcsr; 599 else 600 stmxcsr(&mxcsr); 601 critical_exit(); 602 return (fpetable[(mxcsr & (~mxcsr >> 7)) & 0x3f]); 603 } 604 605 /* 606 * Device Not Available (DNA, #NM) exception handler. 607 * 608 * It would be better to switch FP context here (if curthread != 609 * fpcurthread) and not necessarily for every context switch, but it 610 * is too hard to access foreign pcb's. 611 */ 612 void 613 fpudna(void) 614 { 615 616 /* 617 * This handler is entered with interrupts enabled, so context 618 * switches may occur before critical_enter() is executed. If 619 * a context switch occurs, then when we regain control, our 620 * state will have been completely restored. The CPU may 621 * change underneath us, but the only part of our context that 622 * lives in the CPU is CR0.TS and that will be "restored" by 623 * setting it on the new CPU. 624 */ 625 critical_enter(); 626 627 if (PCPU_GET(fpcurthread) == curthread) { 628 printf("fpudna: fpcurthread == curthread\n"); 629 stop_emulating(); 630 critical_exit(); 631 return; 632 } 633 if (PCPU_GET(fpcurthread) != NULL) { 634 panic("fpudna: fpcurthread = %p (%d), curthread = %p (%d)\n", 635 PCPU_GET(fpcurthread), PCPU_GET(fpcurthread)->td_tid, 636 curthread, curthread->td_tid); 637 } 638 stop_emulating(); 639 /* 640 * Record new context early in case frstor causes a trap. 641 */ 642 PCPU_SET(fpcurthread, curthread); 643 644 fpu_clean_state(); 645 646 if ((curpcb->pcb_flags & PCB_FPUINITDONE) == 0) { 647 /* 648 * This is the first time this thread has used the FPU or 649 * the PCB doesn't contain a clean FPU state. Explicitly 650 * load an initial state. 651 * 652 * We prefer to restore the state from the actual save 653 * area in PCB instead of directly loading from 654 * fpu_initialstate, to ignite the XSAVEOPT 655 * tracking engine. 656 */ 657 bcopy(fpu_initialstate, curpcb->pcb_save, cpu_max_ext_state_size); 658 fpurestore(curpcb->pcb_save); 659 if (curpcb->pcb_initial_fpucw != __INITIAL_FPUCW__) 660 fldcw(curpcb->pcb_initial_fpucw); 661 if (PCB_USER_FPU(curpcb)) 662 set_pcb_flags(curpcb, 663 PCB_FPUINITDONE | PCB_USERFPUINITDONE); 664 else 665 set_pcb_flags(curpcb, PCB_FPUINITDONE); 666 } else 667 fpurestore(curpcb->pcb_save); 668 critical_exit(); 669 } 670 671 void 672 fpudrop() 673 { 674 struct thread *td; 675 676 td = PCPU_GET(fpcurthread); 677 KASSERT(td == curthread, ("fpudrop: fpcurthread != curthread")); 678 CRITICAL_ASSERT(td); 679 PCPU_SET(fpcurthread, NULL); 680 clear_pcb_flags(td->td_pcb, PCB_FPUINITDONE); 681 start_emulating(); 682 } 683 684 /* 685 * Get the user state of the FPU into pcb->pcb_user_save without 686 * dropping ownership (if possible). It returns the FPU ownership 687 * status. 688 */ 689 int 690 fpugetregs(struct thread *td) 691 { 692 struct pcb *pcb; 693 uint64_t *xstate_bv, bit; 694 char *sa; 695 int max_ext_n, i, owned; 696 697 pcb = td->td_pcb; 698 if ((pcb->pcb_flags & PCB_USERFPUINITDONE) == 0) { 699 bcopy(fpu_initialstate, get_pcb_user_save_pcb(pcb), 700 cpu_max_ext_state_size); 701 get_pcb_user_save_pcb(pcb)->sv_env.en_cw = 702 pcb->pcb_initial_fpucw; 703 fpuuserinited(td); 704 return (_MC_FPOWNED_PCB); 705 } 706 critical_enter(); 707 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) { 708 fpusave(get_pcb_user_save_pcb(pcb)); 709 owned = _MC_FPOWNED_FPU; 710 } else { 711 owned = _MC_FPOWNED_PCB; 712 } 713 critical_exit(); 714 if (use_xsave) { 715 /* 716 * Handle partially saved state. 717 */ 718 sa = (char *)get_pcb_user_save_pcb(pcb); 719 xstate_bv = (uint64_t *)(sa + sizeof(struct savefpu) + 720 offsetof(struct xstate_hdr, xstate_bv)); 721 max_ext_n = flsl(xsave_mask); 722 for (i = 0; i < max_ext_n; i++) { 723 bit = 1ULL << i; 724 if ((xsave_mask & bit) == 0 || (*xstate_bv & bit) != 0) 725 continue; 726 bcopy((char *)fpu_initialstate + 727 xsave_area_desc[i].offset, 728 sa + xsave_area_desc[i].offset, 729 xsave_area_desc[i].size); 730 *xstate_bv |= bit; 731 } 732 } 733 return (owned); 734 } 735 736 void 737 fpuuserinited(struct thread *td) 738 { 739 struct pcb *pcb; 740 741 pcb = td->td_pcb; 742 if (PCB_USER_FPU(pcb)) 743 set_pcb_flags(pcb, 744 PCB_FPUINITDONE | PCB_USERFPUINITDONE); 745 else 746 set_pcb_flags(pcb, PCB_FPUINITDONE); 747 } 748 749 int 750 fpusetxstate(struct thread *td, char *xfpustate, size_t xfpustate_size) 751 { 752 struct xstate_hdr *hdr, *ehdr; 753 size_t len, max_len; 754 uint64_t bv; 755 756 /* XXXKIB should we clear all extended state in xstate_bv instead ? */ 757 if (xfpustate == NULL) 758 return (0); 759 if (!use_xsave) 760 return (EOPNOTSUPP); 761 762 len = xfpustate_size; 763 if (len < sizeof(struct xstate_hdr)) 764 return (EINVAL); 765 max_len = cpu_max_ext_state_size - sizeof(struct savefpu); 766 if (len > max_len) 767 return (EINVAL); 768 769 ehdr = (struct xstate_hdr *)xfpustate; 770 bv = ehdr->xstate_bv; 771 772 /* 773 * Avoid #gp. 774 */ 775 if (bv & ~xsave_mask) 776 return (EINVAL); 777 778 hdr = (struct xstate_hdr *)(get_pcb_user_save_td(td) + 1); 779 780 hdr->xstate_bv = bv; 781 bcopy(xfpustate + sizeof(struct xstate_hdr), 782 (char *)(hdr + 1), len - sizeof(struct xstate_hdr)); 783 784 return (0); 785 } 786 787 /* 788 * Set the state of the FPU. 789 */ 790 int 791 fpusetregs(struct thread *td, struct savefpu *addr, char *xfpustate, 792 size_t xfpustate_size) 793 { 794 struct pcb *pcb; 795 int error; 796 797 pcb = td->td_pcb; 798 critical_enter(); 799 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) { 800 error = fpusetxstate(td, xfpustate, xfpustate_size); 801 if (error != 0) { 802 critical_exit(); 803 return (error); 804 } 805 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr)); 806 fpurestore(get_pcb_user_save_td(td)); 807 critical_exit(); 808 set_pcb_flags(pcb, PCB_FPUINITDONE | PCB_USERFPUINITDONE); 809 } else { 810 critical_exit(); 811 error = fpusetxstate(td, xfpustate, xfpustate_size); 812 if (error != 0) 813 return (error); 814 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr)); 815 fpuuserinited(td); 816 } 817 return (0); 818 } 819 820 /* 821 * On AuthenticAMD processors, the fxrstor instruction does not restore 822 * the x87's stored last instruction pointer, last data pointer, and last 823 * opcode values, except in the rare case in which the exception summary 824 * (ES) bit in the x87 status word is set to 1. 825 * 826 * In order to avoid leaking this information across processes, we clean 827 * these values by performing a dummy load before executing fxrstor(). 828 */ 829 static void 830 fpu_clean_state(void) 831 { 832 static float dummy_variable = 0.0; 833 u_short status; 834 835 /* 836 * Clear the ES bit in the x87 status word if it is currently 837 * set, in order to avoid causing a fault in the upcoming load. 838 */ 839 fnstsw(&status); 840 if (status & 0x80) 841 fnclex(); 842 843 /* 844 * Load the dummy variable into the x87 stack. This mangles 845 * the x87 stack, but we don't care since we're about to call 846 * fxrstor() anyway. 847 */ 848 __asm __volatile("ffree %%st(7); flds %0" : : "m" (dummy_variable)); 849 } 850 851 /* 852 * This really sucks. We want the acpi version only, but it requires 853 * the isa_if.h file in order to get the definitions. 854 */ 855 #include "opt_isa.h" 856 #ifdef DEV_ISA 857 #include <isa/isavar.h> 858 /* 859 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI. 860 */ 861 static struct isa_pnp_id fpupnp_ids[] = { 862 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */ 863 { 0 } 864 }; 865 866 static int 867 fpupnp_probe(device_t dev) 868 { 869 int result; 870 871 result = ISA_PNP_PROBE(device_get_parent(dev), dev, fpupnp_ids); 872 if (result <= 0) 873 device_quiet(dev); 874 return (result); 875 } 876 877 static int 878 fpupnp_attach(device_t dev) 879 { 880 881 return (0); 882 } 883 884 static device_method_t fpupnp_methods[] = { 885 /* Device interface */ 886 DEVMETHOD(device_probe, fpupnp_probe), 887 DEVMETHOD(device_attach, fpupnp_attach), 888 DEVMETHOD(device_detach, bus_generic_detach), 889 DEVMETHOD(device_shutdown, bus_generic_shutdown), 890 DEVMETHOD(device_suspend, bus_generic_suspend), 891 DEVMETHOD(device_resume, bus_generic_resume), 892 893 { 0, 0 } 894 }; 895 896 static driver_t fpupnp_driver = { 897 "fpupnp", 898 fpupnp_methods, 899 1, /* no softc */ 900 }; 901 902 static devclass_t fpupnp_devclass; 903 904 DRIVER_MODULE(fpupnp, acpi, fpupnp_driver, fpupnp_devclass, 0, 0); 905 #endif /* DEV_ISA */ 906 907 static MALLOC_DEFINE(M_FPUKERN_CTX, "fpukern_ctx", 908 "Kernel contexts for FPU state"); 909 910 #define FPU_KERN_CTX_FPUINITDONE 0x01 911 #define FPU_KERN_CTX_DUMMY 0x02 /* avoided save for the kern thread */ 912 913 struct fpu_kern_ctx { 914 struct savefpu *prev; 915 uint32_t flags; 916 char hwstate1[]; 917 }; 918 919 struct fpu_kern_ctx * 920 fpu_kern_alloc_ctx(u_int flags) 921 { 922 struct fpu_kern_ctx *res; 923 size_t sz; 924 925 sz = sizeof(struct fpu_kern_ctx) + XSAVE_AREA_ALIGN + 926 cpu_max_ext_state_size; 927 res = malloc(sz, M_FPUKERN_CTX, ((flags & FPU_KERN_NOWAIT) ? 928 M_NOWAIT : M_WAITOK) | M_ZERO); 929 return (res); 930 } 931 932 void 933 fpu_kern_free_ctx(struct fpu_kern_ctx *ctx) 934 { 935 936 /* XXXKIB clear the memory ? */ 937 free(ctx, M_FPUKERN_CTX); 938 } 939 940 static struct savefpu * 941 fpu_kern_ctx_savefpu(struct fpu_kern_ctx *ctx) 942 { 943 vm_offset_t p; 944 945 p = (vm_offset_t)&ctx->hwstate1; 946 p = roundup2(p, XSAVE_AREA_ALIGN); 947 return ((struct savefpu *)p); 948 } 949 950 int 951 fpu_kern_enter(struct thread *td, struct fpu_kern_ctx *ctx, u_int flags) 952 { 953 struct pcb *pcb; 954 955 if ((flags & FPU_KERN_KTHR) != 0 && is_fpu_kern_thread(0)) { 956 ctx->flags = FPU_KERN_CTX_DUMMY; 957 return (0); 958 } 959 pcb = td->td_pcb; 960 KASSERT(!PCB_USER_FPU(pcb) || pcb->pcb_save == 961 get_pcb_user_save_pcb(pcb), ("mangled pcb_save")); 962 ctx->flags = 0; 963 if ((pcb->pcb_flags & PCB_FPUINITDONE) != 0) 964 ctx->flags |= FPU_KERN_CTX_FPUINITDONE; 965 fpuexit(td); 966 ctx->prev = pcb->pcb_save; 967 pcb->pcb_save = fpu_kern_ctx_savefpu(ctx); 968 set_pcb_flags(pcb, PCB_KERNFPU); 969 clear_pcb_flags(pcb, PCB_FPUINITDONE); 970 return (0); 971 } 972 973 int 974 fpu_kern_leave(struct thread *td, struct fpu_kern_ctx *ctx) 975 { 976 struct pcb *pcb; 977 978 if (is_fpu_kern_thread(0) && (ctx->flags & FPU_KERN_CTX_DUMMY) != 0) 979 return (0); 980 KASSERT((ctx->flags & FPU_KERN_CTX_DUMMY) == 0, ("dummy ctx")); 981 pcb = td->td_pcb; 982 critical_enter(); 983 if (curthread == PCPU_GET(fpcurthread)) 984 fpudrop(); 985 critical_exit(); 986 pcb->pcb_save = ctx->prev; 987 if (pcb->pcb_save == get_pcb_user_save_pcb(pcb)) { 988 if ((pcb->pcb_flags & PCB_USERFPUINITDONE) != 0) { 989 set_pcb_flags(pcb, PCB_FPUINITDONE); 990 clear_pcb_flags(pcb, PCB_KERNFPU); 991 } else 992 clear_pcb_flags(pcb, PCB_FPUINITDONE | PCB_KERNFPU); 993 } else { 994 if ((ctx->flags & FPU_KERN_CTX_FPUINITDONE) != 0) 995 set_pcb_flags(pcb, PCB_FPUINITDONE); 996 else 997 clear_pcb_flags(pcb, PCB_FPUINITDONE); 998 KASSERT(!PCB_USER_FPU(pcb), ("unpaired fpu_kern_leave")); 999 } 1000 return (0); 1001 } 1002 1003 int 1004 fpu_kern_thread(u_int flags) 1005 { 1006 1007 KASSERT((curthread->td_pflags & TDP_KTHREAD) != 0, 1008 ("Only kthread may use fpu_kern_thread")); 1009 KASSERT(curpcb->pcb_save == get_pcb_user_save_pcb(curpcb), 1010 ("mangled pcb_save")); 1011 KASSERT(PCB_USER_FPU(curpcb), ("recursive call")); 1012 1013 set_pcb_flags(curpcb, PCB_KERNFPU); 1014 return (0); 1015 } 1016 1017 int 1018 is_fpu_kern_thread(u_int flags) 1019 { 1020 1021 if ((curthread->td_pflags & TDP_KTHREAD) == 0) 1022 return (0); 1023 return ((curpcb->pcb_flags & PCB_KERNFPU) != 0); 1024 } 1025 1026 /* 1027 * FPU save area alloc/free/init utility routines 1028 */ 1029 struct savefpu * 1030 fpu_save_area_alloc(void) 1031 { 1032 1033 return (uma_zalloc(fpu_save_area_zone, 0)); 1034 } 1035 1036 void 1037 fpu_save_area_free(struct savefpu *fsa) 1038 { 1039 1040 uma_zfree(fpu_save_area_zone, fsa); 1041 } 1042 1043 void 1044 fpu_save_area_reset(struct savefpu *fsa) 1045 { 1046 1047 bcopy(fpu_initialstate, fsa, cpu_max_ext_state_size); 1048 } 1049