1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 1990 William Jolitz. 5 * Copyright (c) 1991 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of the University nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 33 */ 34 35 #include <sys/cdefs.h> 36 __FBSDID("$FreeBSD$"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/bus.h> 41 #include <sys/domainset.h> 42 #include <sys/kernel.h> 43 #include <sys/lock.h> 44 #include <sys/malloc.h> 45 #include <sys/module.h> 46 #include <sys/mutex.h> 47 #include <sys/mutex.h> 48 #include <sys/proc.h> 49 #include <sys/sysctl.h> 50 #include <sys/sysent.h> 51 #include <machine/bus.h> 52 #include <sys/rman.h> 53 #include <sys/signalvar.h> 54 #include <vm/uma.h> 55 56 #include <machine/cputypes.h> 57 #include <machine/frame.h> 58 #include <machine/intr_machdep.h> 59 #include <machine/md_var.h> 60 #include <machine/pcb.h> 61 #include <machine/psl.h> 62 #include <machine/resource.h> 63 #include <machine/specialreg.h> 64 #include <machine/segments.h> 65 #include <machine/ucontext.h> 66 #include <x86/ifunc.h> 67 68 /* 69 * Floating point support. 70 */ 71 72 #if defined(__GNUCLIKE_ASM) && !defined(lint) 73 74 #define fldcw(cw) __asm __volatile("fldcw %0" : : "m" (cw)) 75 #define fnclex() __asm __volatile("fnclex") 76 #define fninit() __asm __volatile("fninit") 77 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 78 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=am" (*(addr))) 79 #define fxrstor(addr) __asm __volatile("fxrstor %0" : : "m" (*(addr))) 80 #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 81 #define ldmxcsr(csr) __asm __volatile("ldmxcsr %0" : : "m" (csr)) 82 #define stmxcsr(addr) __asm __volatile("stmxcsr %0" : "=m" (*(addr))) 83 84 static __inline void 85 xrstor32(char *addr, uint64_t mask) 86 { 87 uint32_t low, hi; 88 89 low = mask; 90 hi = mask >> 32; 91 __asm __volatile("xrstor %0" : : "m" (*addr), "a" (low), "d" (hi)); 92 } 93 94 static __inline void 95 xrstor64(char *addr, uint64_t mask) 96 { 97 uint32_t low, hi; 98 99 low = mask; 100 hi = mask >> 32; 101 __asm __volatile("xrstor64 %0" : : "m" (*addr), "a" (low), "d" (hi)); 102 } 103 104 static __inline void 105 xsave32(char *addr, uint64_t mask) 106 { 107 uint32_t low, hi; 108 109 low = mask; 110 hi = mask >> 32; 111 __asm __volatile("xsave %0" : "=m" (*addr) : "a" (low), "d" (hi) : 112 "memory"); 113 } 114 115 static __inline void 116 xsave64(char *addr, uint64_t mask) 117 { 118 uint32_t low, hi; 119 120 low = mask; 121 hi = mask >> 32; 122 __asm __volatile("xsave64 %0" : "=m" (*addr) : "a" (low), "d" (hi) : 123 "memory"); 124 } 125 126 static __inline void 127 xsaveopt32(char *addr, uint64_t mask) 128 { 129 uint32_t low, hi; 130 131 low = mask; 132 hi = mask >> 32; 133 __asm __volatile("xsaveopt %0" : "=m" (*addr) : "a" (low), "d" (hi) : 134 "memory"); 135 } 136 137 static __inline void 138 xsaveopt64(char *addr, uint64_t mask) 139 { 140 uint32_t low, hi; 141 142 low = mask; 143 hi = mask >> 32; 144 __asm __volatile("xsaveopt64 %0" : "=m" (*addr) : "a" (low), "d" (hi) : 145 "memory"); 146 } 147 148 #else /* !(__GNUCLIKE_ASM && !lint) */ 149 150 void fldcw(u_short cw); 151 void fnclex(void); 152 void fninit(void); 153 void fnstcw(caddr_t addr); 154 void fnstsw(caddr_t addr); 155 void fxsave(caddr_t addr); 156 void fxrstor(caddr_t addr); 157 void ldmxcsr(u_int csr); 158 void stmxcsr(u_int *csr); 159 void xrstor32(char *addr, uint64_t mask); 160 void xrstor64(char *addr, uint64_t mask); 161 void xsave32(char *addr, uint64_t mask); 162 void xsave64(char *addr, uint64_t mask); 163 void xsaveopt32(char *addr, uint64_t mask); 164 void xsaveopt64(char *addr, uint64_t mask); 165 166 #endif /* __GNUCLIKE_ASM && !lint */ 167 168 #define start_emulating() load_cr0(rcr0() | CR0_TS) 169 #define stop_emulating() clts() 170 171 CTASSERT(sizeof(struct savefpu) == 512); 172 CTASSERT(sizeof(struct xstate_hdr) == 64); 173 CTASSERT(sizeof(struct savefpu_ymm) == 832); 174 175 /* 176 * This requirement is to make it easier for asm code to calculate 177 * offset of the fpu save area from the pcb address. FPU save area 178 * must be 64-byte aligned. 179 */ 180 CTASSERT(sizeof(struct pcb) % XSAVE_AREA_ALIGN == 0); 181 182 /* 183 * Ensure the copy of XCR0 saved in a core is contained in the padding 184 * area. 185 */ 186 CTASSERT(X86_XSTATE_XCR0_OFFSET >= offsetof(struct savefpu, sv_pad) && 187 X86_XSTATE_XCR0_OFFSET + sizeof(uint64_t) <= sizeof(struct savefpu)); 188 189 static void fpu_clean_state(void); 190 191 SYSCTL_INT(_hw, HW_FLOATINGPT, floatingpoint, CTLFLAG_RD, 192 SYSCTL_NULL_INT_PTR, 1, "Floating point instructions executed in hardware"); 193 194 int use_xsave; /* non-static for cpu_switch.S */ 195 uint64_t xsave_mask; /* the same */ 196 static uma_zone_t fpu_save_area_zone; 197 static struct savefpu *fpu_initialstate; 198 199 static struct xsave_area_elm_descr { 200 u_int offset; 201 u_int size; 202 } *xsave_area_desc; 203 204 static void 205 fpusave_xsaveopt64(void *addr) 206 { 207 xsaveopt64((char *)addr, xsave_mask); 208 } 209 210 static void 211 fpusave_xsaveopt3264(void *addr) 212 { 213 if (SV_CURPROC_FLAG(SV_ILP32)) 214 xsaveopt32((char *)addr, xsave_mask); 215 else 216 xsaveopt64((char *)addr, xsave_mask); 217 } 218 219 static void 220 fpusave_xsave64(void *addr) 221 { 222 xsave64((char *)addr, xsave_mask); 223 } 224 225 static void 226 fpusave_xsave3264(void *addr) 227 { 228 if (SV_CURPROC_FLAG(SV_ILP32)) 229 xsave32((char *)addr, xsave_mask); 230 else 231 xsave64((char *)addr, xsave_mask); 232 } 233 234 static void 235 fpurestore_xrstor64(void *addr) 236 { 237 xrstor64((char *)addr, xsave_mask); 238 } 239 240 static void 241 fpurestore_xrstor3264(void *addr) 242 { 243 if (SV_CURPROC_FLAG(SV_ILP32)) 244 xrstor32((char *)addr, xsave_mask); 245 else 246 xrstor64((char *)addr, xsave_mask); 247 } 248 249 static void 250 fpusave_fxsave(void *addr) 251 { 252 253 fxsave((char *)addr); 254 } 255 256 static void 257 fpurestore_fxrstor(void *addr) 258 { 259 260 fxrstor((char *)addr); 261 } 262 263 static void 264 init_xsave(void) 265 { 266 267 if (use_xsave) 268 return; 269 if ((cpu_feature2 & CPUID2_XSAVE) == 0) 270 return; 271 use_xsave = 1; 272 TUNABLE_INT_FETCH("hw.use_xsave", &use_xsave); 273 } 274 275 DEFINE_IFUNC(, void, fpusave, (void *)) 276 { 277 278 init_xsave(); 279 if (!use_xsave) 280 return (fpusave_fxsave); 281 if ((cpu_stdext_feature & CPUID_EXTSTATE_XSAVEOPT) != 0) { 282 return ((cpu_stdext_feature & CPUID_STDEXT_NFPUSG) != 0 ? 283 fpusave_xsaveopt64 : fpusave_xsaveopt3264); 284 } 285 return ((cpu_stdext_feature & CPUID_STDEXT_NFPUSG) != 0 ? 286 fpusave_xsave64 : fpusave_xsave3264); 287 } 288 289 DEFINE_IFUNC(, void, fpurestore, (void *)) 290 { 291 292 init_xsave(); 293 if (!use_xsave) 294 return (fpurestore_fxrstor); 295 return ((cpu_stdext_feature & CPUID_STDEXT_NFPUSG) != 0 ? 296 fpurestore_xrstor64 : fpurestore_xrstor3264); 297 } 298 299 void 300 fpususpend(void *addr) 301 { 302 u_long cr0; 303 304 cr0 = rcr0(); 305 stop_emulating(); 306 fpusave(addr); 307 load_cr0(cr0); 308 } 309 310 void 311 fpuresume(void *addr) 312 { 313 u_long cr0; 314 315 cr0 = rcr0(); 316 stop_emulating(); 317 fninit(); 318 if (use_xsave) 319 load_xcr(XCR0, xsave_mask); 320 fpurestore(addr); 321 load_cr0(cr0); 322 } 323 324 /* 325 * Enable XSAVE if supported and allowed by user. 326 * Calculate the xsave_mask. 327 */ 328 static void 329 fpuinit_bsp1(void) 330 { 331 u_int cp[4]; 332 uint64_t xsave_mask_user; 333 bool old_wp; 334 335 if (!use_xsave) 336 return; 337 cpuid_count(0xd, 0x0, cp); 338 xsave_mask = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE; 339 if ((cp[0] & xsave_mask) != xsave_mask) 340 panic("CPU0 does not support X87 or SSE: %x", cp[0]); 341 xsave_mask = ((uint64_t)cp[3] << 32) | cp[0]; 342 xsave_mask_user = xsave_mask; 343 TUNABLE_ULONG_FETCH("hw.xsave_mask", &xsave_mask_user); 344 xsave_mask_user |= XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE; 345 xsave_mask &= xsave_mask_user; 346 if ((xsave_mask & XFEATURE_AVX512) != XFEATURE_AVX512) 347 xsave_mask &= ~XFEATURE_AVX512; 348 if ((xsave_mask & XFEATURE_MPX) != XFEATURE_MPX) 349 xsave_mask &= ~XFEATURE_MPX; 350 351 cpuid_count(0xd, 0x1, cp); 352 if ((cp[0] & CPUID_EXTSTATE_XSAVEOPT) != 0) { 353 /* 354 * Patch the XSAVE instruction in the cpu_switch code 355 * to XSAVEOPT. We assume that XSAVE encoding used 356 * REX byte, and set the bit 4 of the r/m byte. 357 * 358 * It seems that some BIOSes give control to the OS 359 * with CR0.WP already set, making the kernel text 360 * read-only before cpu_startup(). 361 */ 362 old_wp = disable_wp(); 363 ctx_switch_xsave32[3] |= 0x10; 364 ctx_switch_xsave[3] |= 0x10; 365 restore_wp(old_wp); 366 } 367 } 368 369 /* 370 * Calculate the fpu save area size. 371 */ 372 static void 373 fpuinit_bsp2(void) 374 { 375 u_int cp[4]; 376 377 if (use_xsave) { 378 cpuid_count(0xd, 0x0, cp); 379 cpu_max_ext_state_size = cp[1]; 380 381 /* 382 * Reload the cpu_feature2, since we enabled OSXSAVE. 383 */ 384 do_cpuid(1, cp); 385 cpu_feature2 = cp[2]; 386 } else 387 cpu_max_ext_state_size = sizeof(struct savefpu); 388 } 389 390 /* 391 * Initialize the floating point unit. 392 */ 393 void 394 fpuinit(void) 395 { 396 register_t saveintr; 397 u_int mxcsr; 398 u_short control; 399 400 if (IS_BSP()) 401 fpuinit_bsp1(); 402 403 if (use_xsave) { 404 load_cr4(rcr4() | CR4_XSAVE); 405 load_xcr(XCR0, xsave_mask); 406 } 407 408 /* 409 * XCR0 shall be set up before CPU can report the save area size. 410 */ 411 if (IS_BSP()) 412 fpuinit_bsp2(); 413 414 /* 415 * It is too early for critical_enter() to work on AP. 416 */ 417 saveintr = intr_disable(); 418 stop_emulating(); 419 fninit(); 420 control = __INITIAL_FPUCW__; 421 fldcw(control); 422 mxcsr = __INITIAL_MXCSR__; 423 ldmxcsr(mxcsr); 424 start_emulating(); 425 intr_restore(saveintr); 426 } 427 428 /* 429 * On the boot CPU we generate a clean state that is used to 430 * initialize the floating point unit when it is first used by a 431 * process. 432 */ 433 static void 434 fpuinitstate(void *arg __unused) 435 { 436 uint64_t *xstate_bv; 437 register_t saveintr; 438 int cp[4], i, max_ext_n; 439 440 /* Do potentially blocking operations before disabling interrupts. */ 441 fpu_save_area_zone = uma_zcreate("FPU_save_area", 442 cpu_max_ext_state_size, NULL, NULL, NULL, NULL, 443 XSAVE_AREA_ALIGN - 1, 0); 444 fpu_initialstate = uma_zalloc(fpu_save_area_zone, M_WAITOK | M_ZERO); 445 if (use_xsave) { 446 max_ext_n = flsl(xsave_mask); 447 xsave_area_desc = malloc(max_ext_n * sizeof(struct 448 xsave_area_elm_descr), M_DEVBUF, M_WAITOK | M_ZERO); 449 } 450 451 cpu_thread_alloc(&thread0); 452 453 saveintr = intr_disable(); 454 stop_emulating(); 455 456 fpusave_fxsave(fpu_initialstate); 457 if (fpu_initialstate->sv_env.en_mxcsr_mask) 458 cpu_mxcsr_mask = fpu_initialstate->sv_env.en_mxcsr_mask; 459 else 460 cpu_mxcsr_mask = 0xFFBF; 461 462 /* 463 * The fninit instruction does not modify XMM registers or x87 464 * registers (MM/ST). The fpusave call dumped the garbage 465 * contained in the registers after reset to the initial state 466 * saved. Clear XMM and x87 registers file image to make the 467 * startup program state and signal handler XMM/x87 register 468 * content predictable. 469 */ 470 bzero(fpu_initialstate->sv_fp, sizeof(fpu_initialstate->sv_fp)); 471 bzero(fpu_initialstate->sv_xmm, sizeof(fpu_initialstate->sv_xmm)); 472 473 /* 474 * Create a table describing the layout of the CPU Extended 475 * Save Area. 476 */ 477 if (use_xsave) { 478 xstate_bv = (uint64_t *)((char *)(fpu_initialstate + 1) + 479 offsetof(struct xstate_hdr, xstate_bv)); 480 *xstate_bv = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE; 481 482 /* x87 state */ 483 xsave_area_desc[0].offset = 0; 484 xsave_area_desc[0].size = 160; 485 /* XMM */ 486 xsave_area_desc[1].offset = 160; 487 xsave_area_desc[1].size = 288 - 160; 488 489 for (i = 2; i < max_ext_n; i++) { 490 cpuid_count(0xd, i, cp); 491 xsave_area_desc[i].offset = cp[1]; 492 xsave_area_desc[i].size = cp[0]; 493 } 494 } 495 496 start_emulating(); 497 intr_restore(saveintr); 498 } 499 /* EFIRT needs this to be initialized before we can enter our EFI environment */ 500 SYSINIT(fpuinitstate, SI_SUB_CPU, SI_ORDER_ANY, fpuinitstate, NULL); 501 502 /* 503 * Free coprocessor (if we have it). 504 */ 505 void 506 fpuexit(struct thread *td) 507 { 508 509 critical_enter(); 510 if (curthread == PCPU_GET(fpcurthread)) { 511 stop_emulating(); 512 fpusave(curpcb->pcb_save); 513 start_emulating(); 514 PCPU_SET(fpcurthread, NULL); 515 } 516 critical_exit(); 517 } 518 519 int 520 fpuformat(void) 521 { 522 523 return (_MC_FPFMT_XMM); 524 } 525 526 /* 527 * The following mechanism is used to ensure that the FPE_... value 528 * that is passed as a trapcode to the signal handler of the user 529 * process does not have more than one bit set. 530 * 531 * Multiple bits may be set if the user process modifies the control 532 * word while a status word bit is already set. While this is a sign 533 * of bad coding, we have no choise than to narrow them down to one 534 * bit, since we must not send a trapcode that is not exactly one of 535 * the FPE_ macros. 536 * 537 * The mechanism has a static table with 127 entries. Each combination 538 * of the 7 FPU status word exception bits directly translates to a 539 * position in this table, where a single FPE_... value is stored. 540 * This FPE_... value stored there is considered the "most important" 541 * of the exception bits and will be sent as the signal code. The 542 * precedence of the bits is based upon Intel Document "Numerical 543 * Applications", Chapter "Special Computational Situations". 544 * 545 * The macro to choose one of these values does these steps: 1) Throw 546 * away status word bits that cannot be masked. 2) Throw away the bits 547 * currently masked in the control word, assuming the user isn't 548 * interested in them anymore. 3) Reinsert status word bit 7 (stack 549 * fault) if it is set, which cannot be masked but must be presered. 550 * 4) Use the remaining bits to point into the trapcode table. 551 * 552 * The 6 maskable bits in order of their preference, as stated in the 553 * above referenced Intel manual: 554 * 1 Invalid operation (FP_X_INV) 555 * 1a Stack underflow 556 * 1b Stack overflow 557 * 1c Operand of unsupported format 558 * 1d SNaN operand. 559 * 2 QNaN operand (not an exception, irrelavant here) 560 * 3 Any other invalid-operation not mentioned above or zero divide 561 * (FP_X_INV, FP_X_DZ) 562 * 4 Denormal operand (FP_X_DNML) 563 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 564 * 6 Inexact result (FP_X_IMP) 565 */ 566 static char fpetable[128] = { 567 0, 568 FPE_FLTINV, /* 1 - INV */ 569 FPE_FLTUND, /* 2 - DNML */ 570 FPE_FLTINV, /* 3 - INV | DNML */ 571 FPE_FLTDIV, /* 4 - DZ */ 572 FPE_FLTINV, /* 5 - INV | DZ */ 573 FPE_FLTDIV, /* 6 - DNML | DZ */ 574 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 575 FPE_FLTOVF, /* 8 - OFL */ 576 FPE_FLTINV, /* 9 - INV | OFL */ 577 FPE_FLTUND, /* A - DNML | OFL */ 578 FPE_FLTINV, /* B - INV | DNML | OFL */ 579 FPE_FLTDIV, /* C - DZ | OFL */ 580 FPE_FLTINV, /* D - INV | DZ | OFL */ 581 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 582 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 583 FPE_FLTUND, /* 10 - UFL */ 584 FPE_FLTINV, /* 11 - INV | UFL */ 585 FPE_FLTUND, /* 12 - DNML | UFL */ 586 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 587 FPE_FLTDIV, /* 14 - DZ | UFL */ 588 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 589 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 590 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 591 FPE_FLTOVF, /* 18 - OFL | UFL */ 592 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 593 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 594 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 595 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 596 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 597 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 598 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 599 FPE_FLTRES, /* 20 - IMP */ 600 FPE_FLTINV, /* 21 - INV | IMP */ 601 FPE_FLTUND, /* 22 - DNML | IMP */ 602 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 603 FPE_FLTDIV, /* 24 - DZ | IMP */ 604 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 605 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 606 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 607 FPE_FLTOVF, /* 28 - OFL | IMP */ 608 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 609 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 610 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 611 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 612 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 613 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 614 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 615 FPE_FLTUND, /* 30 - UFL | IMP */ 616 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 617 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 618 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 619 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 620 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 621 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 622 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 623 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 624 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 625 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 626 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 627 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 628 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 629 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 630 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 631 FPE_FLTSUB, /* 40 - STK */ 632 FPE_FLTSUB, /* 41 - INV | STK */ 633 FPE_FLTUND, /* 42 - DNML | STK */ 634 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 635 FPE_FLTDIV, /* 44 - DZ | STK */ 636 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 637 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 638 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 639 FPE_FLTOVF, /* 48 - OFL | STK */ 640 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 641 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 642 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 643 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 644 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 645 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 646 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 647 FPE_FLTUND, /* 50 - UFL | STK */ 648 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 649 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 650 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 651 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 652 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 653 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 654 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 655 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 656 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 657 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 658 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 659 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 660 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 661 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 662 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 663 FPE_FLTRES, /* 60 - IMP | STK */ 664 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 665 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 666 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 667 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 668 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 669 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 670 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 671 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 672 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 673 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 674 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 675 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 676 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 677 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 678 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 679 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 680 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 681 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 682 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 683 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 684 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 685 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 686 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 687 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 688 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 689 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 690 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 691 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 692 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 693 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 694 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 695 }; 696 697 /* 698 * Read the FP status and control words, then generate si_code value 699 * for SIGFPE. The error code chosen will be one of the 700 * FPE_... macros. It will be sent as the second argument to old 701 * BSD-style signal handlers and as "siginfo_t->si_code" (second 702 * argument) to SA_SIGINFO signal handlers. 703 * 704 * Some time ago, we cleared the x87 exceptions with FNCLEX there. 705 * Clearing exceptions was necessary mainly to avoid IRQ13 bugs. The 706 * usermode code which understands the FPU hardware enough to enable 707 * the exceptions, can also handle clearing the exception state in the 708 * handler. The only consequence of not clearing the exception is the 709 * rethrow of the SIGFPE on return from the signal handler and 710 * reexecution of the corresponding instruction. 711 * 712 * For XMM traps, the exceptions were never cleared. 713 */ 714 int 715 fputrap_x87(void) 716 { 717 struct savefpu *pcb_save; 718 u_short control, status; 719 720 critical_enter(); 721 722 /* 723 * Interrupt handling (for another interrupt) may have pushed the 724 * state to memory. Fetch the relevant parts of the state from 725 * wherever they are. 726 */ 727 if (PCPU_GET(fpcurthread) != curthread) { 728 pcb_save = curpcb->pcb_save; 729 control = pcb_save->sv_env.en_cw; 730 status = pcb_save->sv_env.en_sw; 731 } else { 732 fnstcw(&control); 733 fnstsw(&status); 734 } 735 736 critical_exit(); 737 return (fpetable[status & ((~control & 0x3f) | 0x40)]); 738 } 739 740 int 741 fputrap_sse(void) 742 { 743 u_int mxcsr; 744 745 critical_enter(); 746 if (PCPU_GET(fpcurthread) != curthread) 747 mxcsr = curpcb->pcb_save->sv_env.en_mxcsr; 748 else 749 stmxcsr(&mxcsr); 750 critical_exit(); 751 return (fpetable[(mxcsr & (~mxcsr >> 7)) & 0x3f]); 752 } 753 754 static void 755 restore_fpu_curthread(struct thread *td) 756 { 757 struct pcb *pcb; 758 759 /* 760 * Record new context early in case frstor causes a trap. 761 */ 762 PCPU_SET(fpcurthread, td); 763 764 stop_emulating(); 765 fpu_clean_state(); 766 pcb = td->td_pcb; 767 768 if ((pcb->pcb_flags & PCB_FPUINITDONE) == 0) { 769 /* 770 * This is the first time this thread has used the FPU or 771 * the PCB doesn't contain a clean FPU state. Explicitly 772 * load an initial state. 773 * 774 * We prefer to restore the state from the actual save 775 * area in PCB instead of directly loading from 776 * fpu_initialstate, to ignite the XSAVEOPT 777 * tracking engine. 778 */ 779 bcopy(fpu_initialstate, pcb->pcb_save, 780 cpu_max_ext_state_size); 781 fpurestore(pcb->pcb_save); 782 if (pcb->pcb_initial_fpucw != __INITIAL_FPUCW__) 783 fldcw(pcb->pcb_initial_fpucw); 784 if (PCB_USER_FPU(pcb)) 785 set_pcb_flags(pcb, PCB_FPUINITDONE | 786 PCB_USERFPUINITDONE); 787 else 788 set_pcb_flags(pcb, PCB_FPUINITDONE); 789 } else 790 fpurestore(pcb->pcb_save); 791 } 792 793 /* 794 * Device Not Available (DNA, #NM) exception handler. 795 * 796 * It would be better to switch FP context here (if curthread != 797 * fpcurthread) and not necessarily for every context switch, but it 798 * is too hard to access foreign pcb's. 799 */ 800 void 801 fpudna(void) 802 { 803 struct thread *td; 804 805 td = curthread; 806 /* 807 * This handler is entered with interrupts enabled, so context 808 * switches may occur before critical_enter() is executed. If 809 * a context switch occurs, then when we regain control, our 810 * state will have been completely restored. The CPU may 811 * change underneath us, but the only part of our context that 812 * lives in the CPU is CR0.TS and that will be "restored" by 813 * setting it on the new CPU. 814 */ 815 critical_enter(); 816 817 KASSERT((curpcb->pcb_flags & PCB_FPUNOSAVE) == 0, 818 ("fpudna while in fpu_kern_enter(FPU_KERN_NOCTX)")); 819 if (__predict_false(PCPU_GET(fpcurthread) == td)) { 820 /* 821 * Some virtual machines seems to set %cr0.TS at 822 * arbitrary moments. Silently clear the TS bit 823 * regardless of the eager/lazy FPU context switch 824 * mode. 825 */ 826 stop_emulating(); 827 } else { 828 if (__predict_false(PCPU_GET(fpcurthread) != NULL)) { 829 panic( 830 "fpudna: fpcurthread = %p (%d), curthread = %p (%d)\n", 831 PCPU_GET(fpcurthread), 832 PCPU_GET(fpcurthread)->td_tid, td, td->td_tid); 833 } 834 restore_fpu_curthread(td); 835 } 836 critical_exit(); 837 } 838 839 void fpu_activate_sw(struct thread *td); /* Called from the context switch */ 840 void 841 fpu_activate_sw(struct thread *td) 842 { 843 844 if ((td->td_pflags & TDP_KTHREAD) != 0 || !PCB_USER_FPU(td->td_pcb)) { 845 PCPU_SET(fpcurthread, NULL); 846 start_emulating(); 847 } else if (PCPU_GET(fpcurthread) != td) { 848 restore_fpu_curthread(td); 849 } 850 } 851 852 void 853 fpudrop(void) 854 { 855 struct thread *td; 856 857 td = PCPU_GET(fpcurthread); 858 KASSERT(td == curthread, ("fpudrop: fpcurthread != curthread")); 859 CRITICAL_ASSERT(td); 860 PCPU_SET(fpcurthread, NULL); 861 clear_pcb_flags(td->td_pcb, PCB_FPUINITDONE); 862 start_emulating(); 863 } 864 865 /* 866 * Get the user state of the FPU into pcb->pcb_user_save without 867 * dropping ownership (if possible). It returns the FPU ownership 868 * status. 869 */ 870 int 871 fpugetregs(struct thread *td) 872 { 873 struct pcb *pcb; 874 uint64_t *xstate_bv, bit; 875 char *sa; 876 int max_ext_n, i, owned; 877 878 pcb = td->td_pcb; 879 critical_enter(); 880 if ((pcb->pcb_flags & PCB_USERFPUINITDONE) == 0) { 881 bcopy(fpu_initialstate, get_pcb_user_save_pcb(pcb), 882 cpu_max_ext_state_size); 883 get_pcb_user_save_pcb(pcb)->sv_env.en_cw = 884 pcb->pcb_initial_fpucw; 885 fpuuserinited(td); 886 critical_exit(); 887 return (_MC_FPOWNED_PCB); 888 } 889 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) { 890 fpusave(get_pcb_user_save_pcb(pcb)); 891 owned = _MC_FPOWNED_FPU; 892 } else { 893 owned = _MC_FPOWNED_PCB; 894 } 895 if (use_xsave) { 896 /* 897 * Handle partially saved state. 898 */ 899 sa = (char *)get_pcb_user_save_pcb(pcb); 900 xstate_bv = (uint64_t *)(sa + sizeof(struct savefpu) + 901 offsetof(struct xstate_hdr, xstate_bv)); 902 max_ext_n = flsl(xsave_mask); 903 for (i = 0; i < max_ext_n; i++) { 904 bit = 1ULL << i; 905 if ((xsave_mask & bit) == 0 || (*xstate_bv & bit) != 0) 906 continue; 907 bcopy((char *)fpu_initialstate + 908 xsave_area_desc[i].offset, 909 sa + xsave_area_desc[i].offset, 910 xsave_area_desc[i].size); 911 *xstate_bv |= bit; 912 } 913 } 914 critical_exit(); 915 return (owned); 916 } 917 918 void 919 fpuuserinited(struct thread *td) 920 { 921 struct pcb *pcb; 922 923 CRITICAL_ASSERT(td); 924 pcb = td->td_pcb; 925 if (PCB_USER_FPU(pcb)) 926 set_pcb_flags(pcb, 927 PCB_FPUINITDONE | PCB_USERFPUINITDONE); 928 else 929 set_pcb_flags(pcb, PCB_FPUINITDONE); 930 } 931 932 int 933 fpusetxstate(struct thread *td, char *xfpustate, size_t xfpustate_size) 934 { 935 struct xstate_hdr *hdr, *ehdr; 936 size_t len, max_len; 937 uint64_t bv; 938 939 /* XXXKIB should we clear all extended state in xstate_bv instead ? */ 940 if (xfpustate == NULL) 941 return (0); 942 if (!use_xsave) 943 return (EOPNOTSUPP); 944 945 len = xfpustate_size; 946 if (len < sizeof(struct xstate_hdr)) 947 return (EINVAL); 948 max_len = cpu_max_ext_state_size - sizeof(struct savefpu); 949 if (len > max_len) 950 return (EINVAL); 951 952 ehdr = (struct xstate_hdr *)xfpustate; 953 bv = ehdr->xstate_bv; 954 955 /* 956 * Avoid #gp. 957 */ 958 if (bv & ~xsave_mask) 959 return (EINVAL); 960 961 hdr = (struct xstate_hdr *)(get_pcb_user_save_td(td) + 1); 962 963 hdr->xstate_bv = bv; 964 bcopy(xfpustate + sizeof(struct xstate_hdr), 965 (char *)(hdr + 1), len - sizeof(struct xstate_hdr)); 966 967 return (0); 968 } 969 970 /* 971 * Set the state of the FPU. 972 */ 973 int 974 fpusetregs(struct thread *td, struct savefpu *addr, char *xfpustate, 975 size_t xfpustate_size) 976 { 977 struct pcb *pcb; 978 int error; 979 980 addr->sv_env.en_mxcsr &= cpu_mxcsr_mask; 981 pcb = td->td_pcb; 982 error = 0; 983 critical_enter(); 984 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) { 985 error = fpusetxstate(td, xfpustate, xfpustate_size); 986 if (error == 0) { 987 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr)); 988 fpurestore(get_pcb_user_save_td(td)); 989 set_pcb_flags(pcb, PCB_FPUINITDONE | 990 PCB_USERFPUINITDONE); 991 } 992 } else { 993 error = fpusetxstate(td, xfpustate, xfpustate_size); 994 if (error == 0) { 995 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr)); 996 fpuuserinited(td); 997 } 998 } 999 critical_exit(); 1000 return (error); 1001 } 1002 1003 /* 1004 * On AuthenticAMD processors, the fxrstor instruction does not restore 1005 * the x87's stored last instruction pointer, last data pointer, and last 1006 * opcode values, except in the rare case in which the exception summary 1007 * (ES) bit in the x87 status word is set to 1. 1008 * 1009 * In order to avoid leaking this information across processes, we clean 1010 * these values by performing a dummy load before executing fxrstor(). 1011 */ 1012 static void 1013 fpu_clean_state(void) 1014 { 1015 static float dummy_variable = 0.0; 1016 u_short status; 1017 1018 /* 1019 * Clear the ES bit in the x87 status word if it is currently 1020 * set, in order to avoid causing a fault in the upcoming load. 1021 */ 1022 fnstsw(&status); 1023 if (status & 0x80) 1024 fnclex(); 1025 1026 /* 1027 * Load the dummy variable into the x87 stack. This mangles 1028 * the x87 stack, but we don't care since we're about to call 1029 * fxrstor() anyway. 1030 */ 1031 __asm __volatile("ffree %%st(7); flds %0" : : "m" (dummy_variable)); 1032 } 1033 1034 /* 1035 * This really sucks. We want the acpi version only, but it requires 1036 * the isa_if.h file in order to get the definitions. 1037 */ 1038 #include "opt_isa.h" 1039 #ifdef DEV_ISA 1040 #include <isa/isavar.h> 1041 /* 1042 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI. 1043 */ 1044 static struct isa_pnp_id fpupnp_ids[] = { 1045 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */ 1046 { 0 } 1047 }; 1048 1049 static int 1050 fpupnp_probe(device_t dev) 1051 { 1052 int result; 1053 1054 result = ISA_PNP_PROBE(device_get_parent(dev), dev, fpupnp_ids); 1055 if (result <= 0) 1056 device_quiet(dev); 1057 return (result); 1058 } 1059 1060 static int 1061 fpupnp_attach(device_t dev) 1062 { 1063 1064 return (0); 1065 } 1066 1067 static device_method_t fpupnp_methods[] = { 1068 /* Device interface */ 1069 DEVMETHOD(device_probe, fpupnp_probe), 1070 DEVMETHOD(device_attach, fpupnp_attach), 1071 DEVMETHOD(device_detach, bus_generic_detach), 1072 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1073 DEVMETHOD(device_suspend, bus_generic_suspend), 1074 DEVMETHOD(device_resume, bus_generic_resume), 1075 { 0, 0 } 1076 }; 1077 1078 static driver_t fpupnp_driver = { 1079 "fpupnp", 1080 fpupnp_methods, 1081 1, /* no softc */ 1082 }; 1083 1084 static devclass_t fpupnp_devclass; 1085 1086 DRIVER_MODULE(fpupnp, acpi, fpupnp_driver, fpupnp_devclass, 0, 0); 1087 ISA_PNP_INFO(fpupnp_ids); 1088 #endif /* DEV_ISA */ 1089 1090 static MALLOC_DEFINE(M_FPUKERN_CTX, "fpukern_ctx", 1091 "Kernel contexts for FPU state"); 1092 1093 #define FPU_KERN_CTX_FPUINITDONE 0x01 1094 #define FPU_KERN_CTX_DUMMY 0x02 /* avoided save for the kern thread */ 1095 #define FPU_KERN_CTX_INUSE 0x04 1096 1097 struct fpu_kern_ctx { 1098 struct savefpu *prev; 1099 uint32_t flags; 1100 char hwstate1[]; 1101 }; 1102 1103 static inline size_t __pure2 1104 fpu_kern_alloc_sz(u_int max_est) 1105 { 1106 return (sizeof(struct fpu_kern_ctx) + XSAVE_AREA_ALIGN + max_est); 1107 } 1108 1109 static inline int __pure2 1110 fpu_kern_malloc_flags(u_int fpflags) 1111 { 1112 return (((fpflags & FPU_KERN_NOWAIT) ? M_NOWAIT : M_WAITOK) | M_ZERO); 1113 } 1114 1115 struct fpu_kern_ctx * 1116 fpu_kern_alloc_ctx_domain(int domain, u_int flags) 1117 { 1118 return (malloc_domainset(fpu_kern_alloc_sz(cpu_max_ext_state_size), 1119 M_FPUKERN_CTX, DOMAINSET_PREF(domain), 1120 fpu_kern_malloc_flags(flags))); 1121 } 1122 1123 struct fpu_kern_ctx * 1124 fpu_kern_alloc_ctx(u_int flags) 1125 { 1126 return (malloc(fpu_kern_alloc_sz(cpu_max_ext_state_size), 1127 M_FPUKERN_CTX, fpu_kern_malloc_flags(flags))); 1128 } 1129 1130 void 1131 fpu_kern_free_ctx(struct fpu_kern_ctx *ctx) 1132 { 1133 1134 KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) == 0, ("free'ing inuse ctx")); 1135 /* XXXKIB clear the memory ? */ 1136 free(ctx, M_FPUKERN_CTX); 1137 } 1138 1139 static struct savefpu * 1140 fpu_kern_ctx_savefpu(struct fpu_kern_ctx *ctx) 1141 { 1142 vm_offset_t p; 1143 1144 p = (vm_offset_t)&ctx->hwstate1; 1145 p = roundup2(p, XSAVE_AREA_ALIGN); 1146 return ((struct savefpu *)p); 1147 } 1148 1149 void 1150 fpu_kern_enter(struct thread *td, struct fpu_kern_ctx *ctx, u_int flags) 1151 { 1152 struct pcb *pcb; 1153 1154 pcb = td->td_pcb; 1155 KASSERT((flags & FPU_KERN_NOCTX) != 0 || ctx != NULL, 1156 ("ctx is required when !FPU_KERN_NOCTX")); 1157 KASSERT(ctx == NULL || (ctx->flags & FPU_KERN_CTX_INUSE) == 0, 1158 ("using inuse ctx")); 1159 KASSERT((pcb->pcb_flags & PCB_FPUNOSAVE) == 0, 1160 ("recursive fpu_kern_enter while in PCB_FPUNOSAVE state")); 1161 1162 if ((flags & FPU_KERN_NOCTX) != 0) { 1163 critical_enter(); 1164 stop_emulating(); 1165 if (curthread == PCPU_GET(fpcurthread)) { 1166 fpusave(curpcb->pcb_save); 1167 PCPU_SET(fpcurthread, NULL); 1168 } else { 1169 KASSERT(PCPU_GET(fpcurthread) == NULL, 1170 ("invalid fpcurthread")); 1171 } 1172 1173 /* 1174 * This breaks XSAVEOPT tracker, but 1175 * PCB_FPUNOSAVE state is supposed to never need to 1176 * save FPU context at all. 1177 */ 1178 fpurestore(fpu_initialstate); 1179 set_pcb_flags(pcb, PCB_KERNFPU | PCB_FPUNOSAVE | 1180 PCB_FPUINITDONE); 1181 return; 1182 } 1183 if ((flags & FPU_KERN_KTHR) != 0 && is_fpu_kern_thread(0)) { 1184 ctx->flags = FPU_KERN_CTX_DUMMY | FPU_KERN_CTX_INUSE; 1185 return; 1186 } 1187 critical_enter(); 1188 KASSERT(!PCB_USER_FPU(pcb) || pcb->pcb_save == 1189 get_pcb_user_save_pcb(pcb), ("mangled pcb_save")); 1190 ctx->flags = FPU_KERN_CTX_INUSE; 1191 if ((pcb->pcb_flags & PCB_FPUINITDONE) != 0) 1192 ctx->flags |= FPU_KERN_CTX_FPUINITDONE; 1193 fpuexit(td); 1194 ctx->prev = pcb->pcb_save; 1195 pcb->pcb_save = fpu_kern_ctx_savefpu(ctx); 1196 set_pcb_flags(pcb, PCB_KERNFPU); 1197 clear_pcb_flags(pcb, PCB_FPUINITDONE); 1198 critical_exit(); 1199 } 1200 1201 int 1202 fpu_kern_leave(struct thread *td, struct fpu_kern_ctx *ctx) 1203 { 1204 struct pcb *pcb; 1205 1206 pcb = td->td_pcb; 1207 1208 if ((pcb->pcb_flags & PCB_FPUNOSAVE) != 0) { 1209 KASSERT(ctx == NULL, ("non-null ctx after FPU_KERN_NOCTX")); 1210 KASSERT(PCPU_GET(fpcurthread) == NULL, 1211 ("non-NULL fpcurthread for PCB_FPUNOSAVE")); 1212 CRITICAL_ASSERT(td); 1213 1214 clear_pcb_flags(pcb, PCB_FPUNOSAVE | PCB_FPUINITDONE); 1215 start_emulating(); 1216 } else { 1217 KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) != 0, 1218 ("leaving not inuse ctx")); 1219 ctx->flags &= ~FPU_KERN_CTX_INUSE; 1220 1221 if (is_fpu_kern_thread(0) && 1222 (ctx->flags & FPU_KERN_CTX_DUMMY) != 0) 1223 return (0); 1224 KASSERT((ctx->flags & FPU_KERN_CTX_DUMMY) == 0, 1225 ("dummy ctx")); 1226 critical_enter(); 1227 if (curthread == PCPU_GET(fpcurthread)) 1228 fpudrop(); 1229 pcb->pcb_save = ctx->prev; 1230 } 1231 1232 if (pcb->pcb_save == get_pcb_user_save_pcb(pcb)) { 1233 if ((pcb->pcb_flags & PCB_USERFPUINITDONE) != 0) { 1234 set_pcb_flags(pcb, PCB_FPUINITDONE); 1235 if ((pcb->pcb_flags & PCB_KERNFPU_THR) == 0) 1236 clear_pcb_flags(pcb, PCB_KERNFPU); 1237 } else if ((pcb->pcb_flags & PCB_KERNFPU_THR) == 0) 1238 clear_pcb_flags(pcb, PCB_FPUINITDONE | PCB_KERNFPU); 1239 } else { 1240 if ((ctx->flags & FPU_KERN_CTX_FPUINITDONE) != 0) 1241 set_pcb_flags(pcb, PCB_FPUINITDONE); 1242 else 1243 clear_pcb_flags(pcb, PCB_FPUINITDONE); 1244 KASSERT(!PCB_USER_FPU(pcb), ("unpaired fpu_kern_leave")); 1245 } 1246 critical_exit(); 1247 return (0); 1248 } 1249 1250 int 1251 fpu_kern_thread(u_int flags) 1252 { 1253 1254 KASSERT((curthread->td_pflags & TDP_KTHREAD) != 0, 1255 ("Only kthread may use fpu_kern_thread")); 1256 KASSERT(curpcb->pcb_save == get_pcb_user_save_pcb(curpcb), 1257 ("mangled pcb_save")); 1258 KASSERT(PCB_USER_FPU(curpcb), ("recursive call")); 1259 1260 set_pcb_flags(curpcb, PCB_KERNFPU | PCB_KERNFPU_THR); 1261 return (0); 1262 } 1263 1264 int 1265 is_fpu_kern_thread(u_int flags) 1266 { 1267 1268 if ((curthread->td_pflags & TDP_KTHREAD) == 0) 1269 return (0); 1270 return ((curpcb->pcb_flags & PCB_KERNFPU_THR) != 0); 1271 } 1272 1273 /* 1274 * FPU save area alloc/free/init utility routines 1275 */ 1276 struct savefpu * 1277 fpu_save_area_alloc(void) 1278 { 1279 1280 return (uma_zalloc(fpu_save_area_zone, M_WAITOK)); 1281 } 1282 1283 void 1284 fpu_save_area_free(struct savefpu *fsa) 1285 { 1286 1287 uma_zfree(fpu_save_area_zone, fsa); 1288 } 1289 1290 void 1291 fpu_save_area_reset(struct savefpu *fsa) 1292 { 1293 1294 bcopy(fpu_initialstate, fsa, cpu_max_ext_state_size); 1295 } 1296