1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 1990 William Jolitz. 5 * Copyright (c) 1991 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of the University nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 33 */ 34 35 #include <sys/cdefs.h> 36 __FBSDID("$FreeBSD$"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/bus.h> 41 #include <sys/kernel.h> 42 #include <sys/lock.h> 43 #include <sys/malloc.h> 44 #include <sys/module.h> 45 #include <sys/mutex.h> 46 #include <sys/mutex.h> 47 #include <sys/proc.h> 48 #include <sys/sysctl.h> 49 #include <machine/bus.h> 50 #include <sys/rman.h> 51 #include <sys/signalvar.h> 52 #include <vm/uma.h> 53 54 #include <machine/cputypes.h> 55 #include <machine/frame.h> 56 #include <machine/intr_machdep.h> 57 #include <machine/md_var.h> 58 #include <machine/pcb.h> 59 #include <machine/psl.h> 60 #include <machine/resource.h> 61 #include <machine/specialreg.h> 62 #include <machine/segments.h> 63 #include <machine/ucontext.h> 64 #include <x86/ifunc.h> 65 66 /* 67 * Floating point support. 68 */ 69 70 #if defined(__GNUCLIKE_ASM) && !defined(lint) 71 72 #define fldcw(cw) __asm __volatile("fldcw %0" : : "m" (cw)) 73 #define fnclex() __asm __volatile("fnclex") 74 #define fninit() __asm __volatile("fninit") 75 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 76 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=am" (*(addr))) 77 #define fxrstor(addr) __asm __volatile("fxrstor %0" : : "m" (*(addr))) 78 #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 79 #define ldmxcsr(csr) __asm __volatile("ldmxcsr %0" : : "m" (csr)) 80 #define stmxcsr(addr) __asm __volatile("stmxcsr %0" : : "m" (*(addr))) 81 82 static __inline void 83 xrstor(char *addr, uint64_t mask) 84 { 85 uint32_t low, hi; 86 87 low = mask; 88 hi = mask >> 32; 89 __asm __volatile("xrstor %0" : : "m" (*addr), "a" (low), "d" (hi)); 90 } 91 92 static __inline void 93 xsave(char *addr, uint64_t mask) 94 { 95 uint32_t low, hi; 96 97 low = mask; 98 hi = mask >> 32; 99 __asm __volatile("xsave %0" : "=m" (*addr) : "a" (low), "d" (hi) : 100 "memory"); 101 } 102 103 static __inline void 104 xsaveopt(char *addr, uint64_t mask) 105 { 106 uint32_t low, hi; 107 108 low = mask; 109 hi = mask >> 32; 110 __asm __volatile("xsaveopt %0" : "=m" (*addr) : "a" (low), "d" (hi) : 111 "memory"); 112 } 113 114 #else /* !(__GNUCLIKE_ASM && !lint) */ 115 116 void fldcw(u_short cw); 117 void fnclex(void); 118 void fninit(void); 119 void fnstcw(caddr_t addr); 120 void fnstsw(caddr_t addr); 121 void fxsave(caddr_t addr); 122 void fxrstor(caddr_t addr); 123 void ldmxcsr(u_int csr); 124 void stmxcsr(u_int *csr); 125 void xrstor(char *addr, uint64_t mask); 126 void xsave(char *addr, uint64_t mask); 127 void xsaveopt(char *addr, uint64_t mask); 128 129 #endif /* __GNUCLIKE_ASM && !lint */ 130 131 #define start_emulating() load_cr0(rcr0() | CR0_TS) 132 #define stop_emulating() clts() 133 134 CTASSERT(sizeof(struct savefpu) == 512); 135 CTASSERT(sizeof(struct xstate_hdr) == 64); 136 CTASSERT(sizeof(struct savefpu_ymm) == 832); 137 138 /* 139 * This requirement is to make it easier for asm code to calculate 140 * offset of the fpu save area from the pcb address. FPU save area 141 * must be 64-byte aligned. 142 */ 143 CTASSERT(sizeof(struct pcb) % XSAVE_AREA_ALIGN == 0); 144 145 /* 146 * Ensure the copy of XCR0 saved in a core is contained in the padding 147 * area. 148 */ 149 CTASSERT(X86_XSTATE_XCR0_OFFSET >= offsetof(struct savefpu, sv_pad) && 150 X86_XSTATE_XCR0_OFFSET + sizeof(uint64_t) <= sizeof(struct savefpu)); 151 152 static void fpu_clean_state(void); 153 154 SYSCTL_INT(_hw, HW_FLOATINGPT, floatingpoint, CTLFLAG_RD, 155 SYSCTL_NULL_INT_PTR, 1, "Floating point instructions executed in hardware"); 156 157 int use_xsave; /* non-static for cpu_switch.S */ 158 uint64_t xsave_mask; /* the same */ 159 static uma_zone_t fpu_save_area_zone; 160 static struct savefpu *fpu_initialstate; 161 162 struct xsave_area_elm_descr { 163 u_int offset; 164 u_int size; 165 } *xsave_area_desc; 166 167 static void 168 fpusave_xsaveopt(void *addr) 169 { 170 171 xsaveopt((char *)addr, xsave_mask); 172 } 173 174 static void 175 fpusave_xsave(void *addr) 176 { 177 178 xsave((char *)addr, xsave_mask); 179 } 180 181 static void 182 fpurestore_xrstor(void *addr) 183 { 184 185 xrstor((char *)addr, xsave_mask); 186 } 187 188 static void 189 fpusave_fxsave(void *addr) 190 { 191 192 fxsave((char *)addr); 193 } 194 195 static void 196 fpurestore_fxrstor(void *addr) 197 { 198 199 fxrstor((char *)addr); 200 } 201 202 static void 203 init_xsave(void) 204 { 205 206 if (use_xsave) 207 return; 208 if ((cpu_feature2 & CPUID2_XSAVE) == 0) 209 return; 210 use_xsave = 1; 211 TUNABLE_INT_FETCH("hw.use_xsave", &use_xsave); 212 } 213 214 DEFINE_IFUNC(, void, fpusave, (void *)) 215 { 216 217 init_xsave(); 218 if (use_xsave) 219 return ((cpu_stdext_feature & CPUID_EXTSTATE_XSAVEOPT) != 0 ? 220 fpusave_xsaveopt : fpusave_xsave); 221 return (fpusave_fxsave); 222 } 223 224 DEFINE_IFUNC(, void, fpurestore, (void *)) 225 { 226 227 init_xsave(); 228 return (use_xsave ? fpurestore_xrstor : fpurestore_fxrstor); 229 } 230 231 void 232 fpususpend(void *addr) 233 { 234 u_long cr0; 235 236 cr0 = rcr0(); 237 stop_emulating(); 238 fpusave(addr); 239 load_cr0(cr0); 240 } 241 242 void 243 fpuresume(void *addr) 244 { 245 u_long cr0; 246 247 cr0 = rcr0(); 248 stop_emulating(); 249 fninit(); 250 if (use_xsave) 251 load_xcr(XCR0, xsave_mask); 252 fpurestore(addr); 253 load_cr0(cr0); 254 } 255 256 /* 257 * Enable XSAVE if supported and allowed by user. 258 * Calculate the xsave_mask. 259 */ 260 static void 261 fpuinit_bsp1(void) 262 { 263 u_int cp[4]; 264 uint64_t xsave_mask_user; 265 bool old_wp; 266 267 if (!use_xsave) 268 return; 269 cpuid_count(0xd, 0x0, cp); 270 xsave_mask = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE; 271 if ((cp[0] & xsave_mask) != xsave_mask) 272 panic("CPU0 does not support X87 or SSE: %x", cp[0]); 273 xsave_mask = ((uint64_t)cp[3] << 32) | cp[0]; 274 xsave_mask_user = xsave_mask; 275 TUNABLE_ULONG_FETCH("hw.xsave_mask", &xsave_mask_user); 276 xsave_mask_user |= XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE; 277 xsave_mask &= xsave_mask_user; 278 if ((xsave_mask & XFEATURE_AVX512) != XFEATURE_AVX512) 279 xsave_mask &= ~XFEATURE_AVX512; 280 if ((xsave_mask & XFEATURE_MPX) != XFEATURE_MPX) 281 xsave_mask &= ~XFEATURE_MPX; 282 283 cpuid_count(0xd, 0x1, cp); 284 if ((cp[0] & CPUID_EXTSTATE_XSAVEOPT) != 0) { 285 /* 286 * Patch the XSAVE instruction in the cpu_switch code 287 * to XSAVEOPT. We assume that XSAVE encoding used 288 * REX byte, and set the bit 4 of the r/m byte. 289 * 290 * It seems that some BIOSes give control to the OS 291 * with CR0.WP already set, making the kernel text 292 * read-only before cpu_startup(). 293 */ 294 old_wp = disable_wp(); 295 ctx_switch_xsave[3] |= 0x10; 296 restore_wp(old_wp); 297 } 298 } 299 300 /* 301 * Calculate the fpu save area size. 302 */ 303 static void 304 fpuinit_bsp2(void) 305 { 306 u_int cp[4]; 307 308 if (use_xsave) { 309 cpuid_count(0xd, 0x0, cp); 310 cpu_max_ext_state_size = cp[1]; 311 312 /* 313 * Reload the cpu_feature2, since we enabled OSXSAVE. 314 */ 315 do_cpuid(1, cp); 316 cpu_feature2 = cp[2]; 317 } else 318 cpu_max_ext_state_size = sizeof(struct savefpu); 319 } 320 321 /* 322 * Initialize the floating point unit. 323 */ 324 void 325 fpuinit(void) 326 { 327 register_t saveintr; 328 u_int mxcsr; 329 u_short control; 330 331 if (IS_BSP()) 332 fpuinit_bsp1(); 333 334 if (use_xsave) { 335 load_cr4(rcr4() | CR4_XSAVE); 336 load_xcr(XCR0, xsave_mask); 337 } 338 339 /* 340 * XCR0 shall be set up before CPU can report the save area size. 341 */ 342 if (IS_BSP()) 343 fpuinit_bsp2(); 344 345 /* 346 * It is too early for critical_enter() to work on AP. 347 */ 348 saveintr = intr_disable(); 349 stop_emulating(); 350 fninit(); 351 control = __INITIAL_FPUCW__; 352 fldcw(control); 353 mxcsr = __INITIAL_MXCSR__; 354 ldmxcsr(mxcsr); 355 start_emulating(); 356 intr_restore(saveintr); 357 } 358 359 /* 360 * On the boot CPU we generate a clean state that is used to 361 * initialize the floating point unit when it is first used by a 362 * process. 363 */ 364 static void 365 fpuinitstate(void *arg __unused) 366 { 367 uint64_t *xstate_bv; 368 register_t saveintr; 369 int cp[4], i, max_ext_n; 370 371 fpu_initialstate = malloc(cpu_max_ext_state_size, M_DEVBUF, 372 M_WAITOK | M_ZERO); 373 saveintr = intr_disable(); 374 stop_emulating(); 375 376 fpusave_fxsave(fpu_initialstate); 377 if (fpu_initialstate->sv_env.en_mxcsr_mask) 378 cpu_mxcsr_mask = fpu_initialstate->sv_env.en_mxcsr_mask; 379 else 380 cpu_mxcsr_mask = 0xFFBF; 381 382 /* 383 * The fninit instruction does not modify XMM registers or x87 384 * registers (MM/ST). The fpusave call dumped the garbage 385 * contained in the registers after reset to the initial state 386 * saved. Clear XMM and x87 registers file image to make the 387 * startup program state and signal handler XMM/x87 register 388 * content predictable. 389 */ 390 bzero(fpu_initialstate->sv_fp, sizeof(fpu_initialstate->sv_fp)); 391 bzero(fpu_initialstate->sv_xmm, sizeof(fpu_initialstate->sv_xmm)); 392 393 /* 394 * Create a table describing the layout of the CPU Extended 395 * Save Area. 396 */ 397 if (use_xsave) { 398 xstate_bv = (uint64_t *)((char *)(fpu_initialstate + 1) + 399 offsetof(struct xstate_hdr, xstate_bv)); 400 *xstate_bv = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE; 401 402 max_ext_n = flsl(xsave_mask); 403 xsave_area_desc = malloc(max_ext_n * sizeof(struct 404 xsave_area_elm_descr), M_DEVBUF, M_WAITOK | M_ZERO); 405 /* x87 state */ 406 xsave_area_desc[0].offset = 0; 407 xsave_area_desc[0].size = 160; 408 /* XMM */ 409 xsave_area_desc[1].offset = 160; 410 xsave_area_desc[1].size = 288 - 160; 411 412 for (i = 2; i < max_ext_n; i++) { 413 cpuid_count(0xd, i, cp); 414 xsave_area_desc[i].offset = cp[1]; 415 xsave_area_desc[i].size = cp[0]; 416 } 417 } 418 419 fpu_save_area_zone = uma_zcreate("FPU_save_area", 420 cpu_max_ext_state_size, NULL, NULL, NULL, NULL, 421 XSAVE_AREA_ALIGN - 1, 0); 422 423 start_emulating(); 424 intr_restore(saveintr); 425 } 426 /* EFIRT needs this to be initialized before we can enter our EFI environment */ 427 SYSINIT(fpuinitstate, SI_SUB_DRIVERS, SI_ORDER_FIRST, fpuinitstate, NULL); 428 429 /* 430 * Free coprocessor (if we have it). 431 */ 432 void 433 fpuexit(struct thread *td) 434 { 435 436 critical_enter(); 437 if (curthread == PCPU_GET(fpcurthread)) { 438 stop_emulating(); 439 fpusave(curpcb->pcb_save); 440 start_emulating(); 441 PCPU_SET(fpcurthread, NULL); 442 } 443 critical_exit(); 444 } 445 446 int 447 fpuformat(void) 448 { 449 450 return (_MC_FPFMT_XMM); 451 } 452 453 /* 454 * The following mechanism is used to ensure that the FPE_... value 455 * that is passed as a trapcode to the signal handler of the user 456 * process does not have more than one bit set. 457 * 458 * Multiple bits may be set if the user process modifies the control 459 * word while a status word bit is already set. While this is a sign 460 * of bad coding, we have no choise than to narrow them down to one 461 * bit, since we must not send a trapcode that is not exactly one of 462 * the FPE_ macros. 463 * 464 * The mechanism has a static table with 127 entries. Each combination 465 * of the 7 FPU status word exception bits directly translates to a 466 * position in this table, where a single FPE_... value is stored. 467 * This FPE_... value stored there is considered the "most important" 468 * of the exception bits and will be sent as the signal code. The 469 * precedence of the bits is based upon Intel Document "Numerical 470 * Applications", Chapter "Special Computational Situations". 471 * 472 * The macro to choose one of these values does these steps: 1) Throw 473 * away status word bits that cannot be masked. 2) Throw away the bits 474 * currently masked in the control word, assuming the user isn't 475 * interested in them anymore. 3) Reinsert status word bit 7 (stack 476 * fault) if it is set, which cannot be masked but must be presered. 477 * 4) Use the remaining bits to point into the trapcode table. 478 * 479 * The 6 maskable bits in order of their preference, as stated in the 480 * above referenced Intel manual: 481 * 1 Invalid operation (FP_X_INV) 482 * 1a Stack underflow 483 * 1b Stack overflow 484 * 1c Operand of unsupported format 485 * 1d SNaN operand. 486 * 2 QNaN operand (not an exception, irrelavant here) 487 * 3 Any other invalid-operation not mentioned above or zero divide 488 * (FP_X_INV, FP_X_DZ) 489 * 4 Denormal operand (FP_X_DNML) 490 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 491 * 6 Inexact result (FP_X_IMP) 492 */ 493 static char fpetable[128] = { 494 0, 495 FPE_FLTINV, /* 1 - INV */ 496 FPE_FLTUND, /* 2 - DNML */ 497 FPE_FLTINV, /* 3 - INV | DNML */ 498 FPE_FLTDIV, /* 4 - DZ */ 499 FPE_FLTINV, /* 5 - INV | DZ */ 500 FPE_FLTDIV, /* 6 - DNML | DZ */ 501 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 502 FPE_FLTOVF, /* 8 - OFL */ 503 FPE_FLTINV, /* 9 - INV | OFL */ 504 FPE_FLTUND, /* A - DNML | OFL */ 505 FPE_FLTINV, /* B - INV | DNML | OFL */ 506 FPE_FLTDIV, /* C - DZ | OFL */ 507 FPE_FLTINV, /* D - INV | DZ | OFL */ 508 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 509 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 510 FPE_FLTUND, /* 10 - UFL */ 511 FPE_FLTINV, /* 11 - INV | UFL */ 512 FPE_FLTUND, /* 12 - DNML | UFL */ 513 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 514 FPE_FLTDIV, /* 14 - DZ | UFL */ 515 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 516 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 517 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 518 FPE_FLTOVF, /* 18 - OFL | UFL */ 519 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 520 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 521 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 522 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 523 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 524 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 525 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 526 FPE_FLTRES, /* 20 - IMP */ 527 FPE_FLTINV, /* 21 - INV | IMP */ 528 FPE_FLTUND, /* 22 - DNML | IMP */ 529 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 530 FPE_FLTDIV, /* 24 - DZ | IMP */ 531 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 532 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 533 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 534 FPE_FLTOVF, /* 28 - OFL | IMP */ 535 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 536 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 537 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 538 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 539 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 540 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 541 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 542 FPE_FLTUND, /* 30 - UFL | IMP */ 543 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 544 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 545 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 546 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 547 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 548 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 549 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 550 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 551 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 552 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 553 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 554 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 555 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 556 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 557 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 558 FPE_FLTSUB, /* 40 - STK */ 559 FPE_FLTSUB, /* 41 - INV | STK */ 560 FPE_FLTUND, /* 42 - DNML | STK */ 561 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 562 FPE_FLTDIV, /* 44 - DZ | STK */ 563 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 564 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 565 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 566 FPE_FLTOVF, /* 48 - OFL | STK */ 567 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 568 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 569 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 570 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 571 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 572 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 573 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 574 FPE_FLTUND, /* 50 - UFL | STK */ 575 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 576 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 577 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 578 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 579 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 580 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 581 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 582 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 583 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 584 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 585 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 586 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 587 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 588 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 589 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 590 FPE_FLTRES, /* 60 - IMP | STK */ 591 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 592 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 593 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 594 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 595 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 596 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 597 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 598 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 599 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 600 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 601 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 602 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 603 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 604 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 605 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 606 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 607 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 608 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 609 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 610 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 611 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 612 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 613 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 614 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 615 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 616 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 617 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 618 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 619 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 620 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 621 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 622 }; 623 624 /* 625 * Read the FP status and control words, then generate si_code value 626 * for SIGFPE. The error code chosen will be one of the 627 * FPE_... macros. It will be sent as the second argument to old 628 * BSD-style signal handlers and as "siginfo_t->si_code" (second 629 * argument) to SA_SIGINFO signal handlers. 630 * 631 * Some time ago, we cleared the x87 exceptions with FNCLEX there. 632 * Clearing exceptions was necessary mainly to avoid IRQ13 bugs. The 633 * usermode code which understands the FPU hardware enough to enable 634 * the exceptions, can also handle clearing the exception state in the 635 * handler. The only consequence of not clearing the exception is the 636 * rethrow of the SIGFPE on return from the signal handler and 637 * reexecution of the corresponding instruction. 638 * 639 * For XMM traps, the exceptions were never cleared. 640 */ 641 int 642 fputrap_x87(void) 643 { 644 struct savefpu *pcb_save; 645 u_short control, status; 646 647 critical_enter(); 648 649 /* 650 * Interrupt handling (for another interrupt) may have pushed the 651 * state to memory. Fetch the relevant parts of the state from 652 * wherever they are. 653 */ 654 if (PCPU_GET(fpcurthread) != curthread) { 655 pcb_save = curpcb->pcb_save; 656 control = pcb_save->sv_env.en_cw; 657 status = pcb_save->sv_env.en_sw; 658 } else { 659 fnstcw(&control); 660 fnstsw(&status); 661 } 662 663 critical_exit(); 664 return (fpetable[status & ((~control & 0x3f) | 0x40)]); 665 } 666 667 int 668 fputrap_sse(void) 669 { 670 u_int mxcsr; 671 672 critical_enter(); 673 if (PCPU_GET(fpcurthread) != curthread) 674 mxcsr = curpcb->pcb_save->sv_env.en_mxcsr; 675 else 676 stmxcsr(&mxcsr); 677 critical_exit(); 678 return (fpetable[(mxcsr & (~mxcsr >> 7)) & 0x3f]); 679 } 680 681 static void 682 restore_fpu_curthread(struct thread *td) 683 { 684 struct pcb *pcb; 685 686 /* 687 * Record new context early in case frstor causes a trap. 688 */ 689 PCPU_SET(fpcurthread, td); 690 691 stop_emulating(); 692 fpu_clean_state(); 693 pcb = td->td_pcb; 694 695 if ((pcb->pcb_flags & PCB_FPUINITDONE) == 0) { 696 /* 697 * This is the first time this thread has used the FPU or 698 * the PCB doesn't contain a clean FPU state. Explicitly 699 * load an initial state. 700 * 701 * We prefer to restore the state from the actual save 702 * area in PCB instead of directly loading from 703 * fpu_initialstate, to ignite the XSAVEOPT 704 * tracking engine. 705 */ 706 bcopy(fpu_initialstate, pcb->pcb_save, 707 cpu_max_ext_state_size); 708 fpurestore(pcb->pcb_save); 709 if (pcb->pcb_initial_fpucw != __INITIAL_FPUCW__) 710 fldcw(pcb->pcb_initial_fpucw); 711 if (PCB_USER_FPU(pcb)) 712 set_pcb_flags(pcb, PCB_FPUINITDONE | 713 PCB_USERFPUINITDONE); 714 else 715 set_pcb_flags(pcb, PCB_FPUINITDONE); 716 } else 717 fpurestore(pcb->pcb_save); 718 } 719 720 /* 721 * Device Not Available (DNA, #NM) exception handler. 722 * 723 * It would be better to switch FP context here (if curthread != 724 * fpcurthread) and not necessarily for every context switch, but it 725 * is too hard to access foreign pcb's. 726 */ 727 void 728 fpudna(void) 729 { 730 struct thread *td; 731 732 td = curthread; 733 /* 734 * This handler is entered with interrupts enabled, so context 735 * switches may occur before critical_enter() is executed. If 736 * a context switch occurs, then when we regain control, our 737 * state will have been completely restored. The CPU may 738 * change underneath us, but the only part of our context that 739 * lives in the CPU is CR0.TS and that will be "restored" by 740 * setting it on the new CPU. 741 */ 742 critical_enter(); 743 744 KASSERT((curpcb->pcb_flags & PCB_FPUNOSAVE) == 0, 745 ("fpudna while in fpu_kern_enter(FPU_KERN_NOCTX)")); 746 if (__predict_false(PCPU_GET(fpcurthread) == td)) { 747 /* 748 * Some virtual machines seems to set %cr0.TS at 749 * arbitrary moments. Silently clear the TS bit 750 * regardless of the eager/lazy FPU context switch 751 * mode. 752 */ 753 stop_emulating(); 754 } else { 755 if (__predict_false(PCPU_GET(fpcurthread) != NULL)) { 756 panic( 757 "fpudna: fpcurthread = %p (%d), curthread = %p (%d)\n", 758 PCPU_GET(fpcurthread), 759 PCPU_GET(fpcurthread)->td_tid, td, td->td_tid); 760 } 761 restore_fpu_curthread(td); 762 } 763 critical_exit(); 764 } 765 766 void fpu_activate_sw(struct thread *td); /* Called from the context switch */ 767 void 768 fpu_activate_sw(struct thread *td) 769 { 770 771 if ((td->td_pflags & TDP_KTHREAD) != 0 || !PCB_USER_FPU(td->td_pcb)) { 772 PCPU_SET(fpcurthread, NULL); 773 start_emulating(); 774 } else if (PCPU_GET(fpcurthread) != td) { 775 restore_fpu_curthread(td); 776 } 777 } 778 779 void 780 fpudrop(void) 781 { 782 struct thread *td; 783 784 td = PCPU_GET(fpcurthread); 785 KASSERT(td == curthread, ("fpudrop: fpcurthread != curthread")); 786 CRITICAL_ASSERT(td); 787 PCPU_SET(fpcurthread, NULL); 788 clear_pcb_flags(td->td_pcb, PCB_FPUINITDONE); 789 start_emulating(); 790 } 791 792 /* 793 * Get the user state of the FPU into pcb->pcb_user_save without 794 * dropping ownership (if possible). It returns the FPU ownership 795 * status. 796 */ 797 int 798 fpugetregs(struct thread *td) 799 { 800 struct pcb *pcb; 801 uint64_t *xstate_bv, bit; 802 char *sa; 803 int max_ext_n, i, owned; 804 805 pcb = td->td_pcb; 806 critical_enter(); 807 if ((pcb->pcb_flags & PCB_USERFPUINITDONE) == 0) { 808 bcopy(fpu_initialstate, get_pcb_user_save_pcb(pcb), 809 cpu_max_ext_state_size); 810 get_pcb_user_save_pcb(pcb)->sv_env.en_cw = 811 pcb->pcb_initial_fpucw; 812 fpuuserinited(td); 813 critical_exit(); 814 return (_MC_FPOWNED_PCB); 815 } 816 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) { 817 fpusave(get_pcb_user_save_pcb(pcb)); 818 owned = _MC_FPOWNED_FPU; 819 } else { 820 owned = _MC_FPOWNED_PCB; 821 } 822 if (use_xsave) { 823 /* 824 * Handle partially saved state. 825 */ 826 sa = (char *)get_pcb_user_save_pcb(pcb); 827 xstate_bv = (uint64_t *)(sa + sizeof(struct savefpu) + 828 offsetof(struct xstate_hdr, xstate_bv)); 829 max_ext_n = flsl(xsave_mask); 830 for (i = 0; i < max_ext_n; i++) { 831 bit = 1ULL << i; 832 if ((xsave_mask & bit) == 0 || (*xstate_bv & bit) != 0) 833 continue; 834 bcopy((char *)fpu_initialstate + 835 xsave_area_desc[i].offset, 836 sa + xsave_area_desc[i].offset, 837 xsave_area_desc[i].size); 838 *xstate_bv |= bit; 839 } 840 } 841 critical_exit(); 842 return (owned); 843 } 844 845 void 846 fpuuserinited(struct thread *td) 847 { 848 struct pcb *pcb; 849 850 CRITICAL_ASSERT(td); 851 pcb = td->td_pcb; 852 if (PCB_USER_FPU(pcb)) 853 set_pcb_flags(pcb, 854 PCB_FPUINITDONE | PCB_USERFPUINITDONE); 855 else 856 set_pcb_flags(pcb, PCB_FPUINITDONE); 857 } 858 859 int 860 fpusetxstate(struct thread *td, char *xfpustate, size_t xfpustate_size) 861 { 862 struct xstate_hdr *hdr, *ehdr; 863 size_t len, max_len; 864 uint64_t bv; 865 866 /* XXXKIB should we clear all extended state in xstate_bv instead ? */ 867 if (xfpustate == NULL) 868 return (0); 869 if (!use_xsave) 870 return (EOPNOTSUPP); 871 872 len = xfpustate_size; 873 if (len < sizeof(struct xstate_hdr)) 874 return (EINVAL); 875 max_len = cpu_max_ext_state_size - sizeof(struct savefpu); 876 if (len > max_len) 877 return (EINVAL); 878 879 ehdr = (struct xstate_hdr *)xfpustate; 880 bv = ehdr->xstate_bv; 881 882 /* 883 * Avoid #gp. 884 */ 885 if (bv & ~xsave_mask) 886 return (EINVAL); 887 888 hdr = (struct xstate_hdr *)(get_pcb_user_save_td(td) + 1); 889 890 hdr->xstate_bv = bv; 891 bcopy(xfpustate + sizeof(struct xstate_hdr), 892 (char *)(hdr + 1), len - sizeof(struct xstate_hdr)); 893 894 return (0); 895 } 896 897 /* 898 * Set the state of the FPU. 899 */ 900 int 901 fpusetregs(struct thread *td, struct savefpu *addr, char *xfpustate, 902 size_t xfpustate_size) 903 { 904 struct pcb *pcb; 905 int error; 906 907 addr->sv_env.en_mxcsr &= cpu_mxcsr_mask; 908 pcb = td->td_pcb; 909 error = 0; 910 critical_enter(); 911 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) { 912 error = fpusetxstate(td, xfpustate, xfpustate_size); 913 if (error == 0) { 914 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr)); 915 fpurestore(get_pcb_user_save_td(td)); 916 set_pcb_flags(pcb, PCB_FPUINITDONE | 917 PCB_USERFPUINITDONE); 918 } 919 } else { 920 error = fpusetxstate(td, xfpustate, xfpustate_size); 921 if (error == 0) { 922 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr)); 923 fpuuserinited(td); 924 } 925 } 926 critical_exit(); 927 return (error); 928 } 929 930 /* 931 * On AuthenticAMD processors, the fxrstor instruction does not restore 932 * the x87's stored last instruction pointer, last data pointer, and last 933 * opcode values, except in the rare case in which the exception summary 934 * (ES) bit in the x87 status word is set to 1. 935 * 936 * In order to avoid leaking this information across processes, we clean 937 * these values by performing a dummy load before executing fxrstor(). 938 */ 939 static void 940 fpu_clean_state(void) 941 { 942 static float dummy_variable = 0.0; 943 u_short status; 944 945 /* 946 * Clear the ES bit in the x87 status word if it is currently 947 * set, in order to avoid causing a fault in the upcoming load. 948 */ 949 fnstsw(&status); 950 if (status & 0x80) 951 fnclex(); 952 953 /* 954 * Load the dummy variable into the x87 stack. This mangles 955 * the x87 stack, but we don't care since we're about to call 956 * fxrstor() anyway. 957 */ 958 __asm __volatile("ffree %%st(7); flds %0" : : "m" (dummy_variable)); 959 } 960 961 /* 962 * This really sucks. We want the acpi version only, but it requires 963 * the isa_if.h file in order to get the definitions. 964 */ 965 #include "opt_isa.h" 966 #ifdef DEV_ISA 967 #include <isa/isavar.h> 968 /* 969 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI. 970 */ 971 static struct isa_pnp_id fpupnp_ids[] = { 972 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */ 973 { 0 } 974 }; 975 976 static int 977 fpupnp_probe(device_t dev) 978 { 979 int result; 980 981 result = ISA_PNP_PROBE(device_get_parent(dev), dev, fpupnp_ids); 982 if (result <= 0) 983 device_quiet(dev); 984 return (result); 985 } 986 987 static int 988 fpupnp_attach(device_t dev) 989 { 990 991 return (0); 992 } 993 994 static device_method_t fpupnp_methods[] = { 995 /* Device interface */ 996 DEVMETHOD(device_probe, fpupnp_probe), 997 DEVMETHOD(device_attach, fpupnp_attach), 998 DEVMETHOD(device_detach, bus_generic_detach), 999 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1000 DEVMETHOD(device_suspend, bus_generic_suspend), 1001 DEVMETHOD(device_resume, bus_generic_resume), 1002 1003 { 0, 0 } 1004 }; 1005 1006 static driver_t fpupnp_driver = { 1007 "fpupnp", 1008 fpupnp_methods, 1009 1, /* no softc */ 1010 }; 1011 1012 static devclass_t fpupnp_devclass; 1013 1014 DRIVER_MODULE(fpupnp, acpi, fpupnp_driver, fpupnp_devclass, 0, 0); 1015 ISA_PNP_INFO(fpupnp_ids); 1016 #endif /* DEV_ISA */ 1017 1018 static MALLOC_DEFINE(M_FPUKERN_CTX, "fpukern_ctx", 1019 "Kernel contexts for FPU state"); 1020 1021 #define FPU_KERN_CTX_FPUINITDONE 0x01 1022 #define FPU_KERN_CTX_DUMMY 0x02 /* avoided save for the kern thread */ 1023 #define FPU_KERN_CTX_INUSE 0x04 1024 1025 struct fpu_kern_ctx { 1026 struct savefpu *prev; 1027 uint32_t flags; 1028 char hwstate1[]; 1029 }; 1030 1031 struct fpu_kern_ctx * 1032 fpu_kern_alloc_ctx(u_int flags) 1033 { 1034 struct fpu_kern_ctx *res; 1035 size_t sz; 1036 1037 sz = sizeof(struct fpu_kern_ctx) + XSAVE_AREA_ALIGN + 1038 cpu_max_ext_state_size; 1039 res = malloc(sz, M_FPUKERN_CTX, ((flags & FPU_KERN_NOWAIT) ? 1040 M_NOWAIT : M_WAITOK) | M_ZERO); 1041 return (res); 1042 } 1043 1044 void 1045 fpu_kern_free_ctx(struct fpu_kern_ctx *ctx) 1046 { 1047 1048 KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) == 0, ("free'ing inuse ctx")); 1049 /* XXXKIB clear the memory ? */ 1050 free(ctx, M_FPUKERN_CTX); 1051 } 1052 1053 static struct savefpu * 1054 fpu_kern_ctx_savefpu(struct fpu_kern_ctx *ctx) 1055 { 1056 vm_offset_t p; 1057 1058 p = (vm_offset_t)&ctx->hwstate1; 1059 p = roundup2(p, XSAVE_AREA_ALIGN); 1060 return ((struct savefpu *)p); 1061 } 1062 1063 void 1064 fpu_kern_enter(struct thread *td, struct fpu_kern_ctx *ctx, u_int flags) 1065 { 1066 struct pcb *pcb; 1067 1068 pcb = td->td_pcb; 1069 KASSERT((flags & FPU_KERN_NOCTX) != 0 || ctx != NULL, 1070 ("ctx is required when !FPU_KERN_NOCTX")); 1071 KASSERT(ctx == NULL || (ctx->flags & FPU_KERN_CTX_INUSE) == 0, 1072 ("using inuse ctx")); 1073 KASSERT((pcb->pcb_flags & PCB_FPUNOSAVE) == 0, 1074 ("recursive fpu_kern_enter while in PCB_FPUNOSAVE state")); 1075 1076 if ((flags & FPU_KERN_NOCTX) != 0) { 1077 critical_enter(); 1078 stop_emulating(); 1079 if (curthread == PCPU_GET(fpcurthread)) { 1080 fpusave(curpcb->pcb_save); 1081 PCPU_SET(fpcurthread, NULL); 1082 } else { 1083 KASSERT(PCPU_GET(fpcurthread) == NULL, 1084 ("invalid fpcurthread")); 1085 } 1086 1087 /* 1088 * This breaks XSAVEOPT tracker, but 1089 * PCB_FPUNOSAVE state is supposed to never need to 1090 * save FPU context at all. 1091 */ 1092 fpurestore(fpu_initialstate); 1093 set_pcb_flags(pcb, PCB_KERNFPU | PCB_FPUNOSAVE | 1094 PCB_FPUINITDONE); 1095 return; 1096 } 1097 if ((flags & FPU_KERN_KTHR) != 0 && is_fpu_kern_thread(0)) { 1098 ctx->flags = FPU_KERN_CTX_DUMMY | FPU_KERN_CTX_INUSE; 1099 return; 1100 } 1101 critical_enter(); 1102 KASSERT(!PCB_USER_FPU(pcb) || pcb->pcb_save == 1103 get_pcb_user_save_pcb(pcb), ("mangled pcb_save")); 1104 ctx->flags = FPU_KERN_CTX_INUSE; 1105 if ((pcb->pcb_flags & PCB_FPUINITDONE) != 0) 1106 ctx->flags |= FPU_KERN_CTX_FPUINITDONE; 1107 fpuexit(td); 1108 ctx->prev = pcb->pcb_save; 1109 pcb->pcb_save = fpu_kern_ctx_savefpu(ctx); 1110 set_pcb_flags(pcb, PCB_KERNFPU); 1111 clear_pcb_flags(pcb, PCB_FPUINITDONE); 1112 critical_exit(); 1113 } 1114 1115 int 1116 fpu_kern_leave(struct thread *td, struct fpu_kern_ctx *ctx) 1117 { 1118 struct pcb *pcb; 1119 1120 pcb = td->td_pcb; 1121 1122 if ((pcb->pcb_flags & PCB_FPUNOSAVE) != 0) { 1123 KASSERT(ctx == NULL, ("non-null ctx after FPU_KERN_NOCTX")); 1124 KASSERT(PCPU_GET(fpcurthread) == NULL, 1125 ("non-NULL fpcurthread for PCB_FPUNOSAVE")); 1126 CRITICAL_ASSERT(td); 1127 1128 clear_pcb_flags(pcb, PCB_FPUNOSAVE | PCB_FPUINITDONE); 1129 start_emulating(); 1130 } else { 1131 KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) != 0, 1132 ("leaving not inuse ctx")); 1133 ctx->flags &= ~FPU_KERN_CTX_INUSE; 1134 1135 if (is_fpu_kern_thread(0) && 1136 (ctx->flags & FPU_KERN_CTX_DUMMY) != 0) 1137 return (0); 1138 KASSERT((ctx->flags & FPU_KERN_CTX_DUMMY) == 0, 1139 ("dummy ctx")); 1140 critical_enter(); 1141 if (curthread == PCPU_GET(fpcurthread)) 1142 fpudrop(); 1143 pcb->pcb_save = ctx->prev; 1144 } 1145 1146 if (pcb->pcb_save == get_pcb_user_save_pcb(pcb)) { 1147 if ((pcb->pcb_flags & PCB_USERFPUINITDONE) != 0) { 1148 set_pcb_flags(pcb, PCB_FPUINITDONE); 1149 clear_pcb_flags(pcb, PCB_KERNFPU); 1150 } else 1151 clear_pcb_flags(pcb, PCB_FPUINITDONE | PCB_KERNFPU); 1152 } else { 1153 if ((ctx->flags & FPU_KERN_CTX_FPUINITDONE) != 0) 1154 set_pcb_flags(pcb, PCB_FPUINITDONE); 1155 else 1156 clear_pcb_flags(pcb, PCB_FPUINITDONE); 1157 KASSERT(!PCB_USER_FPU(pcb), ("unpaired fpu_kern_leave")); 1158 } 1159 critical_exit(); 1160 return (0); 1161 } 1162 1163 int 1164 fpu_kern_thread(u_int flags) 1165 { 1166 1167 KASSERT((curthread->td_pflags & TDP_KTHREAD) != 0, 1168 ("Only kthread may use fpu_kern_thread")); 1169 KASSERT(curpcb->pcb_save == get_pcb_user_save_pcb(curpcb), 1170 ("mangled pcb_save")); 1171 KASSERT(PCB_USER_FPU(curpcb), ("recursive call")); 1172 1173 set_pcb_flags(curpcb, PCB_KERNFPU); 1174 return (0); 1175 } 1176 1177 int 1178 is_fpu_kern_thread(u_int flags) 1179 { 1180 1181 if ((curthread->td_pflags & TDP_KTHREAD) == 0) 1182 return (0); 1183 return ((curpcb->pcb_flags & PCB_KERNFPU) != 0); 1184 } 1185 1186 /* 1187 * FPU save area alloc/free/init utility routines 1188 */ 1189 struct savefpu * 1190 fpu_save_area_alloc(void) 1191 { 1192 1193 return (uma_zalloc(fpu_save_area_zone, M_WAITOK)); 1194 } 1195 1196 void 1197 fpu_save_area_free(struct savefpu *fsa) 1198 { 1199 1200 uma_zfree(fpu_save_area_zone, fsa); 1201 } 1202 1203 void 1204 fpu_save_area_reset(struct savefpu *fsa) 1205 { 1206 1207 bcopy(fpu_initialstate, fsa, cpu_max_ext_state_size); 1208 } 1209