1 /*- 2 * Copyright (c) 1990 William Jolitz. 3 * Copyright (c) 1991 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by the University of 17 * California, Berkeley and its contributors. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 35 * $FreeBSD$ 36 */ 37 38 #include "opt_debug_npx.h" 39 #include "opt_math_emulate.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/bus.h> 44 #include <sys/kernel.h> 45 #include <sys/malloc.h> 46 #include <sys/module.h> 47 #include <sys/sysctl.h> 48 #include <sys/proc.h> 49 #include <machine/bus.h> 50 #include <sys/rman.h> 51 #ifdef NPX_DEBUG 52 #include <sys/syslog.h> 53 #endif 54 #include <sys/signalvar.h> 55 56 #ifndef SMP 57 #include <machine/asmacros.h> 58 #endif 59 #include <machine/cputypes.h> 60 #include <machine/frame.h> 61 #include <machine/ipl.h> 62 #include <machine/md_var.h> 63 #include <machine/pcb.h> 64 #include <machine/psl.h> 65 #ifndef SMP 66 #include <machine/clock.h> 67 #endif 68 #include <machine/resource.h> 69 #include <machine/specialreg.h> 70 #include <machine/segments.h> 71 72 #ifndef SMP 73 #include <i386/isa/icu.h> 74 #include <i386/isa/intr_machdep.h> 75 #include <i386/isa/isa.h> 76 #endif 77 78 /* 79 * 387 and 287 Numeric Coprocessor Extension (NPX) Driver. 80 */ 81 82 /* Configuration flags. */ 83 #define NPX_DISABLE_I586_OPTIMIZED_BCOPY (1 << 0) 84 #define NPX_DISABLE_I586_OPTIMIZED_BZERO (1 << 1) 85 #define NPX_DISABLE_I586_OPTIMIZED_COPYIO (1 << 2) 86 #define NPX_PREFER_EMULATOR (1 << 3) 87 88 #ifdef __GNUC__ 89 90 #define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr))) 91 #define fnclex() __asm("fnclex") 92 #define fninit() __asm("fninit") 93 #define fnop() __asm("fnop") 94 #define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr))) 95 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 96 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr))) 97 #define fp_divide_by_0() __asm("fldz; fld1; fdiv %st,%st(1); fnop") 98 #define frstor(addr) __asm("frstor %0" : : "m" (*(addr))) 99 #define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \ 100 : : "n" (CR0_TS) : "ax") 101 #define stop_emulating() __asm("clts") 102 103 #else /* not __GNUC__ */ 104 105 void fldcw __P((caddr_t addr)); 106 void fnclex __P((void)); 107 void fninit __P((void)); 108 void fnop __P((void)); 109 void fnsave __P((caddr_t addr)); 110 void fnstcw __P((caddr_t addr)); 111 void fnstsw __P((caddr_t addr)); 112 void fp_divide_by_0 __P((void)); 113 void frstor __P((caddr_t addr)); 114 void start_emulating __P((void)); 115 void stop_emulating __P((void)); 116 117 #endif /* __GNUC__ */ 118 119 typedef u_char bool_t; 120 121 static int npx_attach __P((device_t dev)); 122 void npx_intr __P((void *)); 123 static void npx_identify __P((driver_t *driver, device_t parent)); 124 static int npx_probe __P((device_t dev)); 125 static int npx_probe1 __P((device_t dev)); 126 #ifdef I586_CPU 127 static long timezero __P((const char *funcname, 128 void (*func)(void *buf, size_t len))); 129 #endif /* I586_CPU */ 130 131 int hw_float; /* XXX currently just alias for npx_exists */ 132 133 SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint, 134 CTLFLAG_RD, &hw_float, 0, 135 "Floatingpoint instructions executed in hardware"); 136 137 #ifndef SMP 138 static u_int npx0_imask = SWI_CLOCK_MASK; 139 static struct gate_descriptor npx_idt_probeintr; 140 static int npx_intrno; 141 static volatile u_int npx_intrs_while_probing; 142 static volatile u_int npx_traps_while_probing; 143 #endif 144 145 static bool_t npx_ex16; 146 static bool_t npx_exists; 147 static bool_t npx_irq13; 148 static int npx_irq; /* irq number */ 149 150 #ifndef SMP 151 /* 152 * Special interrupt handlers. Someday intr0-intr15 will be used to count 153 * interrupts. We'll still need a special exception 16 handler. The busy 154 * latch stuff in probeintr() can be moved to npxprobe(). 155 */ 156 inthand_t probeintr; 157 __asm(" \n\ 158 .text \n\ 159 .p2align 2,0x90 \n\ 160 .type " __XSTRING(CNAME(probeintr)) ",@function \n\ 161 " __XSTRING(CNAME(probeintr)) ": \n\ 162 ss \n\ 163 incl " __XSTRING(CNAME(npx_intrs_while_probing)) " \n\ 164 pushl %eax \n\ 165 movb $0x20,%al # EOI (asm in strings loses cpp features) \n\ 166 outb %al,$0xa0 # IO_ICU2 \n\ 167 outb %al,$0x20 # IO_ICU1 \n\ 168 movb $0,%al \n\ 169 outb %al,$0xf0 # clear BUSY# latch \n\ 170 popl %eax \n\ 171 iret \n\ 172 "); 173 174 inthand_t probetrap; 175 __asm(" \n\ 176 .text \n\ 177 .p2align 2,0x90 \n\ 178 .type " __XSTRING(CNAME(probetrap)) ",@function \n\ 179 " __XSTRING(CNAME(probetrap)) ": \n\ 180 ss \n\ 181 incl " __XSTRING(CNAME(npx_traps_while_probing)) " \n\ 182 fnclex \n\ 183 iret \n\ 184 "); 185 #endif /* SMP */ 186 187 /* 188 * Identify routine. Create a connection point on our parent for probing. 189 */ 190 static void 191 npx_identify(driver, parent) 192 driver_t *driver; 193 device_t parent; 194 { 195 device_t child; 196 197 child = BUS_ADD_CHILD(parent, 0, "npx", 0); 198 if (child == NULL) 199 panic("npx_identify"); 200 } 201 202 /* 203 * Probe routine. Initialize cr0 to give correct behaviour for [f]wait 204 * whether the device exists or not (XXX should be elsewhere). Set flags 205 * to tell npxattach() what to do. Modify device struct if npx doesn't 206 * need to use interrupts. Return 1 if device exists. 207 */ 208 static int 209 npx_probe(dev) 210 device_t dev; 211 { 212 #ifdef SMP 213 214 if (resource_int_value("npx", 0, "irq", &npx_irq) != 0) 215 npx_irq = 13; 216 return npx_probe1(dev); 217 218 #else /* SMP */ 219 220 int result; 221 u_long save_eflags; 222 u_char save_icu1_mask; 223 u_char save_icu2_mask; 224 struct gate_descriptor save_idt_npxintr; 225 struct gate_descriptor save_idt_npxtrap; 226 /* 227 * This routine is now just a wrapper for npxprobe1(), to install 228 * special npx interrupt and trap handlers, to enable npx interrupts 229 * and to disable other interrupts. Someday isa_configure() will 230 * install suitable handlers and run with interrupts enabled so we 231 * won't need to do so much here. 232 */ 233 if (resource_int_value("npx", 0, "irq", &npx_irq) != 0) 234 npx_irq = 13; 235 npx_intrno = NRSVIDT + npx_irq; 236 save_eflags = read_eflags(); 237 disable_intr(); 238 save_icu1_mask = inb(IO_ICU1 + 1); 239 save_icu2_mask = inb(IO_ICU2 + 1); 240 save_idt_npxintr = idt[npx_intrno]; 241 save_idt_npxtrap = idt[16]; 242 outb(IO_ICU1 + 1, ~IRQ_SLAVE); 243 outb(IO_ICU2 + 1, ~(1 << (npx_irq - 8))); 244 setidt(16, probetrap, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 245 setidt(npx_intrno, probeintr, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 246 npx_idt_probeintr = idt[npx_intrno]; 247 enable_intr(); 248 result = npx_probe1(dev); 249 disable_intr(); 250 outb(IO_ICU1 + 1, save_icu1_mask); 251 outb(IO_ICU2 + 1, save_icu2_mask); 252 idt[npx_intrno] = save_idt_npxintr; 253 idt[16] = save_idt_npxtrap; 254 write_eflags(save_eflags); 255 return (result); 256 257 #endif /* SMP */ 258 } 259 260 static int 261 npx_probe1(dev) 262 device_t dev; 263 { 264 #ifndef SMP 265 u_short control; 266 u_short status; 267 #endif 268 269 /* 270 * Partially reset the coprocessor, if any. Some BIOS's don't reset 271 * it after a warm boot. 272 */ 273 outb(0xf1, 0); /* full reset on some systems, NOP on others */ 274 outb(0xf0, 0); /* clear BUSY# latch */ 275 /* 276 * Prepare to trap all ESC (i.e., NPX) instructions and all WAIT 277 * instructions. We must set the CR0_MP bit and use the CR0_TS 278 * bit to control the trap, because setting the CR0_EM bit does 279 * not cause WAIT instructions to trap. It's important to trap 280 * WAIT instructions - otherwise the "wait" variants of no-wait 281 * control instructions would degenerate to the "no-wait" variants 282 * after FP context switches but work correctly otherwise. It's 283 * particularly important to trap WAITs when there is no NPX - 284 * otherwise the "wait" variants would always degenerate. 285 * 286 * Try setting CR0_NE to get correct error reporting on 486DX's. 287 * Setting it should fail or do nothing on lesser processors. 288 */ 289 load_cr0(rcr0() | CR0_MP | CR0_NE); 290 /* 291 * But don't trap while we're probing. 292 */ 293 stop_emulating(); 294 /* 295 * Finish resetting the coprocessor, if any. If there is an error 296 * pending, then we may get a bogus IRQ13, but probeintr() will handle 297 * it OK. Bogus halts have never been observed, but we enabled 298 * IRQ13 and cleared the BUSY# latch early to handle them anyway. 299 */ 300 fninit(); 301 302 #ifdef SMP 303 /* 304 * Exception 16 MUST work for SMP. 305 */ 306 npx_irq13 = 0; 307 npx_ex16 = hw_float = npx_exists = 1; 308 device_set_desc(dev, "math processor"); 309 return (0); 310 311 #else /* !SMP */ 312 device_set_desc(dev, "math processor"); 313 314 /* 315 * Don't use fwait here because it might hang. 316 * Don't use fnop here because it usually hangs if there is no FPU. 317 */ 318 DELAY(1000); /* wait for any IRQ13 */ 319 #ifdef DIAGNOSTIC 320 if (npx_intrs_while_probing != 0) 321 printf("fninit caused %u bogus npx interrupt(s)\n", 322 npx_intrs_while_probing); 323 if (npx_traps_while_probing != 0) 324 printf("fninit caused %u bogus npx trap(s)\n", 325 npx_traps_while_probing); 326 #endif 327 /* 328 * Check for a status of mostly zero. 329 */ 330 status = 0x5a5a; 331 fnstsw(&status); 332 if ((status & 0xb8ff) == 0) { 333 /* 334 * Good, now check for a proper control word. 335 */ 336 control = 0x5a5a; 337 fnstcw(&control); 338 if ((control & 0x1f3f) == 0x033f) { 339 hw_float = npx_exists = 1; 340 /* 341 * We have an npx, now divide by 0 to see if exception 342 * 16 works. 343 */ 344 control &= ~(1 << 2); /* enable divide by 0 trap */ 345 fldcw(&control); 346 npx_traps_while_probing = npx_intrs_while_probing = 0; 347 fp_divide_by_0(); 348 if (npx_traps_while_probing != 0) { 349 /* 350 * Good, exception 16 works. 351 */ 352 npx_ex16 = 1; 353 return (0); 354 } 355 if (npx_intrs_while_probing != 0) { 356 int rid; 357 struct resource *r; 358 void *intr; 359 /* 360 * Bad, we are stuck with IRQ13. 361 */ 362 npx_irq13 = 1; 363 /* 364 * npxattach would be too late to set npx0_imask 365 */ 366 npx0_imask |= (1 << npx_irq); 367 368 /* 369 * We allocate these resources permanently, 370 * so there is no need to keep track of them. 371 */ 372 rid = 0; 373 r = bus_alloc_resource(dev, SYS_RES_IOPORT, 374 &rid, IO_NPX, IO_NPX, 375 IO_NPXSIZE, RF_ACTIVE); 376 if (r == 0) 377 panic("npx: can't get ports"); 378 rid = 0; 379 r = bus_alloc_resource(dev, SYS_RES_IRQ, 380 &rid, npx_irq, npx_irq, 381 1, RF_ACTIVE); 382 if (r == 0) 383 panic("npx: can't get IRQ"); 384 BUS_SETUP_INTR(device_get_parent(dev), 385 dev, r, INTR_TYPE_MISC, 386 npx_intr, 0, &intr); 387 if (intr == 0) 388 panic("npx: can't create intr"); 389 390 return (0); 391 } 392 /* 393 * Worse, even IRQ13 is broken. Use emulator. 394 */ 395 } 396 } 397 /* 398 * Probe failed, but we want to get to npxattach to initialize the 399 * emulator and say that it has been installed. XXX handle devices 400 * that aren't really devices better. 401 */ 402 return (0); 403 #endif /* SMP */ 404 } 405 406 /* 407 * Attach routine - announce which it is, and wire into system 408 */ 409 int 410 npx_attach(dev) 411 device_t dev; 412 { 413 int flags; 414 415 if (resource_int_value("npx", 0, "flags", &flags) != 0) 416 flags = 0; 417 418 if (flags) 419 device_printf(dev, "flags 0x%x ", flags); 420 if (npx_irq13) { 421 device_printf(dev, "using IRQ 13 interface\n"); 422 } else { 423 #if defined(MATH_EMULATE) || defined(GPL_MATH_EMULATE) 424 if (npx_ex16) { 425 if (!(flags & NPX_PREFER_EMULATOR)) 426 device_printf(dev, "INT 16 interface\n"); 427 else { 428 device_printf(dev, "FPU exists, but flags request " 429 "emulator\n"); 430 hw_float = npx_exists = 0; 431 } 432 } else if (npx_exists) { 433 device_printf(dev, "error reporting broken; using 387 emulator\n"); 434 hw_float = npx_exists = 0; 435 } else 436 device_printf(dev, "387 emulator\n"); 437 #else 438 if (npx_ex16) { 439 device_printf(dev, "INT 16 interface\n"); 440 if (flags & NPX_PREFER_EMULATOR) { 441 device_printf(dev, "emulator requested, but none compiled " 442 "into kernel, using FPU\n"); 443 } 444 } else 445 device_printf(dev, "no 387 emulator in kernel and no FPU!\n"); 446 #endif 447 } 448 npxinit(__INITIAL_NPXCW__); 449 450 #ifdef I586_CPU 451 if (cpu_class == CPUCLASS_586 && npx_ex16 && npx_exists && 452 timezero("i586_bzero()", i586_bzero) < 453 timezero("bzero()", bzero) * 4 / 5) { 454 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY)) { 455 bcopy_vector = i586_bcopy; 456 ovbcopy_vector = i586_bcopy; 457 } 458 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BZERO)) 459 bzero = i586_bzero; 460 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_COPYIO)) { 461 copyin_vector = i586_copyin; 462 copyout_vector = i586_copyout; 463 } 464 } 465 #endif 466 467 return (0); /* XXX unused */ 468 } 469 470 /* 471 * Initialize floating point unit. 472 */ 473 void 474 npxinit(control) 475 u_short control; 476 { 477 struct save87 dummy; 478 479 if (!npx_exists) 480 return; 481 /* 482 * fninit has the same h/w bugs as fnsave. Use the detoxified 483 * fnsave to throw away any junk in the fpu. npxsave() initializes 484 * the fpu and sets npxproc = NULL as important side effects. 485 */ 486 npxsave(&dummy); 487 stop_emulating(); 488 fldcw(&control); 489 if (curpcb != NULL) 490 fnsave(&curpcb->pcb_savefpu); 491 start_emulating(); 492 } 493 494 /* 495 * Free coprocessor (if we have it). 496 */ 497 void 498 npxexit(p) 499 struct proc *p; 500 { 501 502 if (p == npxproc) 503 npxsave(&curpcb->pcb_savefpu); 504 #ifdef NPX_DEBUG 505 if (npx_exists) { 506 u_int masked_exceptions; 507 508 masked_exceptions = curpcb->pcb_savefpu.sv_env.en_cw 509 & curpcb->pcb_savefpu.sv_env.en_sw & 0x7f; 510 /* 511 * Log exceptions that would have trapped with the old 512 * control word (overflow, divide by 0, and invalid operand). 513 */ 514 if (masked_exceptions & 0x0d) 515 log(LOG_ERR, 516 "pid %d (%s) exited with masked floating point exceptions 0x%02x\n", 517 p->p_pid, p->p_comm, masked_exceptions); 518 } 519 #endif 520 } 521 522 /* 523 * The following mechanism is used to ensure that the FPE_... value 524 * that is passed as a trapcode to the signal handler of the user 525 * process does not have more than one bit set. 526 * 527 * Multiple bits may be set if the user process modifies the control 528 * word while a status word bit is already set. While this is a sign 529 * of bad coding, we have no choise than to narrow them down to one 530 * bit, since we must not send a trapcode that is not exactly one of 531 * the FPE_ macros. 532 * 533 * The mechanism has a static table with 127 entries. Each combination 534 * of the 7 FPU status word exception bits directly translates to a 535 * position in this table, where a single FPE_... value is stored. 536 * This FPE_... value stored there is considered the "most important" 537 * of the exception bits and will be sent as the signal code. The 538 * precedence of the bits is based upon Intel Document "Numerical 539 * Applications", Chapter "Special Computational Situations". 540 * 541 * The macro to choose one of these values does these steps: 1) Throw 542 * away status word bits that cannot be masked. 2) Throw away the bits 543 * currently masked in the control word, assuming the user isn't 544 * interested in them anymore. 3) Reinsert status word bit 7 (stack 545 * fault) if it is set, which cannot be masked but must be presered. 546 * 4) Use the remaining bits to point into the trapcode table. 547 * 548 * The 6 maskable bits in order of their preference, as stated in the 549 * above referenced Intel manual: 550 * 1 Invalid operation (FP_X_INV) 551 * 1a Stack underflow 552 * 1b Stack overflow 553 * 1c Operand of unsupported format 554 * 1d SNaN operand. 555 * 2 QNaN operand (not an exception, irrelavant here) 556 * 3 Any other invalid-operation not mentioned above or zero divide 557 * (FP_X_INV, FP_X_DZ) 558 * 4 Denormal operand (FP_X_DNML) 559 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 560 * 6 Inexact result (FP_X_IMP) 561 */ 562 static char fpetable[128] = { 563 0, 564 FPE_FLTINV, /* 1 - INV */ 565 FPE_FLTUND, /* 2 - DNML */ 566 FPE_FLTINV, /* 3 - INV | DNML */ 567 FPE_FLTDIV, /* 4 - DZ */ 568 FPE_FLTINV, /* 5 - INV | DZ */ 569 FPE_FLTDIV, /* 6 - DNML | DZ */ 570 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 571 FPE_FLTOVF, /* 8 - OFL */ 572 FPE_FLTINV, /* 9 - INV | OFL */ 573 FPE_FLTUND, /* A - DNML | OFL */ 574 FPE_FLTINV, /* B - INV | DNML | OFL */ 575 FPE_FLTDIV, /* C - DZ | OFL */ 576 FPE_FLTINV, /* D - INV | DZ | OFL */ 577 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 578 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 579 FPE_FLTUND, /* 10 - UFL */ 580 FPE_FLTINV, /* 11 - INV | UFL */ 581 FPE_FLTUND, /* 12 - DNML | UFL */ 582 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 583 FPE_FLTDIV, /* 14 - DZ | UFL */ 584 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 585 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 586 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 587 FPE_FLTOVF, /* 18 - OFL | UFL */ 588 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 589 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 590 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 591 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 592 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 593 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 594 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 595 FPE_FLTRES, /* 20 - IMP */ 596 FPE_FLTINV, /* 21 - INV | IMP */ 597 FPE_FLTUND, /* 22 - DNML | IMP */ 598 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 599 FPE_FLTDIV, /* 24 - DZ | IMP */ 600 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 601 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 602 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 603 FPE_FLTOVF, /* 28 - OFL | IMP */ 604 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 605 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 606 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 607 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 608 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 609 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 610 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 611 FPE_FLTUND, /* 30 - UFL | IMP */ 612 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 613 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 614 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 615 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 616 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 617 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 618 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 619 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 620 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 621 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 622 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 623 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 624 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 625 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 626 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 627 FPE_FLTSUB, /* 40 - STK */ 628 FPE_FLTSUB, /* 41 - INV | STK */ 629 FPE_FLTUND, /* 42 - DNML | STK */ 630 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 631 FPE_FLTDIV, /* 44 - DZ | STK */ 632 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 633 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 634 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 635 FPE_FLTOVF, /* 48 - OFL | STK */ 636 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 637 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 638 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 639 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 640 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 641 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 642 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 643 FPE_FLTUND, /* 50 - UFL | STK */ 644 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 645 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 646 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 647 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 648 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 649 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 650 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 651 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 652 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 653 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 654 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 655 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 656 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 657 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 658 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 659 FPE_FLTRES, /* 60 - IMP | STK */ 660 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 661 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 662 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 663 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 664 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 665 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 666 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 667 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 668 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 669 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 670 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 671 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 672 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 673 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 674 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 675 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 676 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 677 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 678 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 679 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 680 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 681 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 682 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 683 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 684 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 685 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 686 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 687 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 688 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 689 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 690 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 691 }; 692 693 /* 694 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE. 695 * 696 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now 697 * depend on longjmp() restoring a usable state. Restoring the state 698 * or examining it might fail if we didn't clear exceptions. 699 * 700 * The error code chosen will be one of the FPE_... macros. It will be 701 * sent as the second argument to old BSD-style signal handlers and as 702 * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers. 703 * 704 * XXX the FP state is not preserved across signal handlers. So signal 705 * handlers cannot afford to do FP unless they preserve the state or 706 * longjmp() out. Both preserving the state and longjmp()ing may be 707 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable 708 * solution for signals other than SIGFPE. 709 */ 710 void 711 npx_intr(dummy) 712 void *dummy; 713 { 714 int code; 715 u_short control; 716 struct intrframe *frame; 717 718 if (npxproc == NULL || !npx_exists) { 719 printf("npxintr: npxproc = %p, curproc = %p, npx_exists = %d\n", 720 npxproc, curproc, npx_exists); 721 panic("npxintr from nowhere"); 722 } 723 if (npxproc != curproc) { 724 printf("npxintr: npxproc = %p, curproc = %p, npx_exists = %d\n", 725 npxproc, curproc, npx_exists); 726 panic("npxintr from non-current process"); 727 } 728 729 outb(0xf0, 0); 730 fnstsw(&curpcb->pcb_savefpu.sv_ex_sw); 731 fnstcw(&control); 732 fnclex(); 733 734 /* 735 * Pass exception to process. 736 */ 737 frame = (struct intrframe *)&dummy; /* XXX */ 738 if ((ISPL(frame->if_cs) == SEL_UPL) || (frame->if_eflags & PSL_VM)) { 739 /* 740 * Interrupt is essentially a trap, so we can afford to call 741 * the SIGFPE handler (if any) as soon as the interrupt 742 * returns. 743 * 744 * XXX little or nothing is gained from this, and plenty is 745 * lost - the interrupt frame has to contain the trap frame 746 * (this is otherwise only necessary for the rescheduling trap 747 * in doreti, and the frame for that could easily be set up 748 * just before it is used). 749 */ 750 curproc->p_md.md_regs = INTR_TO_TRAPFRAME(frame); 751 /* 752 * Encode the appropriate code for detailed information on 753 * this exception. 754 */ 755 code = 756 fpetable[(curpcb->pcb_savefpu.sv_ex_sw & ~control & 0x3f) | 757 (curpcb->pcb_savefpu.sv_ex_sw & 0x40)]; 758 trapsignal(curproc, SIGFPE, code); 759 } else { 760 /* 761 * Nested interrupt. These losers occur when: 762 * o an IRQ13 is bogusly generated at a bogus time, e.g.: 763 * o immediately after an fnsave or frstor of an 764 * error state. 765 * o a couple of 386 instructions after 766 * "fstpl _memvar" causes a stack overflow. 767 * These are especially nasty when combined with a 768 * trace trap. 769 * o an IRQ13 occurs at the same time as another higher- 770 * priority interrupt. 771 * 772 * Treat them like a true async interrupt. 773 */ 774 psignal(curproc, SIGFPE); 775 } 776 } 777 778 /* 779 * Implement device not available (DNA) exception 780 * 781 * It would be better to switch FP context here (if curproc != npxproc) 782 * and not necessarily for every context switch, but it is too hard to 783 * access foreign pcb's. 784 */ 785 int 786 npxdna() 787 { 788 if (!npx_exists) 789 return (0); 790 if (npxproc != NULL) { 791 printf("npxdna: npxproc = %p, curproc = %p\n", 792 npxproc, curproc); 793 panic("npxdna"); 794 } 795 stop_emulating(); 796 /* 797 * Record new context early in case frstor causes an IRQ13. 798 */ 799 npxproc = curproc; 800 curpcb->pcb_savefpu.sv_ex_sw = 0; 801 /* 802 * The following frstor may cause an IRQ13 when the state being 803 * restored has a pending error. The error will appear to have been 804 * triggered by the current (npx) user instruction even when that 805 * instruction is a no-wait instruction that should not trigger an 806 * error (e.g., fnclex). On at least one 486 system all of the 807 * no-wait instructions are broken the same as frstor, so our 808 * treatment does not amplify the breakage. On at least one 809 * 386/Cyrix 387 system, fnclex works correctly while frstor and 810 * fnsave are broken, so our treatment breaks fnclex if it is the 811 * first FPU instruction after a context switch. 812 */ 813 frstor(&curpcb->pcb_savefpu); 814 815 return (1); 816 } 817 818 /* 819 * Wrapper for fnsave instruction to handle h/w bugs. If there is an error 820 * pending, then fnsave generates a bogus IRQ13 on some systems. Force 821 * any IRQ13 to be handled immediately, and then ignore it. This routine is 822 * often called at splhigh so it must not use many system services. In 823 * particular, it's much easier to install a special handler than to 824 * guarantee that it's safe to use npxintr() and its supporting code. 825 */ 826 void 827 npxsave(addr) 828 struct save87 *addr; 829 { 830 #ifdef SMP 831 832 stop_emulating(); 833 fnsave(addr); 834 /* fnop(); */ 835 start_emulating(); 836 npxproc = NULL; 837 838 #else /* SMP */ 839 840 u_char icu1_mask; 841 u_char icu2_mask; 842 u_char old_icu1_mask; 843 u_char old_icu2_mask; 844 struct gate_descriptor save_idt_npxintr; 845 846 disable_intr(); 847 old_icu1_mask = inb(IO_ICU1 + 1); 848 old_icu2_mask = inb(IO_ICU2 + 1); 849 save_idt_npxintr = idt[npx_intrno]; 850 outb(IO_ICU1 + 1, old_icu1_mask & ~(IRQ_SLAVE | npx0_imask)); 851 outb(IO_ICU2 + 1, old_icu2_mask & ~(npx0_imask >> 8)); 852 idt[npx_intrno] = npx_idt_probeintr; 853 enable_intr(); 854 stop_emulating(); 855 fnsave(addr); 856 fnop(); 857 start_emulating(); 858 npxproc = NULL; 859 disable_intr(); 860 icu1_mask = inb(IO_ICU1 + 1); /* masks may have changed */ 861 icu2_mask = inb(IO_ICU2 + 1); 862 outb(IO_ICU1 + 1, 863 (icu1_mask & ~npx0_imask) | (old_icu1_mask & npx0_imask)); 864 outb(IO_ICU2 + 1, 865 (icu2_mask & ~(npx0_imask >> 8)) 866 | (old_icu2_mask & (npx0_imask >> 8))); 867 idt[npx_intrno] = save_idt_npxintr; 868 enable_intr(); /* back to usual state */ 869 870 #endif /* SMP */ 871 } 872 873 #ifdef I586_CPU 874 static long 875 timezero(funcname, func) 876 const char *funcname; 877 void (*func) __P((void *buf, size_t len)); 878 879 { 880 void *buf; 881 #define BUFSIZE 1000000 882 long usec; 883 struct timeval finish, start; 884 885 buf = malloc(BUFSIZE, M_TEMP, M_NOWAIT); 886 if (buf == NULL) 887 return (BUFSIZE); 888 microtime(&start); 889 (*func)(buf, BUFSIZE); 890 microtime(&finish); 891 usec = 1000000 * (finish.tv_sec - start.tv_sec) + 892 finish.tv_usec - start.tv_usec; 893 if (usec <= 0) 894 usec = 1; 895 if (bootverbose) 896 printf("%s bandwidth = %ld bytes/sec\n", 897 funcname, (long)(BUFSIZE * (int64_t)1000000 / usec)); 898 free(buf, M_TEMP); 899 return (usec); 900 } 901 #endif /* I586_CPU */ 902 903 static device_method_t npx_methods[] = { 904 /* Device interface */ 905 DEVMETHOD(device_identify, npx_identify), 906 DEVMETHOD(device_probe, npx_probe), 907 DEVMETHOD(device_attach, npx_attach), 908 DEVMETHOD(device_detach, bus_generic_detach), 909 DEVMETHOD(device_shutdown, bus_generic_shutdown), 910 DEVMETHOD(device_suspend, bus_generic_suspend), 911 DEVMETHOD(device_resume, bus_generic_resume), 912 913 { 0, 0 } 914 }; 915 916 static driver_t npx_driver = { 917 "npx", 918 npx_methods, 919 1, /* no softc */ 920 }; 921 922 static devclass_t npx_devclass; 923 924 /* 925 * We prefer to attach to the root nexus so that the usual case (exception 16) 926 * doesn't describe the processor as being `on isa'. 927 */ 928 DRIVER_MODULE(npx, nexus, npx_driver, npx_devclass, 0, 0); 929