1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 1990 William Jolitz. 5 * Copyright (c) 1991 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of the University nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/domainset.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/module.h> 41 #include <sys/mutex.h> 42 #include <sys/mutex.h> 43 #include <sys/proc.h> 44 #include <sys/sysctl.h> 45 #include <sys/sysent.h> 46 #include <sys/tslog.h> 47 #include <machine/bus.h> 48 #include <sys/rman.h> 49 #include <sys/signalvar.h> 50 #include <vm/uma.h> 51 52 #include <machine/cputypes.h> 53 #include <machine/frame.h> 54 #include <machine/intr_machdep.h> 55 #include <machine/md_var.h> 56 #include <machine/pcb.h> 57 #include <machine/psl.h> 58 #include <machine/resource.h> 59 #include <machine/specialreg.h> 60 #include <machine/segments.h> 61 #include <machine/ucontext.h> 62 #include <x86/ifunc.h> 63 64 /* 65 * Floating point support. 66 */ 67 68 #define fldcw(cw) __asm __volatile("fldcw %0" : : "m" (cw)) 69 #define fnclex() __asm __volatile("fnclex") 70 #define fninit() __asm __volatile("fninit") 71 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 72 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=am" (*(addr))) 73 #define fxrstor(addr) __asm __volatile("fxrstor %0" : : "m" (*(addr))) 74 #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 75 #define ldmxcsr(csr) __asm __volatile("ldmxcsr %0" : : "m" (csr)) 76 #define stmxcsr(addr) __asm __volatile("stmxcsr %0" : "=m" (*(addr))) 77 78 static __inline void 79 xrstor32(char *addr, uint64_t mask) 80 { 81 uint32_t low, hi; 82 83 low = mask; 84 hi = mask >> 32; 85 __asm __volatile("xrstor %0" : : "m" (*addr), "a" (low), "d" (hi)); 86 } 87 88 static __inline void 89 xrstor64(char *addr, uint64_t mask) 90 { 91 uint32_t low, hi; 92 93 low = mask; 94 hi = mask >> 32; 95 __asm __volatile("xrstor64 %0" : : "m" (*addr), "a" (low), "d" (hi)); 96 } 97 98 static __inline void 99 xsave32(char *addr, uint64_t mask) 100 { 101 uint32_t low, hi; 102 103 low = mask; 104 hi = mask >> 32; 105 __asm __volatile("xsave %0" : "=m" (*addr) : "a" (low), "d" (hi) : 106 "memory"); 107 } 108 109 static __inline void 110 xsave64(char *addr, uint64_t mask) 111 { 112 uint32_t low, hi; 113 114 low = mask; 115 hi = mask >> 32; 116 __asm __volatile("xsave64 %0" : "=m" (*addr) : "a" (low), "d" (hi) : 117 "memory"); 118 } 119 120 static __inline void 121 xsaveopt32(char *addr, uint64_t mask) 122 { 123 uint32_t low, hi; 124 125 low = mask; 126 hi = mask >> 32; 127 __asm __volatile("xsaveopt %0" : "=m" (*addr) : "a" (low), "d" (hi) : 128 "memory"); 129 } 130 131 static __inline void 132 xsaveopt64(char *addr, uint64_t mask) 133 { 134 uint32_t low, hi; 135 136 low = mask; 137 hi = mask >> 32; 138 __asm __volatile("xsaveopt64 %0" : "=m" (*addr) : "a" (low), "d" (hi) : 139 "memory"); 140 } 141 142 CTASSERT(sizeof(struct savefpu) == 512); 143 CTASSERT(sizeof(struct xstate_hdr) == 64); 144 CTASSERT(sizeof(struct savefpu_ymm) == 832); 145 146 /* 147 * This requirement is to make it easier for asm code to calculate 148 * offset of the fpu save area from the pcb address. FPU save area 149 * must be 64-byte aligned. 150 */ 151 CTASSERT(sizeof(struct pcb) % XSAVE_AREA_ALIGN == 0); 152 153 /* 154 * Ensure the copy of XCR0 saved in a core is contained in the padding 155 * area. 156 */ 157 CTASSERT(X86_XSTATE_XCR0_OFFSET >= offsetof(struct savefpu, sv_pad) && 158 X86_XSTATE_XCR0_OFFSET + sizeof(uint64_t) <= sizeof(struct savefpu)); 159 160 static void fpu_clean_state(void); 161 162 SYSCTL_INT(_hw, HW_FLOATINGPT, floatingpoint, CTLFLAG_RD, 163 SYSCTL_NULL_INT_PTR, 1, "Floating point instructions executed in hardware"); 164 165 int use_xsave; /* non-static for cpu_switch.S */ 166 uint64_t xsave_mask; /* the same */ 167 static uma_zone_t fpu_save_area_zone; 168 static struct savefpu *fpu_initialstate; 169 170 static struct xsave_area_elm_descr { 171 u_int offset; 172 u_int size; 173 } *xsave_area_desc; 174 175 static void 176 fpusave_xsaveopt64(void *addr) 177 { 178 xsaveopt64((char *)addr, xsave_mask); 179 } 180 181 static void 182 fpusave_xsaveopt3264(void *addr) 183 { 184 if (SV_CURPROC_FLAG(SV_ILP32)) 185 xsaveopt32((char *)addr, xsave_mask); 186 else 187 xsaveopt64((char *)addr, xsave_mask); 188 } 189 190 static void 191 fpusave_xsave64(void *addr) 192 { 193 xsave64((char *)addr, xsave_mask); 194 } 195 196 static void 197 fpusave_xsave3264(void *addr) 198 { 199 if (SV_CURPROC_FLAG(SV_ILP32)) 200 xsave32((char *)addr, xsave_mask); 201 else 202 xsave64((char *)addr, xsave_mask); 203 } 204 205 static void 206 fpurestore_xrstor64(void *addr) 207 { 208 xrstor64((char *)addr, xsave_mask); 209 } 210 211 static void 212 fpurestore_xrstor3264(void *addr) 213 { 214 if (SV_CURPROC_FLAG(SV_ILP32)) 215 xrstor32((char *)addr, xsave_mask); 216 else 217 xrstor64((char *)addr, xsave_mask); 218 } 219 220 static void 221 fpusave_fxsave(void *addr) 222 { 223 224 fxsave((char *)addr); 225 } 226 227 static void 228 fpurestore_fxrstor(void *addr) 229 { 230 231 fxrstor((char *)addr); 232 } 233 234 DEFINE_IFUNC(, void, fpusave, (void *)) 235 { 236 if (!use_xsave) 237 return (fpusave_fxsave); 238 if ((cpu_stdext_feature & CPUID_EXTSTATE_XSAVEOPT) != 0) { 239 return ((cpu_stdext_feature & CPUID_STDEXT_NFPUSG) != 0 ? 240 fpusave_xsaveopt64 : fpusave_xsaveopt3264); 241 } 242 return ((cpu_stdext_feature & CPUID_STDEXT_NFPUSG) != 0 ? 243 fpusave_xsave64 : fpusave_xsave3264); 244 } 245 246 DEFINE_IFUNC(, void, fpurestore, (void *)) 247 { 248 if (!use_xsave) 249 return (fpurestore_fxrstor); 250 return ((cpu_stdext_feature & CPUID_STDEXT_NFPUSG) != 0 ? 251 fpurestore_xrstor64 : fpurestore_xrstor3264); 252 } 253 254 void 255 fpususpend(void *addr) 256 { 257 u_long cr0; 258 259 cr0 = rcr0(); 260 fpu_enable(); 261 fpusave(addr); 262 load_cr0(cr0); 263 } 264 265 void 266 fpuresume(void *addr) 267 { 268 u_long cr0; 269 270 cr0 = rcr0(); 271 fpu_enable(); 272 fninit(); 273 if (use_xsave) 274 load_xcr(XCR0, xsave_mask); 275 fpurestore(addr); 276 load_cr0(cr0); 277 } 278 279 /* 280 * Enable XSAVE if supported and allowed by user. 281 * Calculate the xsave_mask. 282 */ 283 static void 284 fpuinit_bsp1(void) 285 { 286 u_int cp[4]; 287 uint64_t xsave_mask_user; 288 bool old_wp; 289 290 if (!use_xsave) 291 return; 292 cpuid_count(0xd, 0x0, cp); 293 xsave_mask = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE; 294 if ((cp[0] & xsave_mask) != xsave_mask) 295 panic("CPU0 does not support X87 or SSE: %x", cp[0]); 296 xsave_mask = ((uint64_t)cp[3] << 32) | cp[0]; 297 xsave_mask_user = xsave_mask; 298 TUNABLE_ULONG_FETCH("hw.xsave_mask", &xsave_mask_user); 299 xsave_mask_user |= XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE; 300 xsave_mask &= xsave_mask_user; 301 if ((xsave_mask & XFEATURE_AVX512) != XFEATURE_AVX512) 302 xsave_mask &= ~XFEATURE_AVX512; 303 if ((xsave_mask & XFEATURE_MPX) != XFEATURE_MPX) 304 xsave_mask &= ~XFEATURE_MPX; 305 306 cpuid_count(0xd, 0x1, cp); 307 if ((cp[0] & CPUID_EXTSTATE_XSAVEOPT) != 0) { 308 /* 309 * Patch the XSAVE instruction in the cpu_switch code 310 * to XSAVEOPT. We assume that XSAVE encoding used 311 * REX byte, and set the bit 4 of the r/m byte. 312 * 313 * It seems that some BIOSes give control to the OS 314 * with CR0.WP already set, making the kernel text 315 * read-only before cpu_startup(). 316 */ 317 old_wp = disable_wp(); 318 ctx_switch_xsave32[3] |= 0x10; 319 ctx_switch_xsave[3] |= 0x10; 320 restore_wp(old_wp); 321 } 322 } 323 324 /* 325 * Calculate the fpu save area size. 326 */ 327 static void 328 fpuinit_bsp2(void) 329 { 330 u_int cp[4]; 331 332 if (use_xsave) { 333 cpuid_count(0xd, 0x0, cp); 334 cpu_max_ext_state_size = cp[1]; 335 336 /* 337 * Reload the cpu_feature2, since we enabled OSXSAVE. 338 */ 339 do_cpuid(1, cp); 340 cpu_feature2 = cp[2]; 341 } else 342 cpu_max_ext_state_size = sizeof(struct savefpu); 343 } 344 345 /* 346 * Initialize the floating point unit. 347 */ 348 void 349 fpuinit(void) 350 { 351 register_t saveintr; 352 uint64_t cr4; 353 u_int mxcsr; 354 u_short control; 355 356 TSENTER(); 357 if (IS_BSP()) 358 fpuinit_bsp1(); 359 360 if (use_xsave) { 361 cr4 = rcr4(); 362 363 /* 364 * Revert enablement of PKRU if user disabled its 365 * saving on context switches by clearing the bit in 366 * the xsave mask. Also redundantly clear the bit in 367 * cpu_stdext_feature2 to prevent pmap from ever 368 * trying to set the page table bits. 369 */ 370 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0 && 371 (xsave_mask & XFEATURE_ENABLED_PKRU) == 0) { 372 cr4 &= ~CR4_PKE; 373 cpu_stdext_feature2 &= ~CPUID_STDEXT2_PKU; 374 } 375 376 load_cr4(cr4 | CR4_XSAVE); 377 load_xcr(XCR0, xsave_mask); 378 } 379 380 /* 381 * XCR0 shall be set up before CPU can report the save area size. 382 */ 383 if (IS_BSP()) 384 fpuinit_bsp2(); 385 386 /* 387 * It is too early for critical_enter() to work on AP. 388 */ 389 saveintr = intr_disable(); 390 fpu_enable(); 391 fninit(); 392 control = __INITIAL_FPUCW__; 393 fldcw(control); 394 mxcsr = __INITIAL_MXCSR__; 395 ldmxcsr(mxcsr); 396 fpu_disable(); 397 intr_restore(saveintr); 398 TSEXIT(); 399 } 400 401 /* 402 * On the boot CPU we generate a clean state that is used to 403 * initialize the floating point unit when it is first used by a 404 * process. 405 */ 406 static void 407 fpuinitstate(void *arg __unused) 408 { 409 uint64_t *xstate_bv; 410 register_t saveintr; 411 int cp[4], i, max_ext_n; 412 413 /* Do potentially blocking operations before disabling interrupts. */ 414 fpu_save_area_zone = uma_zcreate("FPU_save_area", 415 cpu_max_ext_state_size, NULL, NULL, NULL, NULL, 416 XSAVE_AREA_ALIGN - 1, 0); 417 fpu_initialstate = uma_zalloc(fpu_save_area_zone, M_WAITOK | M_ZERO); 418 if (use_xsave) { 419 max_ext_n = flsl(xsave_mask); 420 xsave_area_desc = malloc(max_ext_n * sizeof(struct 421 xsave_area_elm_descr), M_DEVBUF, M_WAITOK | M_ZERO); 422 } 423 424 cpu_thread_alloc(&thread0); 425 426 saveintr = intr_disable(); 427 fpu_enable(); 428 429 fpusave_fxsave(fpu_initialstate); 430 if (fpu_initialstate->sv_env.en_mxcsr_mask) 431 cpu_mxcsr_mask = fpu_initialstate->sv_env.en_mxcsr_mask; 432 else 433 cpu_mxcsr_mask = 0xFFBF; 434 435 /* 436 * The fninit instruction does not modify XMM registers or x87 437 * registers (MM/ST). The fpusave call dumped the garbage 438 * contained in the registers after reset to the initial state 439 * saved. Clear XMM and x87 registers file image to make the 440 * startup program state and signal handler XMM/x87 register 441 * content predictable. 442 */ 443 bzero(fpu_initialstate->sv_fp, sizeof(fpu_initialstate->sv_fp)); 444 bzero(fpu_initialstate->sv_xmm, sizeof(fpu_initialstate->sv_xmm)); 445 446 /* 447 * Create a table describing the layout of the CPU Extended 448 * Save Area. See Intel SDM rev. 075 Vol. 1 13.4.1 "Legacy 449 * Region of an XSAVE Area" for the source of offsets/sizes. 450 */ 451 if (use_xsave) { 452 xstate_bv = (uint64_t *)((char *)(fpu_initialstate + 1) + 453 offsetof(struct xstate_hdr, xstate_bv)); 454 *xstate_bv = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE; 455 456 /* x87 state */ 457 xsave_area_desc[0].offset = 0; 458 xsave_area_desc[0].size = 160; 459 /* XMM */ 460 xsave_area_desc[1].offset = 160; 461 xsave_area_desc[1].size = 416 - 160; 462 463 for (i = 2; i < max_ext_n; i++) { 464 cpuid_count(0xd, i, cp); 465 xsave_area_desc[i].offset = cp[1]; 466 xsave_area_desc[i].size = cp[0]; 467 } 468 } 469 470 fpu_disable(); 471 intr_restore(saveintr); 472 } 473 /* EFIRT needs this to be initialized before we can enter our EFI environment */ 474 SYSINIT(fpuinitstate, SI_SUB_CPU, SI_ORDER_ANY, fpuinitstate, NULL); 475 476 /* 477 * Free coprocessor (if we have it). 478 */ 479 void 480 fpuexit(struct thread *td) 481 { 482 483 critical_enter(); 484 if (curthread == PCPU_GET(fpcurthread)) { 485 fpu_enable(); 486 fpusave(curpcb->pcb_save); 487 fpu_disable(); 488 PCPU_SET(fpcurthread, NULL); 489 } 490 critical_exit(); 491 } 492 493 int 494 fpuformat(void) 495 { 496 497 return (_MC_FPFMT_XMM); 498 } 499 500 /* 501 * The following mechanism is used to ensure that the FPE_... value 502 * that is passed as a trapcode to the signal handler of the user 503 * process does not have more than one bit set. 504 * 505 * Multiple bits may be set if the user process modifies the control 506 * word while a status word bit is already set. While this is a sign 507 * of bad coding, we have no choice than to narrow them down to one 508 * bit, since we must not send a trapcode that is not exactly one of 509 * the FPE_ macros. 510 * 511 * The mechanism has a static table with 127 entries. Each combination 512 * of the 7 FPU status word exception bits directly translates to a 513 * position in this table, where a single FPE_... value is stored. 514 * This FPE_... value stored there is considered the "most important" 515 * of the exception bits and will be sent as the signal code. The 516 * precedence of the bits is based upon Intel Document "Numerical 517 * Applications", Chapter "Special Computational Situations". 518 * 519 * The macro to choose one of these values does these steps: 1) Throw 520 * away status word bits that cannot be masked. 2) Throw away the bits 521 * currently masked in the control word, assuming the user isn't 522 * interested in them anymore. 3) Reinsert status word bit 7 (stack 523 * fault) if it is set, which cannot be masked but must be presered. 524 * 4) Use the remaining bits to point into the trapcode table. 525 * 526 * The 6 maskable bits in order of their preference, as stated in the 527 * above referenced Intel manual: 528 * 1 Invalid operation (FP_X_INV) 529 * 1a Stack underflow 530 * 1b Stack overflow 531 * 1c Operand of unsupported format 532 * 1d SNaN operand. 533 * 2 QNaN operand (not an exception, irrelavant here) 534 * 3 Any other invalid-operation not mentioned above or zero divide 535 * (FP_X_INV, FP_X_DZ) 536 * 4 Denormal operand (FP_X_DNML) 537 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 538 * 6 Inexact result (FP_X_IMP) 539 */ 540 static char fpetable[128] = { 541 0, 542 FPE_FLTINV, /* 1 - INV */ 543 FPE_FLTUND, /* 2 - DNML */ 544 FPE_FLTINV, /* 3 - INV | DNML */ 545 FPE_FLTDIV, /* 4 - DZ */ 546 FPE_FLTINV, /* 5 - INV | DZ */ 547 FPE_FLTDIV, /* 6 - DNML | DZ */ 548 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 549 FPE_FLTOVF, /* 8 - OFL */ 550 FPE_FLTINV, /* 9 - INV | OFL */ 551 FPE_FLTUND, /* A - DNML | OFL */ 552 FPE_FLTINV, /* B - INV | DNML | OFL */ 553 FPE_FLTDIV, /* C - DZ | OFL */ 554 FPE_FLTINV, /* D - INV | DZ | OFL */ 555 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 556 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 557 FPE_FLTUND, /* 10 - UFL */ 558 FPE_FLTINV, /* 11 - INV | UFL */ 559 FPE_FLTUND, /* 12 - DNML | UFL */ 560 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 561 FPE_FLTDIV, /* 14 - DZ | UFL */ 562 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 563 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 564 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 565 FPE_FLTOVF, /* 18 - OFL | UFL */ 566 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 567 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 568 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 569 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 570 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 571 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 572 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 573 FPE_FLTRES, /* 20 - IMP */ 574 FPE_FLTINV, /* 21 - INV | IMP */ 575 FPE_FLTUND, /* 22 - DNML | IMP */ 576 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 577 FPE_FLTDIV, /* 24 - DZ | IMP */ 578 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 579 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 580 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 581 FPE_FLTOVF, /* 28 - OFL | IMP */ 582 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 583 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 584 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 585 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 586 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 587 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 588 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 589 FPE_FLTUND, /* 30 - UFL | IMP */ 590 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 591 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 592 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 593 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 594 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 595 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 596 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 597 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 598 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 599 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 600 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 601 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 602 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 603 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 604 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 605 FPE_FLTSUB, /* 40 - STK */ 606 FPE_FLTSUB, /* 41 - INV | STK */ 607 FPE_FLTUND, /* 42 - DNML | STK */ 608 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 609 FPE_FLTDIV, /* 44 - DZ | STK */ 610 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 611 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 612 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 613 FPE_FLTOVF, /* 48 - OFL | STK */ 614 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 615 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 616 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 617 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 618 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 619 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 620 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 621 FPE_FLTUND, /* 50 - UFL | STK */ 622 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 623 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 624 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 625 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 626 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 627 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 628 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 629 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 630 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 631 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 632 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 633 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 634 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 635 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 636 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 637 FPE_FLTRES, /* 60 - IMP | STK */ 638 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 639 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 640 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 641 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 642 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 643 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 644 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 645 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 646 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 647 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 648 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 649 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 650 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 651 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 652 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 653 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 654 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 655 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 656 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 657 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 658 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 659 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 660 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 661 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 662 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 663 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 664 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 665 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 666 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 667 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 668 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 669 }; 670 671 /* 672 * Read the FP status and control words, then generate si_code value 673 * for SIGFPE. The error code chosen will be one of the 674 * FPE_... macros. It will be sent as the second argument to old 675 * BSD-style signal handlers and as "siginfo_t->si_code" (second 676 * argument) to SA_SIGINFO signal handlers. 677 * 678 * Some time ago, we cleared the x87 exceptions with FNCLEX there. 679 * Clearing exceptions was necessary mainly to avoid IRQ13 bugs. The 680 * usermode code which understands the FPU hardware enough to enable 681 * the exceptions, can also handle clearing the exception state in the 682 * handler. The only consequence of not clearing the exception is the 683 * rethrow of the SIGFPE on return from the signal handler and 684 * reexecution of the corresponding instruction. 685 * 686 * For XMM traps, the exceptions were never cleared. 687 */ 688 int 689 fputrap_x87(void) 690 { 691 struct savefpu *pcb_save; 692 u_short control, status; 693 694 critical_enter(); 695 696 /* 697 * Interrupt handling (for another interrupt) may have pushed the 698 * state to memory. Fetch the relevant parts of the state from 699 * wherever they are. 700 */ 701 if (PCPU_GET(fpcurthread) != curthread) { 702 pcb_save = curpcb->pcb_save; 703 control = pcb_save->sv_env.en_cw; 704 status = pcb_save->sv_env.en_sw; 705 } else { 706 fnstcw(&control); 707 fnstsw(&status); 708 } 709 710 critical_exit(); 711 return (fpetable[status & ((~control & 0x3f) | 0x40)]); 712 } 713 714 int 715 fputrap_sse(void) 716 { 717 u_int mxcsr; 718 719 critical_enter(); 720 if (PCPU_GET(fpcurthread) != curthread) 721 mxcsr = curpcb->pcb_save->sv_env.en_mxcsr; 722 else 723 stmxcsr(&mxcsr); 724 critical_exit(); 725 return (fpetable[(mxcsr & (~mxcsr >> 7)) & 0x3f]); 726 } 727 728 static void 729 restore_fpu_curthread(struct thread *td) 730 { 731 struct pcb *pcb; 732 733 /* 734 * Record new context early in case frstor causes a trap. 735 */ 736 PCPU_SET(fpcurthread, td); 737 738 fpu_enable(); 739 fpu_clean_state(); 740 pcb = td->td_pcb; 741 742 if ((pcb->pcb_flags & PCB_FPUINITDONE) == 0) { 743 /* 744 * This is the first time this thread has used the FPU or 745 * the PCB doesn't contain a clean FPU state. Explicitly 746 * load an initial state. 747 * 748 * We prefer to restore the state from the actual save 749 * area in PCB instead of directly loading from 750 * fpu_initialstate, to ignite the XSAVEOPT 751 * tracking engine. 752 */ 753 bcopy(fpu_initialstate, pcb->pcb_save, 754 cpu_max_ext_state_size); 755 fpurestore(pcb->pcb_save); 756 if (pcb->pcb_initial_fpucw != __INITIAL_FPUCW__) 757 fldcw(pcb->pcb_initial_fpucw); 758 if (PCB_USER_FPU(pcb)) 759 set_pcb_flags(pcb, PCB_FPUINITDONE | 760 PCB_USERFPUINITDONE); 761 else 762 set_pcb_flags(pcb, PCB_FPUINITDONE); 763 } else 764 fpurestore(pcb->pcb_save); 765 } 766 767 /* 768 * Device Not Available (DNA, #NM) exception handler. 769 * 770 * It would be better to switch FP context here (if curthread != 771 * fpcurthread) and not necessarily for every context switch, but it 772 * is too hard to access foreign pcb's. 773 */ 774 void 775 fpudna(void) 776 { 777 struct thread *td; 778 779 td = curthread; 780 /* 781 * This handler is entered with interrupts enabled, so context 782 * switches may occur before critical_enter() is executed. If 783 * a context switch occurs, then when we regain control, our 784 * state will have been completely restored. The CPU may 785 * change underneath us, but the only part of our context that 786 * lives in the CPU is CR0.TS and that will be "restored" by 787 * setting it on the new CPU. 788 */ 789 critical_enter(); 790 791 KASSERT((curpcb->pcb_flags & PCB_FPUNOSAVE) == 0, 792 ("fpudna while in fpu_kern_enter(FPU_KERN_NOCTX)")); 793 if (__predict_false(PCPU_GET(fpcurthread) == td)) { 794 /* 795 * Some virtual machines seems to set %cr0.TS at 796 * arbitrary moments. Silently clear the TS bit 797 * regardless of the eager/lazy FPU context switch 798 * mode. 799 */ 800 fpu_enable(); 801 } else { 802 if (__predict_false(PCPU_GET(fpcurthread) != NULL)) { 803 panic( 804 "fpudna: fpcurthread = %p (%d), curthread = %p (%d)\n", 805 PCPU_GET(fpcurthread), 806 PCPU_GET(fpcurthread)->td_tid, td, td->td_tid); 807 } 808 restore_fpu_curthread(td); 809 } 810 critical_exit(); 811 } 812 813 void fpu_activate_sw(struct thread *td); /* Called from the context switch */ 814 void 815 fpu_activate_sw(struct thread *td) 816 { 817 818 if ((td->td_pflags & TDP_KTHREAD) != 0 || !PCB_USER_FPU(td->td_pcb)) { 819 PCPU_SET(fpcurthread, NULL); 820 fpu_disable(); 821 } else if (PCPU_GET(fpcurthread) != td) { 822 restore_fpu_curthread(td); 823 } 824 } 825 826 void 827 fpudrop(void) 828 { 829 struct thread *td; 830 831 td = PCPU_GET(fpcurthread); 832 KASSERT(td == curthread, ("fpudrop: fpcurthread != curthread")); 833 CRITICAL_ASSERT(td); 834 PCPU_SET(fpcurthread, NULL); 835 clear_pcb_flags(td->td_pcb, PCB_FPUINITDONE); 836 fpu_disable(); 837 } 838 839 /* 840 * Get the user state of the FPU into pcb->pcb_user_save without 841 * dropping ownership (if possible). It returns the FPU ownership 842 * status. 843 */ 844 int 845 fpugetregs(struct thread *td) 846 { 847 struct pcb *pcb; 848 uint64_t *xstate_bv, bit; 849 char *sa; 850 int max_ext_n, i, owned; 851 852 pcb = td->td_pcb; 853 critical_enter(); 854 if ((pcb->pcb_flags & PCB_USERFPUINITDONE) == 0) { 855 bcopy(fpu_initialstate, get_pcb_user_save_pcb(pcb), 856 cpu_max_ext_state_size); 857 get_pcb_user_save_pcb(pcb)->sv_env.en_cw = 858 pcb->pcb_initial_fpucw; 859 fpuuserinited(td); 860 critical_exit(); 861 return (_MC_FPOWNED_PCB); 862 } 863 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) { 864 fpusave(get_pcb_user_save_pcb(pcb)); 865 owned = _MC_FPOWNED_FPU; 866 } else { 867 owned = _MC_FPOWNED_PCB; 868 } 869 if (use_xsave) { 870 /* 871 * Handle partially saved state. 872 */ 873 sa = (char *)get_pcb_user_save_pcb(pcb); 874 xstate_bv = (uint64_t *)(sa + sizeof(struct savefpu) + 875 offsetof(struct xstate_hdr, xstate_bv)); 876 max_ext_n = flsl(xsave_mask); 877 for (i = 0; i < max_ext_n; i++) { 878 bit = 1ULL << i; 879 if ((xsave_mask & bit) == 0 || (*xstate_bv & bit) != 0) 880 continue; 881 bcopy((char *)fpu_initialstate + 882 xsave_area_desc[i].offset, 883 sa + xsave_area_desc[i].offset, 884 xsave_area_desc[i].size); 885 *xstate_bv |= bit; 886 } 887 } 888 critical_exit(); 889 return (owned); 890 } 891 892 void 893 fpuuserinited(struct thread *td) 894 { 895 struct pcb *pcb; 896 897 CRITICAL_ASSERT(td); 898 pcb = td->td_pcb; 899 if (PCB_USER_FPU(pcb)) 900 set_pcb_flags(pcb, 901 PCB_FPUINITDONE | PCB_USERFPUINITDONE); 902 else 903 set_pcb_flags(pcb, PCB_FPUINITDONE); 904 } 905 906 int 907 fpusetxstate(struct thread *td, char *xfpustate, size_t xfpustate_size) 908 { 909 struct xstate_hdr *hdr, *ehdr; 910 size_t len, max_len; 911 uint64_t bv; 912 913 /* XXXKIB should we clear all extended state in xstate_bv instead ? */ 914 if (xfpustate == NULL) 915 return (0); 916 if (!use_xsave) 917 return (EOPNOTSUPP); 918 919 len = xfpustate_size; 920 if (len < sizeof(struct xstate_hdr)) 921 return (EINVAL); 922 max_len = cpu_max_ext_state_size - sizeof(struct savefpu); 923 if (len > max_len) 924 return (EINVAL); 925 926 ehdr = (struct xstate_hdr *)xfpustate; 927 bv = ehdr->xstate_bv; 928 929 /* 930 * Avoid #gp. 931 */ 932 if (bv & ~xsave_mask) 933 return (EINVAL); 934 935 hdr = (struct xstate_hdr *)(get_pcb_user_save_td(td) + 1); 936 937 hdr->xstate_bv = bv; 938 bcopy(xfpustate + sizeof(struct xstate_hdr), 939 (char *)(hdr + 1), len - sizeof(struct xstate_hdr)); 940 941 return (0); 942 } 943 944 /* 945 * Set the state of the FPU. 946 */ 947 int 948 fpusetregs(struct thread *td, struct savefpu *addr, char *xfpustate, 949 size_t xfpustate_size) 950 { 951 struct pcb *pcb; 952 int error; 953 954 addr->sv_env.en_mxcsr &= cpu_mxcsr_mask; 955 pcb = td->td_pcb; 956 error = 0; 957 critical_enter(); 958 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) { 959 error = fpusetxstate(td, xfpustate, xfpustate_size); 960 if (error == 0) { 961 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr)); 962 fpurestore(get_pcb_user_save_td(td)); 963 set_pcb_flags(pcb, PCB_FPUINITDONE | 964 PCB_USERFPUINITDONE); 965 } 966 } else { 967 error = fpusetxstate(td, xfpustate, xfpustate_size); 968 if (error == 0) { 969 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr)); 970 fpuuserinited(td); 971 } 972 } 973 critical_exit(); 974 return (error); 975 } 976 977 /* 978 * On AuthenticAMD processors, the fxrstor instruction does not restore 979 * the x87's stored last instruction pointer, last data pointer, and last 980 * opcode values, except in the rare case in which the exception summary 981 * (ES) bit in the x87 status word is set to 1. 982 * 983 * In order to avoid leaking this information across processes, we clean 984 * these values by performing a dummy load before executing fxrstor(). 985 */ 986 static void 987 fpu_clean_state(void) 988 { 989 static float dummy_variable = 0.0; 990 u_short status; 991 992 /* 993 * Clear the ES bit in the x87 status word if it is currently 994 * set, in order to avoid causing a fault in the upcoming load. 995 */ 996 fnstsw(&status); 997 if (status & 0x80) 998 fnclex(); 999 1000 /* 1001 * Load the dummy variable into the x87 stack. This mangles 1002 * the x87 stack, but we don't care since we're about to call 1003 * fxrstor() anyway. 1004 */ 1005 __asm __volatile("ffree %%st(7); flds %0" : : "m" (dummy_variable)); 1006 } 1007 1008 /* 1009 * This really sucks. We want the acpi version only, but it requires 1010 * the isa_if.h file in order to get the definitions. 1011 */ 1012 #include "opt_isa.h" 1013 #ifdef DEV_ISA 1014 #include <isa/isavar.h> 1015 /* 1016 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI. 1017 */ 1018 static struct isa_pnp_id fpupnp_ids[] = { 1019 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */ 1020 { 0 } 1021 }; 1022 1023 static int 1024 fpupnp_probe(device_t dev) 1025 { 1026 int result; 1027 1028 result = ISA_PNP_PROBE(device_get_parent(dev), dev, fpupnp_ids); 1029 if (result <= 0) 1030 device_quiet(dev); 1031 return (result); 1032 } 1033 1034 static int 1035 fpupnp_attach(device_t dev) 1036 { 1037 1038 return (0); 1039 } 1040 1041 static device_method_t fpupnp_methods[] = { 1042 /* Device interface */ 1043 DEVMETHOD(device_probe, fpupnp_probe), 1044 DEVMETHOD(device_attach, fpupnp_attach), 1045 DEVMETHOD(device_detach, bus_generic_detach), 1046 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1047 DEVMETHOD(device_suspend, bus_generic_suspend), 1048 DEVMETHOD(device_resume, bus_generic_resume), 1049 { 0, 0 } 1050 }; 1051 1052 static driver_t fpupnp_driver = { 1053 "fpupnp", 1054 fpupnp_methods, 1055 1, /* no softc */ 1056 }; 1057 1058 DRIVER_MODULE(fpupnp, acpi, fpupnp_driver, 0, 0); 1059 ISA_PNP_INFO(fpupnp_ids); 1060 #endif /* DEV_ISA */ 1061 1062 static MALLOC_DEFINE(M_FPUKERN_CTX, "fpukern_ctx", 1063 "Kernel contexts for FPU state"); 1064 1065 #define FPU_KERN_CTX_FPUINITDONE 0x01 1066 #define FPU_KERN_CTX_DUMMY 0x02 /* avoided save for the kern thread */ 1067 #define FPU_KERN_CTX_INUSE 0x04 1068 1069 struct fpu_kern_ctx { 1070 struct savefpu *prev; 1071 uint32_t flags; 1072 char hwstate1[]; 1073 }; 1074 1075 static inline size_t __pure2 1076 fpu_kern_alloc_sz(u_int max_est) 1077 { 1078 return (sizeof(struct fpu_kern_ctx) + XSAVE_AREA_ALIGN + max_est); 1079 } 1080 1081 static inline int __pure2 1082 fpu_kern_malloc_flags(u_int fpflags) 1083 { 1084 return (((fpflags & FPU_KERN_NOWAIT) ? M_NOWAIT : M_WAITOK) | M_ZERO); 1085 } 1086 1087 struct fpu_kern_ctx * 1088 fpu_kern_alloc_ctx_domain(int domain, u_int flags) 1089 { 1090 return (malloc_domainset(fpu_kern_alloc_sz(cpu_max_ext_state_size), 1091 M_FPUKERN_CTX, DOMAINSET_PREF(domain), 1092 fpu_kern_malloc_flags(flags))); 1093 } 1094 1095 struct fpu_kern_ctx * 1096 fpu_kern_alloc_ctx(u_int flags) 1097 { 1098 return (malloc(fpu_kern_alloc_sz(cpu_max_ext_state_size), 1099 M_FPUKERN_CTX, fpu_kern_malloc_flags(flags))); 1100 } 1101 1102 void 1103 fpu_kern_free_ctx(struct fpu_kern_ctx *ctx) 1104 { 1105 1106 KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) == 0, ("free'ing inuse ctx")); 1107 /* XXXKIB clear the memory ? */ 1108 free(ctx, M_FPUKERN_CTX); 1109 } 1110 1111 static struct savefpu * 1112 fpu_kern_ctx_savefpu(struct fpu_kern_ctx *ctx) 1113 { 1114 vm_offset_t p; 1115 1116 p = (vm_offset_t)&ctx->hwstate1; 1117 p = roundup2(p, XSAVE_AREA_ALIGN); 1118 return ((struct savefpu *)p); 1119 } 1120 1121 void 1122 fpu_kern_enter(struct thread *td, struct fpu_kern_ctx *ctx, u_int flags) 1123 { 1124 struct pcb *pcb; 1125 1126 pcb = td->td_pcb; 1127 KASSERT((flags & FPU_KERN_NOCTX) != 0 || ctx != NULL, 1128 ("ctx is required when !FPU_KERN_NOCTX")); 1129 KASSERT(ctx == NULL || (ctx->flags & FPU_KERN_CTX_INUSE) == 0, 1130 ("using inuse ctx")); 1131 KASSERT((pcb->pcb_flags & PCB_FPUNOSAVE) == 0, 1132 ("recursive fpu_kern_enter while in PCB_FPUNOSAVE state")); 1133 1134 if ((flags & FPU_KERN_NOCTX) != 0) { 1135 critical_enter(); 1136 fpu_enable(); 1137 if (curthread == PCPU_GET(fpcurthread)) { 1138 fpusave(curpcb->pcb_save); 1139 PCPU_SET(fpcurthread, NULL); 1140 } else { 1141 KASSERT(PCPU_GET(fpcurthread) == NULL, 1142 ("invalid fpcurthread")); 1143 } 1144 1145 /* 1146 * This breaks XSAVEOPT tracker, but 1147 * PCB_FPUNOSAVE state is supposed to never need to 1148 * save FPU context at all. 1149 */ 1150 fpurestore(fpu_initialstate); 1151 set_pcb_flags(pcb, PCB_KERNFPU | PCB_FPUNOSAVE | 1152 PCB_FPUINITDONE); 1153 return; 1154 } 1155 if ((flags & FPU_KERN_KTHR) != 0 && is_fpu_kern_thread(0)) { 1156 ctx->flags = FPU_KERN_CTX_DUMMY | FPU_KERN_CTX_INUSE; 1157 return; 1158 } 1159 critical_enter(); 1160 KASSERT(!PCB_USER_FPU(pcb) || pcb->pcb_save == 1161 get_pcb_user_save_pcb(pcb), ("mangled pcb_save")); 1162 ctx->flags = FPU_KERN_CTX_INUSE; 1163 if ((pcb->pcb_flags & PCB_FPUINITDONE) != 0) 1164 ctx->flags |= FPU_KERN_CTX_FPUINITDONE; 1165 fpuexit(td); 1166 ctx->prev = pcb->pcb_save; 1167 pcb->pcb_save = fpu_kern_ctx_savefpu(ctx); 1168 set_pcb_flags(pcb, PCB_KERNFPU); 1169 clear_pcb_flags(pcb, PCB_FPUINITDONE); 1170 critical_exit(); 1171 } 1172 1173 int 1174 fpu_kern_leave(struct thread *td, struct fpu_kern_ctx *ctx) 1175 { 1176 struct pcb *pcb; 1177 1178 pcb = td->td_pcb; 1179 1180 if ((pcb->pcb_flags & PCB_FPUNOSAVE) != 0) { 1181 KASSERT(ctx == NULL, ("non-null ctx after FPU_KERN_NOCTX")); 1182 KASSERT(PCPU_GET(fpcurthread) == NULL, 1183 ("non-NULL fpcurthread for PCB_FPUNOSAVE")); 1184 CRITICAL_ASSERT(td); 1185 1186 clear_pcb_flags(pcb, PCB_FPUNOSAVE | PCB_FPUINITDONE); 1187 fpu_disable(); 1188 } else { 1189 KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) != 0, 1190 ("leaving not inuse ctx")); 1191 ctx->flags &= ~FPU_KERN_CTX_INUSE; 1192 1193 if (is_fpu_kern_thread(0) && 1194 (ctx->flags & FPU_KERN_CTX_DUMMY) != 0) 1195 return (0); 1196 KASSERT((ctx->flags & FPU_KERN_CTX_DUMMY) == 0, 1197 ("dummy ctx")); 1198 critical_enter(); 1199 if (curthread == PCPU_GET(fpcurthread)) 1200 fpudrop(); 1201 pcb->pcb_save = ctx->prev; 1202 } 1203 1204 if (pcb->pcb_save == get_pcb_user_save_pcb(pcb)) { 1205 if ((pcb->pcb_flags & PCB_USERFPUINITDONE) != 0) { 1206 set_pcb_flags(pcb, PCB_FPUINITDONE); 1207 if ((pcb->pcb_flags & PCB_KERNFPU_THR) == 0) 1208 clear_pcb_flags(pcb, PCB_KERNFPU); 1209 } else if ((pcb->pcb_flags & PCB_KERNFPU_THR) == 0) 1210 clear_pcb_flags(pcb, PCB_FPUINITDONE | PCB_KERNFPU); 1211 } else { 1212 if ((ctx->flags & FPU_KERN_CTX_FPUINITDONE) != 0) 1213 set_pcb_flags(pcb, PCB_FPUINITDONE); 1214 else 1215 clear_pcb_flags(pcb, PCB_FPUINITDONE); 1216 KASSERT(!PCB_USER_FPU(pcb), ("unpaired fpu_kern_leave")); 1217 } 1218 critical_exit(); 1219 return (0); 1220 } 1221 1222 int 1223 fpu_kern_thread(u_int flags) 1224 { 1225 1226 KASSERT((curthread->td_pflags & TDP_KTHREAD) != 0, 1227 ("Only kthread may use fpu_kern_thread")); 1228 KASSERT(curpcb->pcb_save == get_pcb_user_save_pcb(curpcb), 1229 ("mangled pcb_save")); 1230 KASSERT(PCB_USER_FPU(curpcb), ("recursive call")); 1231 1232 set_pcb_flags(curpcb, PCB_KERNFPU | PCB_KERNFPU_THR); 1233 return (0); 1234 } 1235 1236 int 1237 is_fpu_kern_thread(u_int flags) 1238 { 1239 1240 if ((curthread->td_pflags & TDP_KTHREAD) == 0) 1241 return (0); 1242 return ((curpcb->pcb_flags & PCB_KERNFPU_THR) != 0); 1243 } 1244 1245 /* 1246 * FPU save area alloc/free/init utility routines 1247 */ 1248 struct savefpu * 1249 fpu_save_area_alloc(void) 1250 { 1251 1252 return (uma_zalloc(fpu_save_area_zone, M_WAITOK)); 1253 } 1254 1255 void 1256 fpu_save_area_free(struct savefpu *fsa) 1257 { 1258 1259 uma_zfree(fpu_save_area_zone, fsa); 1260 } 1261 1262 void 1263 fpu_save_area_reset(struct savefpu *fsa) 1264 { 1265 1266 bcopy(fpu_initialstate, fsa, cpu_max_ext_state_size); 1267 } 1268