1.\" 2.\" Copyright (c) 2005 Bruce M Simpson <bms@FreeBSD.org> 3.\" All rights reserved. 4.\" 5.\" Redistribution and use in source and binary forms, with or without 6.\" modification, are permitted provided that the following conditions 7.\" are met: 8.\" 1. Redistributions of source code must retain the above copyright 9.\" notice, this list of conditions and the following disclaimer. 10.\" 2. Redistributions in binary form must reproduce the above copyright 11.\" notice, this list of conditions and the following disclaimer in the 12.\" documentation and/or other materials provided with the distribution. 13.\" 14.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24.\" SUCH DAMAGE. 25.\" 26.\" $FreeBSD$ 27.\" 28.Dd July 8, 2015 29.Dt PCI 9 30.Os 31.Sh NAME 32.Nm pci , 33.Nm pci_alloc_msi , 34.Nm pci_alloc_msix , 35.Nm pci_disable_busmaster , 36.Nm pci_disable_io , 37.Nm pci_enable_busmaster , 38.Nm pci_enable_io , 39.Nm pci_find_bsf , 40.Nm pci_find_cap , 41.Nm pci_find_dbsf , 42.Nm pci_find_device , 43.Nm pci_find_extcap , 44.Nm pci_find_htcap , 45.Nm pci_get_max_read_req , 46.Nm pci_get_powerstate , 47.Nm pci_get_vpd_ident , 48.Nm pci_get_vpd_readonly , 49.Nm pci_iov_attach , 50.Nm pci_iov_detach , 51.Nm pci_msi_count , 52.Nm pci_msix_count , 53.Nm pci_pending_msix , 54.Nm pci_read_config , 55.Nm pci_release_msi , 56.Nm pci_remap_msix , 57.Nm pci_restore_state , 58.Nm pci_save_state , 59.Nm pci_set_max_read_req , 60.Nm pci_set_powerstate , 61.Nm pci_write_config 62.Nd PCI bus interface 63.Sh SYNOPSIS 64.In sys/bus.h 65.In dev/pci/pcireg.h 66.In dev/pci/pcivar.h 67.Ft int 68.Fn pci_alloc_msi "device_t dev" "int *count" 69.Ft int 70.Fn pci_alloc_msix "device_t dev" "int *count" 71.Ft int 72.Fn pci_disable_busmaster "device_t dev" 73.Ft int 74.Fn pci_disable_io "device_t dev" "int space" 75.Ft int 76.Fn pci_enable_busmaster "device_t dev" 77.Ft int 78.Fn pci_enable_io "device_t dev" "int space" 79.Ft device_t 80.Fn pci_find_bsf "uint8_t bus" "uint8_t slot" "uint8_t func" 81.Ft int 82.Fn pci_find_cap "device_t dev" "int capability" "int *capreg" 83.Ft device_t 84.Fn pci_find_dbsf "uint32_t domain" "uint8_t bus" "uint8_t slot" "uint8_t func" 85.Ft device_t 86.Fn pci_find_device "uint16_t vendor" "uint16_t device" 87.Ft int 88.Fn pci_find_extcap "device_t dev" "int capability" "int *capreg" 89.Ft int 90.Fn pci_find_htcap "device_t dev" "int capability" "int *capreg" 91.Ft int 92.Fn pci_get_max_read_req "device_t dev" 93.Ft int 94.Fn pci_get_powerstate "device_t dev" 95.Ft int 96.Fn pci_get_vpd_ident "device_t dev" "const char **identptr" 97.Ft int 98.Fn pci_get_vpd_readonly "device_t dev" "const char *kw" "const char **vptr" 99.Ft int 100.Fn pci_msi_count "device_t dev" 101.Ft int 102.Fn pci_msix_count "device_t dev" 103.Ft int 104.Fn pci_pending_msix "device_t dev" "u_int index" 105.Ft uint32_t 106.Fn pci_read_config "device_t dev" "int reg" "int width" 107.Ft int 108.Fn pci_release_msi "device_t dev" 109.Ft int 110.Fn pci_remap_msix "device_t dev" "int count" "const u_int *vectors" 111.Ft void 112.Fn pci_restore_state "device_t dev" 113.Ft void 114.Fn pci_save_state "device_t dev" 115.Ft int 116.Fn pci_set_max_read_req "device_t dev" "int size" 117.Ft int 118.Fn pci_set_powerstate "device_t dev" "int state" 119.Ft void 120.Fn pci_write_config "device_t dev" "int reg" "uint32_t val" "int width" 121.In dev/pci/pci_iov.h 122.Ft int 123.Fn pci_iov_attach "device_t dev" "nvlist_t *pf_schema" "nvlist_t *vf_schema" 124.Ft int 125.Fn pci_iov_detach "device_t dev" 126.Sh DESCRIPTION 127The 128.Nm 129set of functions are used for managing PCI devices. 130The functions are split into several groups: 131raw configuration access, 132locating devices, 133device information, 134device configuration, 135and 136message signaled interrupts. 137.Ss Raw Configuration Access 138The 139.Fn pci_read_config 140function is used to read data from the PCI configuration 141space of the device 142.Fa dev , 143at offset 144.Fa reg , 145with 146.Fa width 147specifying the size of the access. 148.Pp 149The 150.Fn pci_write_config 151function is used to write the value 152.Fa val 153to the PCI configuration 154space of the device 155.Fa dev , 156at offset 157.Fa reg , 158with 159.Fa width 160specifying the size of the access. 161.Pp 162.Em NOTE : 163Device drivers should only use these functions for functionality that 164is not available via another 165.Fn pci 166function. 167.Ss Locating Devices 168The 169.Fn pci_find_bsf 170function looks up the 171.Vt device_t 172of a PCI device, given its 173.Fa bus , 174.Fa slot , 175and 176.Fa func . 177The 178.Fa slot 179number actually refers to the number of the device on the bus, 180which does not necessarily indicate its geographic location 181in terms of a physical slot. 182Note that in case the system has multiple PCI domains, 183the 184.Fn pci_find_bsf 185function only searches the first one. 186Actually, it is equivalent to: 187.Bd -literal -offset indent 188pci_find_dbsf(0, bus, slot, func); 189.Ed 190.Pp 191The 192.Fn pci_find_dbsf 193function looks up the 194.Vt device_t 195of a PCI device, given its 196.Fa domain , 197.Fa bus , 198.Fa slot , 199and 200.Fa func . 201The 202.Fa slot 203number actually refers to the number of the device on the bus, 204which does not necessarily indicate its geographic location 205in terms of a physical slot. 206.Pp 207The 208.Fn pci_find_device 209function looks up the 210.Vt device_t 211of a PCI device, given its 212.Fa vendor 213and 214.Fa device 215IDs. 216Note that there can be multiple matches for this search; this function 217only returns the first matching device. 218.Ss Device Information 219The 220.Fn pci_find_cap 221function is used to locate the first instance of a PCI capability 222register set for the device 223.Fa dev . 224The capability to locate is specified by ID via 225.Fa capability . 226Constant macros of the form 227.Dv PCIY_xxx 228for standard capability IDs are defined in 229.In dev/pci/pcireg.h . 230If the capability is found, then 231.Fa *capreg 232is set to the offset in configuration space of the capability register set, 233and 234.Fn pci_find_cap 235returns zero. 236If the capability is not found or the device does not support capabilities, 237.Fn pci_find_cap 238returns an error. 239.Pp 240The 241.Fn pci_find_extcap 242function is used to locate the first instance of a PCI-express 243extended capability register set for the device 244.Fa dev . 245The extended capability to locate is specified by ID via 246.Fa capability . 247Constant macros of the form 248.Dv PCIZ_xxx 249for standard extended capability IDs are defined in 250.In dev/pci/pcireg.h . 251If the extended capability is found, then 252.Fa *capreg 253is set to the offset in configuration space of the extended capability 254register set, and 255.Fn pci_find_extcap 256returns zero. 257If the extended capability is not found or the device is not a 258PCI-express device, 259.Fn pci_find_extcap 260returns an error. 261.Pp 262The 263.Fn pci_find_htcap 264function is used to locate the first instance of a HyperTransport capability 265register set for the device 266.Fa dev . 267The capability to locate is specified by type via 268.Fa capability . 269Constant macros of the form 270.Dv PCIM_HTCAP_xxx 271for standard HyperTransport capability types are defined in 272.In dev/pci/pcireg.h . 273If the capability is found, then 274.Fa *capreg 275is set to the offset in configuration space of the capability register set, 276and 277.Fn pci_find_htcap 278returns zero. 279If the capability is not found or the device is not a HyperTransport device, 280.Fn pci_find_htcap 281returns an error. 282.Pp 283The 284.Fn pci_get_vpd_ident 285function is used to fetch a device's Vital Product Data 286.Pq VPD 287identifier string. 288If the device 289.Fa dev 290supports VPD and provides an identifier string, 291then 292.Fa *identptr 293is set to point at a read-only, null-terminated copy of the identifier 294string, 295and 296.Fn pci_get_vpd_ident 297returns zero. 298If the device does not support VPD or does not provide an identifier 299string, 300then 301.Fn pci_get_vpd_ident 302returns an error. 303.Pp 304The 305.Fn pci_get_vpd_readonly 306function is used to fetch the value of a single VPD read-only keyword 307for the device 308.Fa dev . 309The keyword to fetch is identified by the two character string 310.Fa kw . 311If the device supports VPD and provides a read-only value for the 312requested keyword, 313then 314.Fa *vptr 315is set to point at a read-only, null-terminated copy of the value, 316and 317.Fn pci_get_vpd_readonly 318returns zero. 319If the device does not support VPD or does not provide the requested 320keyword, 321then 322.Fn pci_get_vpd_readonly 323returns an error. 324.Ss Device Configuration 325The 326.Fn pci_enable_busmaster 327function enables PCI bus mastering for the device 328.Fa dev , 329by setting the 330.Dv PCIM_CMD_BUSMASTEREN 331bit in the 332.Dv PCIR_COMMAND 333register. 334The 335.Fn pci_disable_busmaster 336function clears this bit. 337.Pp 338The 339.Fn pci_enable_io 340function enables memory or I/O port address decoding for the device 341.Fa dev , 342by setting the 343.Dv PCIM_CMD_MEMEN 344or 345.Dv PCIM_CMD_PORTEN 346bit in the 347.Dv PCIR_COMMAND 348register appropriately. 349The 350.Fn pci_disable_io 351function clears the appropriate bit. 352The 353.Fa space 354argument specifies which resource is affected; this can be either 355.Dv SYS_RES_MEMORY 356or 357.Dv SYS_RES_IOPORT 358as appropriate. 359Device drivers should generally not use these routines directly. 360The PCI bus will enable decoding automatically when a 361.Dv SYS_RES_MEMORY 362or 363.Dv SYS_RES_IOPORT 364resource is activated via 365.Xr bus_alloc_resource 9 366or 367.Xr bus_activate_resource 9 . 368.Pp 369The 370.Fn pci_get_max_read_req 371function returns the current maximum read request size in bytes for a 372PCI-express device. 373If the 374.Fa dev 375device is not a PCI-express device, 376.Fn pci_get_max_read_req 377returns zero. 378.Pp 379The 380.Fn pci_set_max_read_req 381sets the PCI-express maximum read request size for 382.Fa dev . 383The requested 384.Fa size 385may be adjusted, 386and 387.Fn pci_set_max_read_req 388returns the actual size set in bytes. 389If the 390.Fa dev 391device is not a PCI-express device, 392.Fn pci_set_max_read_req 393returns zero. 394.Pp 395The 396.Fn pci_get_powerstate 397function returns the current power state of the device 398.Fa dev . 399If the device does not support power management capabilities, then the default 400state of 401.Dv PCI_POWERSTATE_D0 402is returned. 403The following power states are defined by PCI: 404.Bl -hang -width ".Dv PCI_POWERSTATE_UNKNOWN" 405.It Dv PCI_POWERSTATE_D0 406State in which device is on and running. 407It is receiving full power from the system and delivering 408full functionality to the user. 409.It Dv PCI_POWERSTATE_D1 410Class-specific low-power state in which device context may or 411may not be lost. 412Busses in this state cannot do anything to the bus, to 413force devices to lose context. 414.It Dv PCI_POWERSTATE_D2 415Class-specific low-power state in which device context may or 416may not be lost. 417Attains greater power savings than 418.Dv PCI_POWERSTATE_D1 . 419Busses in this state can cause devices to lose some context. 420Devices 421.Em must 422be prepared for the bus to be in this state or higher. 423.It Dv PCI_POWERSTATE_D3 424State in which the device is off and not running. 425Device context is lost, and power from the device can 426be removed. 427.It Dv PCI_POWERSTATE_UNKNOWN 428State of the device is unknown. 429.El 430.Pp 431The 432.Fn pci_set_powerstate 433function is used to transition the device 434.Fa dev 435to the PCI power state 436.Fa state . 437If the device does not support power management capabilities or 438it does not support the specific power state 439.Fa state , 440then the function will fail with 441.Er EOPNOTSUPP . 442.Pp 443The 444.Fn pci_iov_attach 445function is used to advertise that the given device 446.Pq and associated device driver 447supports PCI Single-Root I/O Virtualization 448.Pq SR-IOV . 449A driver that supports SR-IOV must implement the 450.Xr PCI_IOV_INIT 9 , 451.Xr PCI_IOV_ADD_VF 9 452and 453.Xr PCI_IOV_UNINIT 9 454methods. 455This function should be called during the 456.Xr DEVICE_ATTACH 9 457method. 458If this function returns an error, it is recommended that the device driver 459still successfully attaches, but runs with SR-IOV disabled. 460The 461.Fa pf_schema 462and 463.Fa vf_schema 464parameters are used to define what device-specific configuration parameters the 465device driver accepts when SR-IOV is enabled for the Physical Function 466.Pq PF 467and for individual Virtual Functions 468.Pq VFs 469respectively. 470See 471.Xr pci_iov_schema 9 472for details on how to construct the schema. 473If either the 474.Pa pf_schema 475or 476.Pa vf_schema 477is invalid or specifies parameter names that conflict with parameter names that 478are already in use, 479.Fn pci_iov_attach 480will return an error and SR-IOV will not be available on the PF device. 481If a driver does not accept configuration parameters for either the PF device 482or the VF devices, the driver must pass an empty schema for that device. 483The SR-IOV infrastructure takes ownership of the 484.Fa pf_schema 485and 486.Fa vf_schema 487and is responsible for freeing them. 488The driver must never free the schemas itself. 489.Pp 490The 491.Fn pci_iov_detach 492function is used to advise the SR-IOV infrastructure that the driver for the 493given device is attempting to detach and that all SR-IOV resources for the 494device must be released. 495This function must be called during the 496.Xr DEVICE_DETACH 9 497method if 498.Fn pci_iov_attach 499was successfully called on the device and 500.Fn pci_iov_detach 501has not subsequently been called on the device and returned no error. 502If this function returns an error, the 503.Xr DEVICE_DETACH 9 504method must fail and return an error, as detaching the PF driver while VF 505devices are active would cause system instability. 506This function is safe to call and will always succeed if 507.Fn pci_iov_attach 508previously failed with an error on the given device, or if 509.Fn pci_iov_attach 510was never called on the device. 511.Pp 512The 513.Fn pci_save_state 514and 515.Fn pci_restore_state 516functions can be used by a device driver to save and restore standard PCI 517config registers. 518The 519.Fn pci_save_state 520function must be invoked while the device has valid state before 521.Fn pci_restore_state 522can be used. 523If the device is not in the fully-powered state 524.Pq Dv PCI_POWERSTATE_D0 525when 526.Fn pci_restore_state 527is invoked, 528then the device will be transitioned to 529.Dv PCI_POWERSTATE_D0 530before any config registers are restored. 531.Ss Message Signaled Interrupts 532Message Signaled Interrupts 533.Pq MSI 534and 535Enhanced Message Signaled Interrupts 536.Pq MSI-X 537are PCI capabilities that provide an alternate method for PCI 538devices to signal interrupts. 539The legacy INTx interrupt is available to PCI devices as a 540.Dv SYS_RES_IRQ 541resource with a resource ID of zero. 542MSI and MSI-X interrupts are available to PCI devices as one or more 543.Dv SYS_RES_IRQ 544resources with resource IDs greater than zero. 545A driver must ask the PCI bus to allocate MSI or MSI-X interrupts 546using 547.Fn pci_alloc_msi 548or 549.Fn pci_alloc_msix 550before it can use MSI or MSI-X 551.Dv SYS_RES_IRQ 552resources. 553A driver is not allowed to use the legacy INTx 554.Dv SYS_RES_IRQ 555resource if MSI or MSI-X interrupts have been allocated, 556and attempts to allocate MSI or MSI-X interrupts will fail if the 557driver is currently using the legacy INTx 558.Dv SYS_RES_IRQ 559resource. 560A driver is only allowed to use either MSI or MSI-X, 561but not both. 562.Pp 563The 564.Fn pci_msi_count 565function returns the maximum number of MSI messages supported by the 566device 567.Fa dev . 568If the device does not support MSI, 569then 570.Fn pci_msi_count 571returns zero. 572.Pp 573The 574.Fn pci_alloc_msi 575function attempts to allocate 576.Fa *count 577MSI messages for the device 578.Fa dev . 579The 580.Fn pci_alloc_msi 581function may allocate fewer messages than requested for various 582reasons including requests for more messages than the device 583.Fa dev 584supports, 585or if the system has a shortage of available MSI messages. 586On success, 587.Fa *count 588is set to the number of messages allocated and 589.Fn pci_alloc_msi 590returns zero. 591The 592.Dv SYS_RES_IRQ 593resources for the allocated messages will be available at consecutive 594resource IDs beginning with one. 595If 596.Fn pci_alloc_msi 597is not able to allocate any messages, 598it returns an error. 599Note that MSI only supports message counts that are powers of two; 600requests to allocate a non-power of two count of messages will fail. 601.Pp 602The 603.Fn pci_release_msi 604function is used to release any allocated MSI or MSI-X messages back 605to the system. 606If any MSI or MSI-X 607.Dv SYS_RES_IRQ 608resources are allocated by the driver or have a configured interrupt 609handler, 610this function will fail with 611.Er EBUSY . 612The 613.Fn pci_release_msi 614function returns zero on success and an error on failure. 615.Pp 616The 617.Fn pci_msix_count 618function returns the maximum number of MSI-X messages supported by the 619device 620.Fa dev . 621If the device does not support MSI-X, 622then 623.Fn pci_msix_count 624returns zero. 625.Pp 626The 627.Fn pci_alloc_msix 628function attempts to allocate 629.Fa *count 630MSI-X messages for the device 631.Fa dev . 632The 633.Fn pci_alloc_msix 634function may allocate fewer messages than requested for various 635reasons including requests for more messages than the device 636.Fa dev 637supports, 638or if the system has a shortage of available MSI-X messages. 639On success, 640.Fa *count 641is set to the number of messages allocated and 642.Fn pci_alloc_msix 643returns zero. 644For MSI-X messages, 645the resource ID for each 646.Dv SYS_RES_IRQ 647resource identifies the index in the MSI-X table of the 648corresponding message. 649A resource ID of one maps to the first index of the MSI-X table; 650a resource ID two identifies the second index in the table, etc. 651The 652.Fn pci_alloc_msix 653function assigns the 654.Fa *count 655messages allocated to the first 656.Fa *count 657table indicies. 658If 659.Fn pci_alloc_msix 660is not able to allocate any messages, 661it returns an error. 662Unlike MSI, 663MSI-X does not require message counts that are powers of two. 664.Pp 665The 666.Fn pci_pending_msix 667function examines the 668.Fa dev 669device's Pending Bit Array 670.Pq PBA 671to determine the pending status of the MSI-X message at table index 672.Fa index . 673If the indicated message is pending, 674this function returns a non-zero value; 675otherwise, 676it returns zero. 677Passing an invalid 678.Fa index 679to this function will result in undefined behavior. 680.Pp 681As mentioned in the description of 682.Fn pci_alloc_msix , 683MSI-X messages are initially assigned to the first N table entries. 684A driver may use a different distribution of available messages to 685table entries via the 686.Fn pci_remap_msix 687function. 688Note that this function must be called after a successful call to 689.Fn pci_alloc_msix 690but before any of the 691.Dv SYS_RES_IRQ 692resources are allocated. 693The 694.Fn pci_remap_msix 695function returns zero on success, 696or an error on failure. 697.Pp 698The 699.Fa vectors 700array should contain 701.Fa count 702message vectors. 703The array maps directly to the MSI-X table in that the first entry in 704the array specifies the message used for the first entry in the MSI-X 705table, 706the second entry in the array corresponds to the second entry in the 707MSI-X table, 708etc. 709The vector value in each array index can either be zero to indicate 710that no message should be assigned to the corresponding MSI-X table entry, 711or it can be a number from one to N 712.Po 713where N is the count returned from the previous call to 714.Fn pci_alloc_msix 715.Pc 716to indicate which of the allocated messages should be assigned to the 717corresponding MSI-X table entry. 718.Pp 719If 720.Fn pci_remap_msix 721succeeds, 722each MSI-X table entry with a non-zero vector will have an associated 723.Dv SYS_RES_IRQ 724resource whose resource ID corresponds to the table index as described 725above for 726.Fn pci_alloc_msix . 727MSI-X table entries that with a vector of zero will not have an 728associated 729.Dv SYS_RES_IRQ 730resource. 731Additionally, 732if any of the original messages allocated by 733.Fn pci_alloc_msix 734are not used in the new distribution of messages in the MSI-X table, 735they will be released automatically. 736Note that if a driver wishes to use fewer messages than were allocated by 737.Fn pci_alloc_msix , 738the driver must use a single, contiguous range of messages beginning 739with one in the new distribution. 740The 741.Fn pci_remap_msix 742function will fail if this condition is not met. 743.Sh IMPLEMENTATION NOTES 744The 745.Vt pci_addr_t 746type varies according to the size of the PCI bus address 747space on the target architecture. 748.Sh SEE ALSO 749.Xr pci 4 , 750.Xr pciconf 8 , 751.Xr bus_alloc_resource 9 , 752.Xr bus_dma 9 , 753.Xr bus_release_resource 9 , 754.Xr bus_setup_intr 9 , 755.Xr bus_teardown_intr 9 , 756.Xr devclass 9 , 757.Xr device 9 , 758.Xr driver 9 , 759.Xr rman 9 760.Rs 761.%B FreeBSD Developers' Handbook 762.%T NewBus 763.%U http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/developers-handbook/ 764.Re 765.Rs 766.%A Shanley 767.%A Anderson 768.%B PCI System Architecture 769.%N 2nd Edition 770.%I Addison-Wesley 771.%O ISBN 0-201-30974-2 772.Re 773.Sh AUTHORS 774.An -nosplit 775This manual page was written by 776.An Bruce M Simpson Aq Mt bms@FreeBSD.org 777and 778.An John Baldwin Aq Mt jhb@FreeBSD.org . 779.Sh BUGS 780The kernel PCI code has a number of references to 781.Dq "slot numbers" . 782These do not refer to the geographic location of PCI devices, 783but to the device number assigned by the combination of the PCI IDSEL 784mechanism and the platform firmware. 785This should be taken note of when working with the kernel PCI code. 786